ARM GAS  /tmp/ccTxDPsK.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_gpio.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Library/src/lcm32f06x_gpio.c"
  16              		.section	.text.GPIO_DeInit,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	GPIO_DeInit
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	GPIO_DeInit:
  25              	.LVL0:
  26              	.LFB45:
   1:Library/src/lcm32f06x_gpio.c **** /**
   2:Library/src/lcm32f06x_gpio.c ****   ******************************************************************************
   3:Library/src/lcm32f06x_gpio.c ****   * @file    lcm32f06x_gpio.c 
   4:Library/src/lcm32f06x_gpio.c ****   * @author  System R&D Team
   5:Library/src/lcm32f06x_gpio.c ****   * @version V2.0.2
   6:Library/src/lcm32f06x_gpio.c ****   * @date    10-April-2025
   7:Library/src/lcm32f06x_gpio.c ****   * @brief   This file provides all the GPIO firmware functions.
   8:Library/src/lcm32f06x_gpio.c ****   ******************************************************************************
   9:Library/src/lcm32f06x_gpio.c ****   * @attention
  10:Library/src/lcm32f06x_gpio.c ****   *
  11:Library/src/lcm32f06x_gpio.c ****   * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  12:Library/src/lcm32f06x_gpio.c ****   * All rights reserved.
  13:Library/src/lcm32f06x_gpio.c ****   *
  14:Library/src/lcm32f06x_gpio.c ****   * This software is licensed under terms that can be found in the LICENSE file
  15:Library/src/lcm32f06x_gpio.c ****   * in the root directory of this software component.
  16:Library/src/lcm32f06x_gpio.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  17:Library/src/lcm32f06x_gpio.c ****   *
  18:Library/src/lcm32f06x_gpio.c ****   ******************************************************************************
  19:Library/src/lcm32f06x_gpio.c ****   */
  20:Library/src/lcm32f06x_gpio.c **** 
  21:Library/src/lcm32f06x_gpio.c **** /* Includes ------------------------------------------------------------------*/
  22:Library/src/lcm32f06x_gpio.c **** #include "lcm32f06x_gpio.h"
  23:Library/src/lcm32f06x_gpio.c **** 
  24:Library/src/lcm32f06x_gpio.c **** /* Private define ------------------------------------------------------------*/
  25:Library/src/lcm32f06x_gpio.c **** 
  26:Library/src/lcm32f06x_gpio.c **** /*
  27:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
  28:Library/src/lcm32f06x_gpio.c ****                     ##### Initialization and Configuration #####
  29:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
  30:Library/src/lcm32f06x_gpio.c **** */
  31:Library/src/lcm32f06x_gpio.c **** 
  32:Library/src/lcm32f06x_gpio.c **** /**
ARM GAS  /tmp/ccTxDPsK.s 			page 2


  33:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_DeInit
  34:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Deinitializes GPIO peripheral registers to their default reset values.
  35:Library/src/lcm32f06x_gpio.c ****   *         CN: 将 GPIO 外设寄存器初始化为其默认重置值。
  36:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
  37:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
  38:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
  39:Library/src/lcm32f06x_gpio.c ****   * @retval None
  40:Library/src/lcm32f06x_gpio.c ****   */
  41:Library/src/lcm32f06x_gpio.c **** void GPIO_DeInit(GPIO_TypeDef *GPIOx)
  42:Library/src/lcm32f06x_gpio.c **** {
  27              		.loc 1 42 1 view -0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 0
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  43:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
  44:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
  31              		.loc 1 44 3 view .LVU1
  45:Library/src/lcm32f06x_gpio.c **** 
  46:Library/src/lcm32f06x_gpio.c ****   if (GPIOx == GPIOA)
  32              		.loc 1 46 3 view .LVU2
  33              		.loc 1 46 6 is_stmt 0 view .LVU3
  34 0000 9023     		movs	r3, #144
  42:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
  35              		.loc 1 42 1 view .LVU4
  36 0002 10B5     		push	{r4, lr}
  37              	.LCFI0:
  38              		.cfi_def_cfa_offset 8
  39              		.cfi_offset 4, -8
  40              		.cfi_offset 14, -4
  41              		.loc 1 46 6 view .LVU5
  42 0004 DB05     		lsls	r3, r3, #23
  43 0006 9842     		cmp	r0, r3
  44 0008 03D0     		beq	.L5
  47:Library/src/lcm32f06x_gpio.c ****   {
  48:Library/src/lcm32f06x_gpio.c ****     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
  49:Library/src/lcm32f06x_gpio.c ****     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
  50:Library/src/lcm32f06x_gpio.c ****   }
  51:Library/src/lcm32f06x_gpio.c ****   else 
  52:Library/src/lcm32f06x_gpio.c ****   {
  53:Library/src/lcm32f06x_gpio.c ****     if (GPIOx == GPIOB)
  45              		.loc 1 53 5 is_stmt 1 view .LVU6
  46              		.loc 1 53 8 is_stmt 0 view .LVU7
  47 000a 0B4B     		ldr	r3, .L7
  48 000c 9842     		cmp	r0, r3
  49 000e 09D0     		beq	.L6
  50              	.LVL1:
  51              	.L1:
  54:Library/src/lcm32f06x_gpio.c ****     {
  55:Library/src/lcm32f06x_gpio.c ****       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
  56:Library/src/lcm32f06x_gpio.c ****       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
  57:Library/src/lcm32f06x_gpio.c ****     }
  58:Library/src/lcm32f06x_gpio.c ****   }
  59:Library/src/lcm32f06x_gpio.c **** }
  52              		.loc 1 59 1 view .LVU8
  53              		@ sp needed
  54 0010 10BD     		pop	{r4, pc}
  55              	.LVL2:
ARM GAS  /tmp/ccTxDPsK.s 			page 3


  56              	.L5:
  48:Library/src/lcm32f06x_gpio.c ****     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
  57              		.loc 1 48 5 is_stmt 1 view .LVU9
  58 0012 0121     		movs	r1, #1
  59 0014 0120     		movs	r0, #1
  60              	.LVL3:
  48:Library/src/lcm32f06x_gpio.c ****     RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
  61              		.loc 1 48 5 is_stmt 0 view .LVU10
  62 0016 FFF7FEFF 		bl	RCC_AHBPeriphResetCmd
  63              	.LVL4:
  49:Library/src/lcm32f06x_gpio.c ****   }
  64              		.loc 1 49 5 is_stmt 1 view .LVU11
  65 001a 0021     		movs	r1, #0
  66 001c 0120     		movs	r0, #1
  67 001e FFF7FEFF 		bl	RCC_AHBPeriphResetCmd
  68              	.LVL5:
  69 0022 F5E7     		b	.L1
  70              	.LVL6:
  71              	.L6:
  55:Library/src/lcm32f06x_gpio.c ****       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
  72              		.loc 1 55 7 view .LVU12
  73 0024 0121     		movs	r1, #1
  74 0026 0220     		movs	r0, #2
  75              	.LVL7:
  55:Library/src/lcm32f06x_gpio.c ****       RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
  76              		.loc 1 55 7 is_stmt 0 view .LVU13
  77 0028 FFF7FEFF 		bl	RCC_AHBPeriphResetCmd
  78              	.LVL8:
  56:Library/src/lcm32f06x_gpio.c ****     }
  79              		.loc 1 56 7 is_stmt 1 view .LVU14
  80 002c 0021     		movs	r1, #0
  81 002e 0220     		movs	r0, #2
  82 0030 FFF7FEFF 		bl	RCC_AHBPeriphResetCmd
  83              	.LVL9:
  84              		.loc 1 59 1 is_stmt 0 view .LVU15
  85 0034 ECE7     		b	.L1
  86              	.L8:
  87 0036 C046     		.align	2
  88              	.L7:
  89 0038 00020048 		.word	1207960064
  90              		.cfi_endproc
  91              	.LFE45:
  93              		.section	.text.GPIO_Init,"ax",%progbits
  94              		.align	1
  95              		.p2align 2,,3
  96              		.global	GPIO_Init
  97              		.syntax unified
  98              		.code	16
  99              		.thumb_func
 101              	GPIO_Init:
 102              	.LVL10:
 103              	.LFB46:
  60:Library/src/lcm32f06x_gpio.c **** 
  61:Library/src/lcm32f06x_gpio.c **** /**
  62:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_Init
  63:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Initializes the GPIOx peripheral according to the specified 
  64:Library/src/lcm32f06x_gpio.c ****   *             parameters in the GPIO_InitStruct.
ARM GAS  /tmp/ccTxDPsK.s 			page 4


  65:Library/src/lcm32f06x_gpio.c ****   *         CN: 根据 GPIO_InitStruct 中指定的参数初始化 GPIOx。
  66:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
  67:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
  68:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
  69:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_InitStruct: 
  70:Library/src/lcm32f06x_gpio.c ****   *         EN: pointer to a GPIO_InitTypeDef structure that contains the 
  71:Library/src/lcm32f06x_gpio.c ****   *             configuration information for the specified GPIO peripheral.
  72:Library/src/lcm32f06x_gpio.c ****   *         CN: 指向 GPIO_InitTypeDef 结构的指针，该结构包含指定 GPIO 外设的配置信息。
  73:Library/src/lcm32f06x_gpio.c ****   * @retval None
  74:Library/src/lcm32f06x_gpio.c ****   */
  75:Library/src/lcm32f06x_gpio.c **** void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
  76:Library/src/lcm32f06x_gpio.c **** {
 104              		.loc 1 76 1 is_stmt 1 view -0
 105              		.cfi_startproc
 106              		@ args = 0, pretend = 0, frame = 0
 107              		@ frame_needed = 0, uses_anonymous_args = 0
  77:Library/src/lcm32f06x_gpio.c ****   uint32_t pinpos = 0, pos = 0;
 108              		.loc 1 77 3 view .LVU17
  78:Library/src/lcm32f06x_gpio.c ****   uint32_t tmpreg = 0;
 109              		.loc 1 78 3 view .LVU18
  79:Library/src/lcm32f06x_gpio.c **** 
  80:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
  81:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 110              		.loc 1 81 3 view .LVU19
  82:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
 111              		.loc 1 82 3 view .LVU20
  83:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
 112              		.loc 1 83 3 view .LVU21
  84:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
 113              		.loc 1 84 3 view .LVU22
  85:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
 114              		.loc 1 85 3 view .LVU23
  86:Library/src/lcm32f06x_gpio.c ****   
  87:Library/src/lcm32f06x_gpio.c ****   /* 获取需要配置的引脚 */
  88:Library/src/lcm32f06x_gpio.c ****   pinpos = GPIO_InitStruct->GPIO_Pin;
 115              		.loc 1 88 3 view .LVU24
  76:Library/src/lcm32f06x_gpio.c ****   uint32_t pinpos = 0, pos = 0;
 116              		.loc 1 76 1 is_stmt 0 view .LVU25
 117 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 118              	.LCFI1:
 119              		.cfi_def_cfa_offset 20
 120              		.cfi_offset 4, -20
 121              		.cfi_offset 5, -16
 122              		.cfi_offset 6, -12
 123              		.cfi_offset 7, -8
 124              		.cfi_offset 14, -4
  89:Library/src/lcm32f06x_gpio.c **** 
  90:Library/src/lcm32f06x_gpio.c ****   for (pos = 0; pos < 16; pos++)
  91:Library/src/lcm32f06x_gpio.c ****   {
  92:Library/src/lcm32f06x_gpio.c ****     if ((pinpos >> pos) & 0x01)
  93:Library/src/lcm32f06x_gpio.c ****     {
  94:Library/src/lcm32f06x_gpio.c ****        /* 配置引脚模式 */
  95:Library/src/lcm32f06x_gpio.c ****       tmpreg = GPIOx->MODER;
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg &= ~(0x03 << (pos * 2));
 125              		.loc 1 96 24 view .LVU26
 126 0002 0322     		movs	r2, #3
  76:Library/src/lcm32f06x_gpio.c ****   uint32_t pinpos = 0, pos = 0;
ARM GAS  /tmp/ccTxDPsK.s 			page 5


 127              		.loc 1 76 1 view .LVU27
 128 0004 CE46     		mov	lr, r9
 129 0006 4746     		mov	r7, r8
  88:Library/src/lcm32f06x_gpio.c **** 
 130              		.loc 1 88 10 view .LVU28
 131 0008 0B68     		ldr	r3, [r1]
 132 000a 1024     		movs	r4, #16
 133 000c 9946     		mov	r9, r3
 134              	.LVL11:
  90:Library/src/lcm32f06x_gpio.c ****   {
 135              		.loc 1 90 3 is_stmt 1 view .LVU29
  90:Library/src/lcm32f06x_gpio.c ****   {
 136              		.loc 1 90 21 discriminator 1 view .LVU30
  92:Library/src/lcm32f06x_gpio.c ****     {
 137              		.loc 1 92 25 is_stmt 0 view .LVU31
 138 000e 0125     		movs	r5, #1
  90:Library/src/lcm32f06x_gpio.c ****   {
 139              		.loc 1 90 12 view .LVU32
 140 0010 0023     		movs	r3, #0
 141              	.LVL12:
 142              		.loc 1 96 24 view .LVU33
 143 0012 9046     		mov	r8, r2
  76:Library/src/lcm32f06x_gpio.c ****   uint32_t pinpos = 0, pos = 0;
 144              		.loc 1 76 1 view .LVU34
 145 0014 80B5     		push	{r7, lr}
 146              	.LCFI2:
 147              		.cfi_def_cfa_offset 28
 148              		.cfi_offset 8, -28
 149              		.cfi_offset 9, -24
 150 0016 1AE0     		b	.L19
 151              	.LVL13:
 152              	.L30:
  97:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
  98:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
  99:Library/src/lcm32f06x_gpio.c **** 
 100:Library/src/lcm32f06x_gpio.c ****       /* 配置翻转速率 */
 101:Library/src/lcm32f06x_gpio.c ****       if (GPIO_InitStruct->GPIO_Speed == GPIO_Speed_Level_2)
 102:Library/src/lcm32f06x_gpio.c ****       {
 103:Library/src/lcm32f06x_gpio.c ****         GPIOx->CS_BSRR = 1 << (pos + 16);
 153              		.loc 1 103 9 is_stmt 1 view .LVU35
 154              		.loc 1 103 28 is_stmt 0 view .LVU36
 155 0018 2A00     		movs	r2, r5
 156 001a A240     		lsls	r2, r2, r4
 157              		.loc 1 103 24 view .LVU37
 158 001c 4263     		str	r2, [r0, #52]
 159              	.LVL14:
 104:Library/src/lcm32f06x_gpio.c ****       }
 105:Library/src/lcm32f06x_gpio.c ****       else
 106:Library/src/lcm32f06x_gpio.c ****       {
 107:Library/src/lcm32f06x_gpio.c ****         GPIOx->CS_BSRR = 1 << pos;
 108:Library/src/lcm32f06x_gpio.c ****       }
 109:Library/src/lcm32f06x_gpio.c **** 
 110:Library/src/lcm32f06x_gpio.c ****       /* 配置上下拉（默认为浮空） */
 111:Library/src/lcm32f06x_gpio.c ****       if ((GPIO_InitStruct->GPIO_PuPd) == GPIO_PuPd_UP)
 160              		.loc 1 111 7 is_stmt 1 view .LVU38
 161              		.loc 1 111 27 is_stmt 0 view .LVU39
 162 001e CA79     		ldrb	r2, [r1, #7]
ARM GAS  /tmp/ccTxDPsK.s 			page 6


 163              		.loc 1 111 10 view .LVU40
 164 0020 012A     		cmp	r2, #1
 165 0022 2FD0     		beq	.L24
 166              	.L13:
 112:Library/src/lcm32f06x_gpio.c ****       {
 113:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << (pos + 16);
 114:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 115:Library/src/lcm32f06x_gpio.c ****       }
 116:Library/src/lcm32f06x_gpio.c ****       else if ((GPIO_InitStruct->GPIO_PuPd) == GPIO_PuPd_DOWN)
 167              		.loc 1 116 12 is_stmt 1 view .LVU41
 168              		.loc 1 116 15 is_stmt 0 view .LVU42
 169 0024 022A     		cmp	r2, #2
 170 0026 43D0     		beq	.L25
 117:Library/src/lcm32f06x_gpio.c ****       {
 118:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << (pos + 16);
 119:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 120:Library/src/lcm32f06x_gpio.c ****       }
 121:Library/src/lcm32f06x_gpio.c ****       else if ((GPIO_InitStruct->GPIO_PuPd) == GPIO_PuPd_UPDOWN)
 171              		.loc 1 121 12 is_stmt 1 view .LVU43
 172              		.loc 1 121 15 is_stmt 0 view .LVU44
 173 0028 032A     		cmp	r2, #3
 174 002a 48D0     		beq	.L26
 122:Library/src/lcm32f06x_gpio.c ****       {
 123:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 124:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 125:Library/src/lcm32f06x_gpio.c ****       }
 126:Library/src/lcm32f06x_gpio.c ****       else
 127:Library/src/lcm32f06x_gpio.c ****       {
 128:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << (pos + 16);
 175              		.loc 1 128 9 is_stmt 1 view .LVU45
 176              		.loc 1 128 28 is_stmt 0 view .LVU46
 177 002c 2A00     		movs	r2, r5
 178 002e A240     		lsls	r2, r2, r4
 179              		.loc 1 128 24 view .LVU47
 180 0030 C260     		str	r2, [r0, #12]
 129:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << (pos + 16);
 181              		.loc 1 129 9 is_stmt 1 view .LVU48
 182              		.loc 1 129 24 is_stmt 0 view .LVU49
 183 0032 0261     		str	r2, [r0, #16]
 184              	.L14:
 130:Library/src/lcm32f06x_gpio.c ****       }
 131:Library/src/lcm32f06x_gpio.c **** 
 132:Library/src/lcm32f06x_gpio.c ****       /* 配置输出类型 */
 133:Library/src/lcm32f06x_gpio.c ****       if (GPIO_InitStruct->GPIO_OType == GPIO_OType_OS)
 185              		.loc 1 133 7 is_stmt 1 view .LVU50
 186              		.loc 1 133 26 is_stmt 0 view .LVU51
 187 0034 8A79     		ldrb	r2, [r1, #6]
 188              		.loc 1 133 10 view .LVU52
 189 0036 022A     		cmp	r2, #2
 190 0038 2CD0     		beq	.L27
 191              	.L17:
 134:Library/src/lcm32f06x_gpio.c ****       {
 135:Library/src/lcm32f06x_gpio.c ****         GPIOx->OS_BSRR = (1 << pos);
 136:Library/src/lcm32f06x_gpio.c ****       }
 137:Library/src/lcm32f06x_gpio.c ****       else if (GPIO_InitStruct->GPIO_OType == GPIO_OType_OD)
 192              		.loc 1 137 12 is_stmt 1 view .LVU53
 193              		.loc 1 137 15 is_stmt 0 view .LVU54
ARM GAS  /tmp/ccTxDPsK.s 			page 7


 194 003a 012A     		cmp	r2, #1
 195 003c 35D0     		beq	.L28
 138:Library/src/lcm32f06x_gpio.c ****       {
 139:Library/src/lcm32f06x_gpio.c ****         GPIOx->OD_BSRR = (1 << pos);
 140:Library/src/lcm32f06x_gpio.c ****       }
 141:Library/src/lcm32f06x_gpio.c ****       else
 142:Library/src/lcm32f06x_gpio.c ****       {
 143:Library/src/lcm32f06x_gpio.c ****         GPIOx->OD_BSRR = (1 << (pos + 16));
 196              		.loc 1 143 9 is_stmt 1 view .LVU55
 197              		.loc 1 143 29 is_stmt 0 view .LVU56
 198 003e 2A00     		movs	r2, r5
 199 0040 A240     		lsls	r2, r2, r4
 200              		.loc 1 143 24 view .LVU57
 201 0042 4260     		str	r2, [r0, #4]
 144:Library/src/lcm32f06x_gpio.c ****         GPIOx->OS_BSRR = (1 << (pos + 16));
 202              		.loc 1 144 9 is_stmt 1 view .LVU58
 203              		.loc 1 144 24 is_stmt 0 view .LVU59
 204 0044 8263     		str	r2, [r0, #56]
 205              	.LVL15:
 206              	.L10:
  90:Library/src/lcm32f06x_gpio.c ****   {
 207              		.loc 1 90 30 is_stmt 1 discriminator 2 view .LVU60
 208 0046 0133     		adds	r3, r3, #1
 209              	.LVL16:
  90:Library/src/lcm32f06x_gpio.c ****   {
 210              		.loc 1 90 21 discriminator 1 view .LVU61
 211 0048 0134     		adds	r4, r4, #1
 212 004a 102B     		cmp	r3, #16
 213 004c 29D0     		beq	.L29
 214              	.LVL17:
 215              	.L19:
  92:Library/src/lcm32f06x_gpio.c ****     {
 216              		.loc 1 92 5 view .LVU62
  92:Library/src/lcm32f06x_gpio.c ****     {
 217              		.loc 1 92 17 is_stmt 0 view .LVU63
 218 004e 4A46     		mov	r2, r9
 219 0050 DA40     		lsrs	r2, r2, r3
  92:Library/src/lcm32f06x_gpio.c ****     {
 220              		.loc 1 92 8 view .LVU64
 221 0052 1542     		tst	r5, r2
 222 0054 F7D0     		beq	.L10
  95:Library/src/lcm32f06x_gpio.c ****       tmpreg &= ~(0x03 << (pos * 2));
 223              		.loc 1 95 7 is_stmt 1 view .LVU65
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
 224              		.loc 1 96 24 is_stmt 0 view .LVU66
 225 0056 4246     		mov	r2, r8
 226 0058 5F00     		lsls	r7, r3, #1
 227 005a BA40     		lsls	r2, r2, r7
 228 005c 9446     		mov	ip, r2
  95:Library/src/lcm32f06x_gpio.c ****       tmpreg &= ~(0x03 << (pos * 2));
 229              		.loc 1 95 14 view .LVU67
 230 005e 0668     		ldr	r6, [r0]
 231              	.LVL18:
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
 232              		.loc 1 96 7 is_stmt 1 view .LVU68
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
 233              		.loc 1 96 14 is_stmt 0 view .LVU69
ARM GAS  /tmp/ccTxDPsK.s 			page 8


 234 0060 3200     		movs	r2, r6
 235 0062 6646     		mov	r6, ip
 236              	.LVL19:
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
 237              		.loc 1 96 14 view .LVU70
 238 0064 B243     		bics	r2, r6
 239              	.LVL20:
  96:Library/src/lcm32f06x_gpio.c ****       tmpreg |= (GPIO_InitStruct->GPIO_Mode) << (pos * 2);
 240              		.loc 1 96 14 view .LVU71
 241 0066 9446     		mov	ip, r2
 242              	.LVL21:
  97:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
 243              		.loc 1 97 7 is_stmt 1 view .LVU72
  97:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
 244              		.loc 1 97 33 is_stmt 0 view .LVU73
 245 0068 0A79     		ldrb	r2, [r1, #4]
 246              	.LVL22:
  97:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
 247              		.loc 1 97 14 view .LVU74
 248 006a 6646     		mov	r6, ip
  97:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
 249              		.loc 1 97 46 view .LVU75
 250 006c BA40     		lsls	r2, r2, r7
  97:Library/src/lcm32f06x_gpio.c ****       GPIOx->MODER = tmpreg;
 251              		.loc 1 97 14 view .LVU76
 252 006e 3243     		orrs	r2, r6
 253              	.LVL23:
  98:Library/src/lcm32f06x_gpio.c **** 
 254              		.loc 1 98 7 is_stmt 1 view .LVU77
  98:Library/src/lcm32f06x_gpio.c **** 
 255              		.loc 1 98 20 is_stmt 0 view .LVU78
 256 0070 0260     		str	r2, [r0]
 101:Library/src/lcm32f06x_gpio.c ****       {
 257              		.loc 1 101 7 is_stmt 1 view .LVU79
 101:Library/src/lcm32f06x_gpio.c ****       {
 258              		.loc 1 101 10 is_stmt 0 view .LVU80
 259 0072 4A79     		ldrb	r2, [r1, #5]
 260              	.LVL24:
 101:Library/src/lcm32f06x_gpio.c ****       {
 261              		.loc 1 101 10 view .LVU81
 262 0074 002A     		cmp	r2, #0
 263 0076 CFD0     		beq	.L30
 107:Library/src/lcm32f06x_gpio.c ****       }
 264              		.loc 1 107 9 is_stmt 1 view .LVU82
 107:Library/src/lcm32f06x_gpio.c ****       }
 265              		.loc 1 107 28 is_stmt 0 view .LVU83
 266 0078 2A00     		movs	r2, r5
 267 007a 9A40     		lsls	r2, r2, r3
 107:Library/src/lcm32f06x_gpio.c ****       }
 268              		.loc 1 107 24 view .LVU84
 269 007c 4263     		str	r2, [r0, #52]
 270              	.LVL25:
 111:Library/src/lcm32f06x_gpio.c ****       {
 271              		.loc 1 111 7 is_stmt 1 view .LVU85
 111:Library/src/lcm32f06x_gpio.c ****       {
 272              		.loc 1 111 27 is_stmt 0 view .LVU86
 273 007e CA79     		ldrb	r2, [r1, #7]
ARM GAS  /tmp/ccTxDPsK.s 			page 9


 111:Library/src/lcm32f06x_gpio.c ****       {
 274              		.loc 1 111 10 view .LVU87
 275 0080 012A     		cmp	r2, #1
 276 0082 CFD1     		bne	.L13
 277              	.L24:
 113:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 278              		.loc 1 113 9 is_stmt 1 view .LVU88
 113:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 279              		.loc 1 113 28 is_stmt 0 view .LVU89
 280 0084 1600     		movs	r6, r2
 114:Library/src/lcm32f06x_gpio.c ****       }
 281              		.loc 1 114 28 view .LVU90
 282 0086 9A40     		lsls	r2, r2, r3
 113:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 283              		.loc 1 113 28 view .LVU91
 284 0088 A640     		lsls	r6, r6, r4
 113:Library/src/lcm32f06x_gpio.c ****         GPIOx->PU_BSRR = 1 << pos;
 285              		.loc 1 113 24 view .LVU92
 286 008a 0661     		str	r6, [r0, #16]
 114:Library/src/lcm32f06x_gpio.c ****       }
 287              		.loc 1 114 9 is_stmt 1 view .LVU93
 114:Library/src/lcm32f06x_gpio.c ****       }
 288              		.loc 1 114 24 is_stmt 0 view .LVU94
 289 008c C260     		str	r2, [r0, #12]
 133:Library/src/lcm32f06x_gpio.c ****       {
 290              		.loc 1 133 7 is_stmt 1 view .LVU95
 133:Library/src/lcm32f06x_gpio.c ****       {
 291              		.loc 1 133 26 is_stmt 0 view .LVU96
 292 008e 8A79     		ldrb	r2, [r1, #6]
 133:Library/src/lcm32f06x_gpio.c ****       {
 293              		.loc 1 133 10 view .LVU97
 294 0090 022A     		cmp	r2, #2
 295 0092 D2D1     		bne	.L17
 296              	.L27:
 135:Library/src/lcm32f06x_gpio.c ****       }
 297              		.loc 1 135 9 is_stmt 1 view .LVU98
 135:Library/src/lcm32f06x_gpio.c ****       }
 298              		.loc 1 135 29 is_stmt 0 view .LVU99
 299 0094 2A00     		movs	r2, r5
 300 0096 9A40     		lsls	r2, r2, r3
  90:Library/src/lcm32f06x_gpio.c ****   {
 301              		.loc 1 90 30 discriminator 2 view .LVU100
 302 0098 0133     		adds	r3, r3, #1
 303              	.LVL26:
 135:Library/src/lcm32f06x_gpio.c ****       }
 304              		.loc 1 135 24 view .LVU101
 305 009a 8263     		str	r2, [r0, #56]
  90:Library/src/lcm32f06x_gpio.c ****   {
 306              		.loc 1 90 30 is_stmt 1 discriminator 2 view .LVU102
 307              	.LVL27:
  90:Library/src/lcm32f06x_gpio.c ****   {
 308              		.loc 1 90 21 discriminator 1 view .LVU103
 309 009c 0134     		adds	r4, r4, #1
 310 009e 102B     		cmp	r3, #16
 311 00a0 D5D1     		bne	.L19
 312              	.LVL28:
 313              	.L29:
ARM GAS  /tmp/ccTxDPsK.s 			page 10


 145:Library/src/lcm32f06x_gpio.c ****       }
 146:Library/src/lcm32f06x_gpio.c ****     }
 147:Library/src/lcm32f06x_gpio.c ****   }
 148:Library/src/lcm32f06x_gpio.c **** }
 314              		.loc 1 148 1 is_stmt 0 view .LVU104
 315              		@ sp needed
 316              	.LVL29:
 317              		.loc 1 148 1 view .LVU105
 318 00a2 C0BC     		pop	{r6, r7}
 319 00a4 B946     		mov	r9, r7
 320 00a6 B046     		mov	r8, r6
 321 00a8 F0BD     		pop	{r4, r5, r6, r7, pc}
 322              	.LVL30:
 323              	.L28:
 139:Library/src/lcm32f06x_gpio.c ****       }
 324              		.loc 1 139 9 is_stmt 1 view .LVU106
 139:Library/src/lcm32f06x_gpio.c ****       }
 325              		.loc 1 139 29 is_stmt 0 view .LVU107
 326 00aa 9A40     		lsls	r2, r2, r3
 139:Library/src/lcm32f06x_gpio.c ****       }
 327              		.loc 1 139 24 view .LVU108
 328 00ac 4260     		str	r2, [r0, #4]
 329 00ae CAE7     		b	.L10
 330              	.L25:
 118:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 331              		.loc 1 118 9 is_stmt 1 view .LVU109
 118:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 332              		.loc 1 118 28 is_stmt 0 view .LVU110
 333 00b0 2A00     		movs	r2, r5
 334 00b2 A240     		lsls	r2, r2, r4
 118:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 335              		.loc 1 118 24 view .LVU111
 336 00b4 C260     		str	r2, [r0, #12]
 119:Library/src/lcm32f06x_gpio.c ****       }
 337              		.loc 1 119 9 is_stmt 1 view .LVU112
 119:Library/src/lcm32f06x_gpio.c ****       }
 338              		.loc 1 119 28 is_stmt 0 view .LVU113
 339 00b6 2A00     		movs	r2, r5
 340 00b8 9A40     		lsls	r2, r2, r3
 119:Library/src/lcm32f06x_gpio.c ****       }
 341              		.loc 1 119 24 view .LVU114
 342 00ba 0261     		str	r2, [r0, #16]
 343 00bc BAE7     		b	.L14
 344              	.L26:
 123:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 345              		.loc 1 123 9 is_stmt 1 view .LVU115
 123:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 346              		.loc 1 123 28 is_stmt 0 view .LVU116
 347 00be 2A00     		movs	r2, r5
 348 00c0 9A40     		lsls	r2, r2, r3
 123:Library/src/lcm32f06x_gpio.c ****         GPIOx->PD_BSRR = 1 << pos;
 349              		.loc 1 123 24 view .LVU117
 350 00c2 C260     		str	r2, [r0, #12]
 124:Library/src/lcm32f06x_gpio.c ****       }
 351              		.loc 1 124 9 is_stmt 1 view .LVU118
 124:Library/src/lcm32f06x_gpio.c ****       }
 352              		.loc 1 124 24 is_stmt 0 view .LVU119
ARM GAS  /tmp/ccTxDPsK.s 			page 11


 353 00c4 0261     		str	r2, [r0, #16]
 354 00c6 B5E7     		b	.L14
 355              		.cfi_endproc
 356              	.LFE46:
 358              		.section	.text.GPIO_StructInit,"ax",%progbits
 359              		.align	1
 360              		.p2align 2,,3
 361              		.global	GPIO_StructInit
 362              		.syntax unified
 363              		.code	16
 364              		.thumb_func
 366              	GPIO_StructInit:
 367              	.LVL31:
 368              	.LFB47:
 149:Library/src/lcm32f06x_gpio.c **** 
 150:Library/src/lcm32f06x_gpio.c **** /**
 151:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_StructInit
 152:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Fills each GPIO_InitStruct member with its default value.
 153:Library/src/lcm32f06x_gpio.c ****   *         CN: 用默认值填充每个 GPIO_InitStruct 成员。
 154:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_InitStruct: 
 155:Library/src/lcm32f06x_gpio.c ****   *         EN: pointer to a GPIO_InitTypeDef structure that contains the 
 156:Library/src/lcm32f06x_gpio.c ****   *             configuration information for the specified GPIO peripheral.
 157:Library/src/lcm32f06x_gpio.c ****   *         CN: 指向 GPIO_InitTypeDef 结构的指针，该结构包含指定 GPIO 外设的配置信息。
 158:Library/src/lcm32f06x_gpio.c ****   * @retval None
 159:Library/src/lcm32f06x_gpio.c ****   */
 160:Library/src/lcm32f06x_gpio.c **** void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
 161:Library/src/lcm32f06x_gpio.c **** {
 369              		.loc 1 161 1 is_stmt 1 view -0
 370              		.cfi_startproc
 371              		@ args = 0, pretend = 0, frame = 0
 372              		@ frame_needed = 0, uses_anonymous_args = 0
 373              		@ link register save eliminated.
 162:Library/src/lcm32f06x_gpio.c ****   GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
 374              		.loc 1 162 3 view .LVU121
 163:Library/src/lcm32f06x_gpio.c **** 
 164:Library/src/lcm32f06x_gpio.c ****   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
 375              		.loc 1 164 30 is_stmt 0 view .LVU122
 376 0000 0023     		movs	r3, #0
 165:Library/src/lcm32f06x_gpio.c **** 
 166:Library/src/lcm32f06x_gpio.c ****   GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
 167:Library/src/lcm32f06x_gpio.c **** 
 168:Library/src/lcm32f06x_gpio.c ****   GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
 169:Library/src/lcm32f06x_gpio.c **** 
 170:Library/src/lcm32f06x_gpio.c ****   GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
 171:Library/src/lcm32f06x_gpio.c **** }
 377              		.loc 1 171 1 view .LVU123
 378              		@ sp needed
 164:Library/src/lcm32f06x_gpio.c **** 
 379              		.loc 1 164 30 view .LVU124
 380 0002 014A     		ldr	r2, .L32
 381 0004 0CC0     		stmia	r0!, {r2, r3}
 382              	.LVL32:
 383              		.loc 1 171 1 view .LVU125
 384 0006 7047     		bx	lr
 385              	.L33:
 386              		.align	2
 387              	.L32:
ARM GAS  /tmp/ccTxDPsK.s 			page 12


 388 0008 FFFF0000 		.word	65535
 389              		.cfi_endproc
 390              	.LFE47:
 392              		.section	.text.GPIO_PinLockConfig,"ax",%progbits
 393              		.align	1
 394              		.p2align 2,,3
 395              		.global	GPIO_PinLockConfig
 396              		.syntax unified
 397              		.code	16
 398              		.thumb_func
 400              	GPIO_PinLockConfig:
 401              	.LVL33:
 402              	.LFB48:
 172:Library/src/lcm32f06x_gpio.c **** 
 173:Library/src/lcm32f06x_gpio.c **** /**
 174:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_PinLockConfig
 175:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Locks GPIO Pins configuration registers.
 176:Library/src/lcm32f06x_gpio.c ****   *         CN: 锁定 GPIO 引脚配置寄存器
 177:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 178:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 179:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设
 180:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 181:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 182:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口
 183:Library/src/lcm32f06x_gpio.c ****   * @retval None
 184:Library/src/lcm32f06x_gpio.c ****   */
 185:Library/src/lcm32f06x_gpio.c **** void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 186:Library/src/lcm32f06x_gpio.c **** {
 403              		.loc 1 186 1 is_stmt 1 view -0
 404              		.cfi_startproc
 405              		@ args = 0, pretend = 0, frame = 0
 406              		@ frame_needed = 0, uses_anonymous_args = 0
 407              		@ link register save eliminated.
 187:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_1 = 0x00010000;
 408              		.loc 1 187 3 view .LVU127
 188:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_0 = 0x00000000;
 409              		.loc 1 188 3 view .LVU128
 189:Library/src/lcm32f06x_gpio.c **** 
 190:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 191:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 410              		.loc 1 191 3 view .LVU129
 192:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 411              		.loc 1 192 3 view .LVU130
 193:Library/src/lcm32f06x_gpio.c **** 
 194:Library/src/lcm32f06x_gpio.c ****   tmp_1 |= GPIO_Pin;
 412              		.loc 1 194 3 view .LVU131
 413              		.loc 1 194 9 is_stmt 0 view .LVU132
 414 0000 8023     		movs	r3, #128
 415 0002 5B02     		lsls	r3, r3, #9
 416 0004 1A00     		movs	r2, r3
 417 0006 0A43     		orrs	r2, r1
 418              	.LVL34:
 195:Library/src/lcm32f06x_gpio.c ****   tmp_0 |= GPIO_Pin;
 419              		.loc 1 195 3 is_stmt 1 view .LVU133
 196:Library/src/lcm32f06x_gpio.c **** 
 197:Library/src/lcm32f06x_gpio.c ****   /* Set LCKK bit */
 198:Library/src/lcm32f06x_gpio.c ****   GPIOx->LCKR = tmp_1;
ARM GAS  /tmp/ccTxDPsK.s 			page 13


 420              		.loc 1 198 3 view .LVU134
 421              		.loc 1 198 15 is_stmt 0 view .LVU135
 422 0008 0262     		str	r2, [r0, #32]
 199:Library/src/lcm32f06x_gpio.c **** 
 200:Library/src/lcm32f06x_gpio.c ****   /* Reset LCKK bit */
 201:Library/src/lcm32f06x_gpio.c ****   GPIOx->LCKR = tmp_0;
 423              		.loc 1 201 3 is_stmt 1 view .LVU136
 424              		.loc 1 201 15 is_stmt 0 view .LVU137
 425 000a 0162     		str	r1, [r0, #32]
 426              	.LVL35:
 202:Library/src/lcm32f06x_gpio.c **** 
 203:Library/src/lcm32f06x_gpio.c ****   /* Set LCKK bit */
 204:Library/src/lcm32f06x_gpio.c ****   GPIOx->LCKR = tmp_1;
 427              		.loc 1 204 3 is_stmt 1 view .LVU138
 428              		.loc 1 204 15 is_stmt 0 view .LVU139
 429 000c 0262     		str	r2, [r0, #32]
 430              	.LVL36:
 205:Library/src/lcm32f06x_gpio.c **** 
 206:Library/src/lcm32f06x_gpio.c ****   /* Read LCKK bit */
 207:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->LCKR;
 431              		.loc 1 207 3 is_stmt 1 view .LVU140
 432              		.loc 1 207 9 is_stmt 0 view .LVU141
 433 000e 026A     		ldr	r2, [r0, #32]
 434              	.LVL37:
 208:Library/src/lcm32f06x_gpio.c **** 
 209:Library/src/lcm32f06x_gpio.c ****   /* Read LCKK bit */
 210:Library/src/lcm32f06x_gpio.c ****   if (!((GPIOx->LCKR >> 16) & 0x01))
 435              		.loc 1 210 3 is_stmt 1 view .LVU142
 436              		.loc 1 210 15 is_stmt 0 view .LVU143
 437 0010 026A     		ldr	r2, [r0, #32]
 438              		.loc 1 210 6 view .LVU144
 439 0012 1A42     		tst	r2, r3
 440 0014 00D0     		beq	.L36
 211:Library/src/lcm32f06x_gpio.c ****   {
 212:Library/src/lcm32f06x_gpio.c ****     /* 锁定失败 */
 213:Library/src/lcm32f06x_gpio.c ****     while (1)
 214:Library/src/lcm32f06x_gpio.c ****     {
 215:Library/src/lcm32f06x_gpio.c ****         __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 216:Library/src/lcm32f06x_gpio.c ****     }
 217:Library/src/lcm32f06x_gpio.c ****   }
 218:Library/src/lcm32f06x_gpio.c **** }
 441              		.loc 1 218 1 view .LVU145
 442              		@ sp needed
 443 0016 7047     		bx	lr
 444              	.L36:
 213:Library/src/lcm32f06x_gpio.c ****     {
 445              		.loc 1 213 5 is_stmt 1 view .LVU146
 215:Library/src/lcm32f06x_gpio.c ****     }
 446              		.loc 1 215 9 discriminator 1 view .LVU147
 447              		.syntax divided
 448              	@ 215 "Library/src/lcm32f06x_gpio.c" 1
 449 0018 C046     		nop
 450              	@ 0 "" 2
 215:Library/src/lcm32f06x_gpio.c ****     }
 451              		.loc 1 215 18 discriminator 1 view .LVU148
 452              	@ 215 "Library/src/lcm32f06x_gpio.c" 1
 453 001a C046     		nop
ARM GAS  /tmp/ccTxDPsK.s 			page 14


 454              	@ 0 "" 2
 215:Library/src/lcm32f06x_gpio.c ****     }
 455              		.loc 1 215 27 discriminator 1 view .LVU149
 456              	@ 215 "Library/src/lcm32f06x_gpio.c" 1
 457 001c C046     		nop
 458              	@ 0 "" 2
 215:Library/src/lcm32f06x_gpio.c ****     }
 459              		.loc 1 215 36 discriminator 1 view .LVU150
 460              	@ 215 "Library/src/lcm32f06x_gpio.c" 1
 461 001e C046     		nop
 462              	@ 0 "" 2
 215:Library/src/lcm32f06x_gpio.c ****     }
 463              		.loc 1 215 45 discriminator 1 view .LVU151
 464              	@ 215 "Library/src/lcm32f06x_gpio.c" 1
 465 0020 C046     		nop
 466              	@ 0 "" 2
 213:Library/src/lcm32f06x_gpio.c ****     {
 467              		.loc 1 213 11 view .LVU152
 468              		.thumb
 469              		.syntax unified
 470 0022 F9E7     		b	.L36
 471              		.cfi_endproc
 472              	.LFE48:
 474              		.section	.text.GPIO_ReadInputDataBit,"ax",%progbits
 475              		.align	1
 476              		.p2align 2,,3
 477              		.global	GPIO_ReadInputDataBit
 478              		.syntax unified
 479              		.code	16
 480              		.thumb_func
 482              	GPIO_ReadInputDataBit:
 483              	.LVL38:
 484              	.LFB49:
 219:Library/src/lcm32f06x_gpio.c **** 
 220:Library/src/lcm32f06x_gpio.c **** /*
 221:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
 222:Library/src/lcm32f06x_gpio.c ****                     ##### GPIO Read and Write #####
 223:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
 224:Library/src/lcm32f06x_gpio.c **** */
 225:Library/src/lcm32f06x_gpio.c **** 
 226:Library/src/lcm32f06x_gpio.c **** /**
 227:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ReadInputDataBit
 228:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Read the specified input port pins bit by bit.
 229:Library/src/lcm32f06x_gpio.c ****   *         CN: 按位读指定的输入端口引脚。
 230:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 231:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 232:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 233:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 234:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be read.
 235:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要读的端口位。
 236:Library/src/lcm32f06x_gpio.c ****   * @retval EN: The input port pin value.
 237:Library/src/lcm32f06x_gpio.c ****   *         CN: 该输入端口引脚的值。
 238:Library/src/lcm32f06x_gpio.c ****   */
 239:Library/src/lcm32f06x_gpio.c **** uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 240:Library/src/lcm32f06x_gpio.c **** {
 485              		.loc 1 240 1 view -0
 486              		.cfi_startproc
ARM GAS  /tmp/ccTxDPsK.s 			page 15


 487              		@ args = 0, pretend = 0, frame = 0
 488              		@ frame_needed = 0, uses_anonymous_args = 0
 489              		@ link register save eliminated.
 241:Library/src/lcm32f06x_gpio.c ****   uint8_t bitstatus = 0x00;
 490              		.loc 1 241 3 view .LVU154
 242:Library/src/lcm32f06x_gpio.c **** 
 243:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 244:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 491              		.loc 1 244 3 view .LVU155
 245:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 492              		.loc 1 245 3 view .LVU156
 246:Library/src/lcm32f06x_gpio.c **** 
 247:Library/src/lcm32f06x_gpio.c ****   if (GPIOx->IDR & GPIO_Pin)
 493              		.loc 1 247 3 view .LVU157
 494              		.loc 1 247 12 is_stmt 0 view .LVU158
 495 0000 4069     		ldr	r0, [r0, #20]
 496              	.LVL39:
 248:Library/src/lcm32f06x_gpio.c ****   {
 249:Library/src/lcm32f06x_gpio.c ****     bitstatus = (uint8_t)Bit_SET;
 250:Library/src/lcm32f06x_gpio.c ****   }
 251:Library/src/lcm32f06x_gpio.c ****   else
 252:Library/src/lcm32f06x_gpio.c ****   {
 253:Library/src/lcm32f06x_gpio.c ****     bitstatus = (uint8_t)Bit_RESET;
 254:Library/src/lcm32f06x_gpio.c ****   }
 255:Library/src/lcm32f06x_gpio.c ****   return bitstatus;
 497              		.loc 1 255 3 is_stmt 1 view .LVU159
 256:Library/src/lcm32f06x_gpio.c **** }
 498              		.loc 1 256 1 is_stmt 0 view .LVU160
 499              		@ sp needed
 247:Library/src/lcm32f06x_gpio.c ****   {
 500              		.loc 1 247 18 view .LVU161
 501 0002 0840     		ands	r0, r1
 502              	.LVL40:
 247:Library/src/lcm32f06x_gpio.c ****   {
 503              		.loc 1 247 6 view .LVU162
 504 0004 431E     		subs	r3, r0, #1
 505 0006 9841     		sbcs	r0, r0, r3
 255:Library/src/lcm32f06x_gpio.c **** }
 506              		.loc 1 255 10 discriminator 1 view .LVU163
 507 0008 C0B2     		uxtb	r0, r0
 508              		.loc 1 256 1 view .LVU164
 509 000a 7047     		bx	lr
 510              		.cfi_endproc
 511              	.LFE49:
 513              		.section	.text.GPIO_ReadInputData,"ax",%progbits
 514              		.align	1
 515              		.p2align 2,,3
 516              		.global	GPIO_ReadInputData
 517              		.syntax unified
 518              		.code	16
 519              		.thumb_func
 521              	GPIO_ReadInputData:
 522              	.LVL41:
 523              	.LFB50:
 257:Library/src/lcm32f06x_gpio.c **** 
 258:Library/src/lcm32f06x_gpio.c **** /**
 259:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ReadInputData
ARM GAS  /tmp/ccTxDPsK.s 			page 16


 260:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Reads the specified input port pin.
 261:Library/src/lcm32f06x_gpio.c ****   *         CN: 读指定的输入端口引脚。
 262:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 263:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 264:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 265:Library/src/lcm32f06x_gpio.c ****   * @retval EN: The input port pin value.
 266:Library/src/lcm32f06x_gpio.c ****   *         CN: 该输入端口引脚的值。
 267:Library/src/lcm32f06x_gpio.c ****   */
 268:Library/src/lcm32f06x_gpio.c **** uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
 269:Library/src/lcm32f06x_gpio.c **** {
 524              		.loc 1 269 1 is_stmt 1 view -0
 525              		.cfi_startproc
 526              		@ args = 0, pretend = 0, frame = 0
 527              		@ frame_needed = 0, uses_anonymous_args = 0
 528              		@ link register save eliminated.
 270:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 271:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 529              		.loc 1 271 3 view .LVU166
 272:Library/src/lcm32f06x_gpio.c **** 
 273:Library/src/lcm32f06x_gpio.c ****   return ((uint16_t)GPIOx->IDR);
 530              		.loc 1 273 3 view .LVU167
 531              		.loc 1 273 26 is_stmt 0 view .LVU168
 532 0000 4069     		ldr	r0, [r0, #20]
 533              	.LVL42:
 274:Library/src/lcm32f06x_gpio.c **** }
 534              		.loc 1 274 1 view .LVU169
 535              		@ sp needed
 273:Library/src/lcm32f06x_gpio.c **** }
 536              		.loc 1 273 11 discriminator 1 view .LVU170
 537 0002 80B2     		uxth	r0, r0
 538              		.loc 1 274 1 view .LVU171
 539 0004 7047     		bx	lr
 540              		.cfi_endproc
 541              	.LFE50:
 543 0006 C046     		.section	.text.GPIO_ReadOutputDataBit,"ax",%progbits
 544              		.align	1
 545              		.p2align 2,,3
 546              		.global	GPIO_ReadOutputDataBit
 547              		.syntax unified
 548              		.code	16
 549              		.thumb_func
 551              	GPIO_ReadOutputDataBit:
 552              	.LVL43:
 553              	.LFB51:
 275:Library/src/lcm32f06x_gpio.c **** 
 276:Library/src/lcm32f06x_gpio.c **** /**
 277:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ReadOutputDataBit
 278:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Reads the specified output data port bit.
 279:Library/src/lcm32f06x_gpio.c ****   *         CN: 读指定的输出数据端口位。
 280:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 281:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 282:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 283:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 284:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be read.
 285:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要读的端口位。
 286:Library/src/lcm32f06x_gpio.c ****   * @retval EN: The input port pin value.
 287:Library/src/lcm32f06x_gpio.c ****   *         CN: 该输出端口引脚的值。
ARM GAS  /tmp/ccTxDPsK.s 			page 17


 288:Library/src/lcm32f06x_gpio.c ****   */
 289:Library/src/lcm32f06x_gpio.c **** uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 290:Library/src/lcm32f06x_gpio.c **** {
 554              		.loc 1 290 1 is_stmt 1 view -0
 555              		.cfi_startproc
 556              		@ args = 0, pretend = 0, frame = 0
 557              		@ frame_needed = 0, uses_anonymous_args = 0
 558              		@ link register save eliminated.
 291:Library/src/lcm32f06x_gpio.c ****   uint8_t bitstatus = 0x00;
 559              		.loc 1 291 3 view .LVU173
 292:Library/src/lcm32f06x_gpio.c **** 
 293:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 294:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 560              		.loc 1 294 3 view .LVU174
 295:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 561              		.loc 1 295 3 view .LVU175
 296:Library/src/lcm32f06x_gpio.c **** 
 297:Library/src/lcm32f06x_gpio.c ****   if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
 562              		.loc 1 297 3 view .LVU176
 563              		.loc 1 297 13 is_stmt 0 view .LVU177
 564 0000 8069     		ldr	r0, [r0, #24]
 565              	.LVL44:
 298:Library/src/lcm32f06x_gpio.c ****   {
 299:Library/src/lcm32f06x_gpio.c ****     bitstatus = (uint8_t)Bit_SET;
 300:Library/src/lcm32f06x_gpio.c ****   }
 301:Library/src/lcm32f06x_gpio.c ****   else
 302:Library/src/lcm32f06x_gpio.c ****   {
 303:Library/src/lcm32f06x_gpio.c ****     bitstatus = (uint8_t)Bit_RESET;
 304:Library/src/lcm32f06x_gpio.c ****   }
 305:Library/src/lcm32f06x_gpio.c ****   return bitstatus;
 566              		.loc 1 305 3 is_stmt 1 view .LVU178
 306:Library/src/lcm32f06x_gpio.c **** }
 567              		.loc 1 306 1 is_stmt 0 view .LVU179
 568              		@ sp needed
 297:Library/src/lcm32f06x_gpio.c ****   {
 569              		.loc 1 297 19 view .LVU180
 570 0002 0840     		ands	r0, r1
 571              	.LVL45:
 297:Library/src/lcm32f06x_gpio.c ****   {
 572              		.loc 1 297 6 view .LVU181
 573 0004 431E     		subs	r3, r0, #1
 574 0006 9841     		sbcs	r0, r0, r3
 305:Library/src/lcm32f06x_gpio.c **** }
 575              		.loc 1 305 10 discriminator 1 view .LVU182
 576 0008 C0B2     		uxtb	r0, r0
 577              		.loc 1 306 1 view .LVU183
 578 000a 7047     		bx	lr
 579              		.cfi_endproc
 580              	.LFE51:
 582              		.section	.text.GPIO_ReadOutputData,"ax",%progbits
 583              		.align	1
 584              		.p2align 2,,3
 585              		.global	GPIO_ReadOutputData
 586              		.syntax unified
 587              		.code	16
 588              		.thumb_func
 590              	GPIO_ReadOutputData:
ARM GAS  /tmp/ccTxDPsK.s 			page 18


 591              	.LVL46:
 592              	.LFB52:
 307:Library/src/lcm32f06x_gpio.c **** 
 308:Library/src/lcm32f06x_gpio.c **** /**
 309:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ReadOutputData
 310:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Reads the specified GPIO output data port.
 311:Library/src/lcm32f06x_gpio.c ****   *         CN: 读指定的输出数据端口。
 312:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 313:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 314:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 315:Library/src/lcm32f06x_gpio.c ****   * @retval EN: The input port pin value.
 316:Library/src/lcm32f06x_gpio.c ****   *         CN: 该输出端口引脚的值。
 317:Library/src/lcm32f06x_gpio.c ****   */
 318:Library/src/lcm32f06x_gpio.c **** uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
 319:Library/src/lcm32f06x_gpio.c **** {
 593              		.loc 1 319 1 is_stmt 1 view -0
 594              		.cfi_startproc
 595              		@ args = 0, pretend = 0, frame = 0
 596              		@ frame_needed = 0, uses_anonymous_args = 0
 597              		@ link register save eliminated.
 320:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 321:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 598              		.loc 1 321 3 view .LVU185
 322:Library/src/lcm32f06x_gpio.c **** 
 323:Library/src/lcm32f06x_gpio.c ****   return ((uint16_t)GPIOx->ODR);
 599              		.loc 1 323 3 view .LVU186
 600              		.loc 1 323 26 is_stmt 0 view .LVU187
 601 0000 8069     		ldr	r0, [r0, #24]
 602              	.LVL47:
 324:Library/src/lcm32f06x_gpio.c **** }
 603              		.loc 1 324 1 view .LVU188
 604              		@ sp needed
 323:Library/src/lcm32f06x_gpio.c **** }
 605              		.loc 1 323 11 discriminator 1 view .LVU189
 606 0002 80B2     		uxth	r0, r0
 607              		.loc 1 324 1 view .LVU190
 608 0004 7047     		bx	lr
 609              		.cfi_endproc
 610              	.LFE52:
 612 0006 C046     		.section	.text.GPIO_SetBits,"ax",%progbits
 613              		.align	1
 614              		.p2align 2,,3
 615              		.global	GPIO_SetBits
 616              		.syntax unified
 617              		.code	16
 618              		.thumb_func
 620              	GPIO_SetBits:
 621              	.LVL48:
 622              	.LFB53:
 325:Library/src/lcm32f06x_gpio.c **** 
 326:Library/src/lcm32f06x_gpio.c **** /**
 327:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_SetBits
 328:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Sets the selected data port bits.
 329:Library/src/lcm32f06x_gpio.c ****   *         CN: 设置选定的数据端口位。
 330:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 331:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 332:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
ARM GAS  /tmp/ccTxDPsK.s 			page 19


 333:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 334:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 335:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 336:Library/src/lcm32f06x_gpio.c ****   * @retval None
 337:Library/src/lcm32f06x_gpio.c ****   */
 338:Library/src/lcm32f06x_gpio.c **** void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 339:Library/src/lcm32f06x_gpio.c **** {
 623              		.loc 1 339 1 is_stmt 1 view -0
 624              		.cfi_startproc
 625              		@ args = 0, pretend = 0, frame = 0
 626              		@ frame_needed = 0, uses_anonymous_args = 0
 627              		@ link register save eliminated.
 340:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 341:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 628              		.loc 1 341 3 view .LVU192
 342:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 629              		.loc 1 342 3 view .LVU193
 343:Library/src/lcm32f06x_gpio.c **** 
 344:Library/src/lcm32f06x_gpio.c ****   GPIOx->BSRR = GPIO_Pin;
 630              		.loc 1 344 3 view .LVU194
 631              		.loc 1 344 15 is_stmt 0 view .LVU195
 632 0000 C161     		str	r1, [r0, #28]
 345:Library/src/lcm32f06x_gpio.c **** }
 633              		.loc 1 345 1 view .LVU196
 634              		@ sp needed
 635 0002 7047     		bx	lr
 636              		.cfi_endproc
 637              	.LFE53:
 639              		.section	.text.GPIO_ResetBits,"ax",%progbits
 640              		.align	1
 641              		.p2align 2,,3
 642              		.global	GPIO_ResetBits
 643              		.syntax unified
 644              		.code	16
 645              		.thumb_func
 647              	GPIO_ResetBits:
 648              	.LVL49:
 649              	.LFB54:
 346:Library/src/lcm32f06x_gpio.c **** 
 347:Library/src/lcm32f06x_gpio.c **** /**
 348:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ResetBits
 349:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Clears the selected data port bits.
 350:Library/src/lcm32f06x_gpio.c ****   *         CN: 清除选定的数据端口位。
 351:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 352:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 353:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 354:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 355:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 356:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 357:Library/src/lcm32f06x_gpio.c ****   * @retval None
 358:Library/src/lcm32f06x_gpio.c ****   */
 359:Library/src/lcm32f06x_gpio.c **** void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 360:Library/src/lcm32f06x_gpio.c **** {
 650              		.loc 1 360 1 is_stmt 1 view -0
 651              		.cfi_startproc
 652              		@ args = 0, pretend = 0, frame = 0
 653              		@ frame_needed = 0, uses_anonymous_args = 0
ARM GAS  /tmp/ccTxDPsK.s 			page 20


 654              		@ link register save eliminated.
 361:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 362:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 655              		.loc 1 362 3 view .LVU198
 363:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 656              		.loc 1 363 3 view .LVU199
 364:Library/src/lcm32f06x_gpio.c **** 
 365:Library/src/lcm32f06x_gpio.c ****   GPIOx->BSRR = GPIO_Pin << 16;
 657              		.loc 1 365 3 view .LVU200
 658              		.loc 1 365 26 is_stmt 0 view .LVU201
 659 0000 0904     		lsls	r1, r1, #16
 660              	.LVL50:
 661              		.loc 1 365 15 view .LVU202
 662 0002 C161     		str	r1, [r0, #28]
 366:Library/src/lcm32f06x_gpio.c **** }
 663              		.loc 1 366 1 view .LVU203
 664              		@ sp needed
 665 0004 7047     		bx	lr
 666              		.cfi_endproc
 667              	.LFE54:
 669 0006 C046     		.section	.text.GPIO_WriteBit,"ax",%progbits
 670              		.align	1
 671              		.p2align 2,,3
 672              		.global	GPIO_WriteBit
 673              		.syntax unified
 674              		.code	16
 675              		.thumb_func
 677              	GPIO_WriteBit:
 678              	.LVL51:
 679              	.LFB55:
 367:Library/src/lcm32f06x_gpio.c **** 
 368:Library/src/lcm32f06x_gpio.c **** /**
 369:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_WriteBit
 370:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Sets or clears the selected data port bit.
 371:Library/src/lcm32f06x_gpio.c ****   *         CN: 设置或清除选定的数据端口位。
 372:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 373:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 374:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 375:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 376:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 377:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 378:Library/src/lcm32f06x_gpio.c ****   * @param  BitVal:
 379:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the value to be written to the selected bit.
 380:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入选择位的值。
 381:Library/src/lcm32f06x_gpio.c ****   *             @arg Bit_RESET: to clear the port pin
 382:Library/src/lcm32f06x_gpio.c ****   *             @arg Bit_SET  : to set the port pin
 383:Library/src/lcm32f06x_gpio.c ****   * @retval None
 384:Library/src/lcm32f06x_gpio.c ****   */
 385:Library/src/lcm32f06x_gpio.c **** void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
 386:Library/src/lcm32f06x_gpio.c **** {
 680              		.loc 1 386 1 is_stmt 1 view -0
 681              		.cfi_startproc
 682              		@ args = 0, pretend = 0, frame = 0
 683              		@ frame_needed = 0, uses_anonymous_args = 0
 684              		@ link register save eliminated.
 387:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 388:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
ARM GAS  /tmp/ccTxDPsK.s 			page 21


 685              		.loc 1 388 3 view .LVU205
 389:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
 686              		.loc 1 389 3 view .LVU206
 390:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_BIT_ACTION(BitVal));
 687              		.loc 1 390 3 view .LVU207
 391:Library/src/lcm32f06x_gpio.c **** 
 392:Library/src/lcm32f06x_gpio.c ****   if (BitVal != Bit_RESET)
 688              		.loc 1 392 3 view .LVU208
 689              		.loc 1 392 6 is_stmt 0 view .LVU209
 690 0000 002A     		cmp	r2, #0
 691 0002 00D1     		bne	.L46
 393:Library/src/lcm32f06x_gpio.c ****   {
 394:Library/src/lcm32f06x_gpio.c ****     GPIOx->BSRR = GPIO_Pin;
 395:Library/src/lcm32f06x_gpio.c ****   }
 396:Library/src/lcm32f06x_gpio.c ****   else
 397:Library/src/lcm32f06x_gpio.c ****   {
 398:Library/src/lcm32f06x_gpio.c ****     GPIOx->BSRR = GPIO_Pin << 16;
 692              		.loc 1 398 5 is_stmt 1 view .LVU210
 693              		.loc 1 398 28 is_stmt 0 view .LVU211
 694 0004 0904     		lsls	r1, r1, #16
 695              	.LVL52:
 696              	.L46:
 697              		.loc 1 398 17 view .LVU212
 698 0006 C161     		str	r1, [r0, #28]
 399:Library/src/lcm32f06x_gpio.c ****   }
 400:Library/src/lcm32f06x_gpio.c **** }
 699              		.loc 1 400 1 view .LVU213
 700              		@ sp needed
 701 0008 7047     		bx	lr
 702              		.cfi_endproc
 703              	.LFE55:
 705 000a C046     		.section	.text.GPIO_Write,"ax",%progbits
 706              		.align	1
 707              		.p2align 2,,3
 708              		.global	GPIO_Write
 709              		.syntax unified
 710              		.code	16
 711              		.thumb_func
 713              	GPIO_Write:
 714              	.LVL53:
 715              	.LFB56:
 401:Library/src/lcm32f06x_gpio.c **** 
 402:Library/src/lcm32f06x_gpio.c **** /**
 403:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_Write
 404:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Writes data to the specified GPIO data port.
 405:Library/src/lcm32f06x_gpio.c ****   *         CN: 将数据写入指定的GPIO数据端口。
 406:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 407:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 408:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 409:Library/src/lcm32f06x_gpio.c ****   * @param  PortVal:
 410:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the value to be written to the port output data register.
 411:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入端口输出数据寄存器的值。
 412:Library/src/lcm32f06x_gpio.c ****   * @retval None
 413:Library/src/lcm32f06x_gpio.c ****   */
 414:Library/src/lcm32f06x_gpio.c **** void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
 415:Library/src/lcm32f06x_gpio.c **** {
 716              		.loc 1 415 1 is_stmt 1 view -0
ARM GAS  /tmp/ccTxDPsK.s 			page 22


 717              		.cfi_startproc
 718              		@ args = 0, pretend = 0, frame = 0
 719              		@ frame_needed = 0, uses_anonymous_args = 0
 720              		@ link register save eliminated.
 416:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 417:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 721              		.loc 1 417 3 view .LVU215
 418:Library/src/lcm32f06x_gpio.c **** 
 419:Library/src/lcm32f06x_gpio.c ****   GPIOx->ODR = PortVal;
 722              		.loc 1 419 3 view .LVU216
 723              		.loc 1 419 14 is_stmt 0 view .LVU217
 724 0000 8161     		str	r1, [r0, #24]
 420:Library/src/lcm32f06x_gpio.c **** }
 725              		.loc 1 420 1 view .LVU218
 726              		@ sp needed
 727 0002 7047     		bx	lr
 728              		.cfi_endproc
 729              	.LFE56:
 731              		.section	.text.GPIO_PinAFConfig,"ax",%progbits
 732              		.align	1
 733              		.p2align 2,,3
 734              		.global	GPIO_PinAFConfig
 735              		.syntax unified
 736              		.code	16
 737              		.thumb_func
 739              	GPIO_PinAFConfig:
 740              	.LVL54:
 741              	.LFB57:
 421:Library/src/lcm32f06x_gpio.c **** 
 422:Library/src/lcm32f06x_gpio.c **** /*
 423:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
 424:Library/src/lcm32f06x_gpio.c ****           ##### GPIO Alternate functions configuration functions #####
 425:Library/src/lcm32f06x_gpio.c ****   ==============================================================================
 426:Library/src/lcm32f06x_gpio.c **** */
 427:Library/src/lcm32f06x_gpio.c **** 
 428:Library/src/lcm32f06x_gpio.c **** /**
 429:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_PinAFConfig
 430:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Configure digital alternate function.
 431:Library/src/lcm32f06x_gpio.c ****   *         CN: 配置数字复用功能。
 432:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 433:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 434:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 435:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_PinSource:
 436:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the pin for the alternate function.
 437:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定复用引脚。
 438:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_AF:
 439:Library/src/lcm32f06x_gpio.c ****   *         EN: Selects the pin to used as alternate function.
 440:Library/src/lcm32f06x_gpio.c ****   *         CN: 选择要用作复用的功能。
 441:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_0: TIM15, TIM16, TIM17, SPI0, MCO, SWDIO, SWCLK, EVENTOUT
 442:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_1: USART0, USART1, TIM1, TIM2, TIM15, TIM16, TIM17, I2C0, 
 443:Library/src/lcm32f06x_gpio.c ****   *                         IR
 444:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_2: TIM1, TIM15, TIM16, TIM17, SPI0, I2C0, USART0
 445:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_3: TIM1, TIM2, TIM15, TIM16, TIM17, USART0, USART1, ACMP0, 
 446:Library/src/lcm32f06x_gpio.c ****   *                         ACMP1
 447:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_4: USART0, USART1, TIM1, SPI0, I2C0, TIM15, TIM16, TIM17 
 448:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_5: TIM1, TIM2, TIM15, TIM16, TI17, SPI0, I2C0, WT, USART0
 449:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_6: ACMP0, ACMP1, TIM1, TIM2, TIM15, TIM16, TIM17, USART0, 
ARM GAS  /tmp/ccTxDPsK.s 			page 23


 450:Library/src/lcm32f06x_gpio.c ****   *                         USART1, I2C0
 451:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AF_7: I2C0, SPI0, USART0, USART1, TIM2, TIM17
 452:Library/src/lcm32f06x_gpio.c ****   * @retval None
 453:Library/src/lcm32f06x_gpio.c ****   */
 454:Library/src/lcm32f06x_gpio.c **** void GPIO_PinAFConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
 455:Library/src/lcm32f06x_gpio.c **** {
 742              		.loc 1 455 1 is_stmt 1 view -0
 743              		.cfi_startproc
 744              		@ args = 0, pretend = 0, frame = 0
 745              		@ frame_needed = 0, uses_anonymous_args = 0
 456:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_1 = 0x00;
 746              		.loc 1 456 3 view .LVU220
 457:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_2 = 0x00;
 747              		.loc 1 457 3 view .LVU221
 458:Library/src/lcm32f06x_gpio.c **** 
 459:Library/src/lcm32f06x_gpio.c ****   /* Check the parameters */
 460:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 748              		.loc 1 460 3 view .LVU222
 461:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
 749              		.loc 1 461 3 view .LVU223
 462:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_AF(GPIO_AF));
 750              		.loc 1 462 3 view .LVU224
 463:Library/src/lcm32f06x_gpio.c **** 
 464:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRL;
 751              		.loc 1 464 3 view .LVU225
 455:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_1 = 0x00;
 752              		.loc 1 455 1 is_stmt 0 view .LVU226
 753 0000 30B5     		push	{r4, r5, lr}
 754              	.LCFI3:
 755              		.cfi_def_cfa_offset 12
 756              		.cfi_offset 4, -12
 757              		.cfi_offset 5, -8
 758              		.cfi_offset 14, -4
 759              		.loc 1 464 9 view .LVU227
 760 0002 456A     		ldr	r5, [r0, #36]
 761              	.LVL55:
 465:Library/src/lcm32f06x_gpio.c ****   tmp_2 = GPIOx->AFRH;
 762              		.loc 1 465 3 is_stmt 1 view .LVU228
 763              		.loc 1 465 9 is_stmt 0 view .LVU229
 764 0004 836A     		ldr	r3, [r0, #40]
 765              	.LVL56:
 466:Library/src/lcm32f06x_gpio.c **** 
 467:Library/src/lcm32f06x_gpio.c ****   if (GPIO_PinSource < 8)
 766              		.loc 1 467 3 is_stmt 1 view .LVU230
 767              		.loc 1 467 6 is_stmt 0 view .LVU231
 768 0006 0729     		cmp	r1, #7
 769 0008 08D8     		bhi	.L49
 468:Library/src/lcm32f06x_gpio.c ****   {
 469:Library/src/lcm32f06x_gpio.c ****     tmp_1 &= ~(0x0F << (GPIO_PinSource * 4));
 770              		.loc 1 469 5 is_stmt 1 view .LVU232
 771              		.loc 1 469 21 is_stmt 0 view .LVU233
 772 000a 0F24     		movs	r4, #15
 773              		.loc 1 469 40 view .LVU234
 774 000c 8900     		lsls	r1, r1, #2
 775              	.LVL57:
 776              		.loc 1 469 21 view .LVU235
 777 000e 8C40     		lsls	r4, r4, r1
ARM GAS  /tmp/ccTxDPsK.s 			page 24


 470:Library/src/lcm32f06x_gpio.c ****     tmp_1 |= (GPIO_AF << (GPIO_PinSource * 4));
 778              		.loc 1 470 23 view .LVU236
 779 0010 8A40     		lsls	r2, r2, r1
 780              	.LVL58:
 469:Library/src/lcm32f06x_gpio.c ****     tmp_1 |= (GPIO_AF << (GPIO_PinSource * 4));
 781              		.loc 1 469 11 view .LVU237
 782 0012 A543     		bics	r5, r4
 783              	.LVL59:
 784              		.loc 1 470 5 is_stmt 1 view .LVU238
 785              		.loc 1 470 11 is_stmt 0 view .LVU239
 786 0014 1543     		orrs	r5, r2
 787              	.LVL60:
 788              	.L50:
 471:Library/src/lcm32f06x_gpio.c ****   }
 472:Library/src/lcm32f06x_gpio.c ****   else
 473:Library/src/lcm32f06x_gpio.c ****   {
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 &= ~(0x0F << ((GPIO_PinSource - 8) * 4));
 475:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 476:Library/src/lcm32f06x_gpio.c ****   }
 477:Library/src/lcm32f06x_gpio.c **** 
 478:Library/src/lcm32f06x_gpio.c ****   GPIOx->AFRL = tmp_1;
 789              		.loc 1 478 3 is_stmt 1 view .LVU240
 790              		.loc 1 478 15 is_stmt 0 view .LVU241
 791 0016 4562     		str	r5, [r0, #36]
 479:Library/src/lcm32f06x_gpio.c ****   GPIOx->AFRH = tmp_2;
 792              		.loc 1 479 3 is_stmt 1 view .LVU242
 480:Library/src/lcm32f06x_gpio.c **** }
 793              		.loc 1 480 1 is_stmt 0 view .LVU243
 794              		@ sp needed
 479:Library/src/lcm32f06x_gpio.c ****   GPIOx->AFRH = tmp_2;
 795              		.loc 1 479 15 view .LVU244
 796 0018 8362     		str	r3, [r0, #40]
 797              	.LVL61:
 798              		.loc 1 480 1 view .LVU245
 799 001a 30BD     		pop	{r4, r5, pc}
 800              	.LVL62:
 801              	.L49:
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 802              		.loc 1 474 5 is_stmt 1 view .LVU246
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 803              		.loc 1 474 21 is_stmt 0 view .LVU247
 804 001c 0F24     		movs	r4, #15
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 805              		.loc 1 474 41 view .LVU248
 806 001e 0839     		subs	r1, r1, #8
 807              	.LVL63:
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 808              		.loc 1 474 46 view .LVU249
 809 0020 8900     		lsls	r1, r1, #2
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
 810              		.loc 1 474 21 view .LVU250
 811 0022 8C40     		lsls	r4, r4, r1
 475:Library/src/lcm32f06x_gpio.c ****   }
 812              		.loc 1 475 23 view .LVU251
 813 0024 8A40     		lsls	r2, r2, r1
 814              	.LVL64:
 474:Library/src/lcm32f06x_gpio.c ****     tmp_2 |= (GPIO_AF << ((GPIO_PinSource - 8) * 4));
ARM GAS  /tmp/ccTxDPsK.s 			page 25


 815              		.loc 1 474 11 view .LVU252
 816 0026 A343     		bics	r3, r4
 817              	.LVL65:
 475:Library/src/lcm32f06x_gpio.c ****   }
 818              		.loc 1 475 5 is_stmt 1 view .LVU253
 475:Library/src/lcm32f06x_gpio.c ****   }
 819              		.loc 1 475 11 is_stmt 0 view .LVU254
 820 0028 1343     		orrs	r3, r2
 821              	.LVL66:
 475:Library/src/lcm32f06x_gpio.c ****   }
 822              		.loc 1 475 11 view .LVU255
 823 002a F4E7     		b	.L50
 824              		.cfi_endproc
 825              	.LFE57:
 827              		.section	.text.GPIO_DriveConfig,"ax",%progbits
 828              		.align	1
 829              		.p2align 2,,3
 830              		.global	GPIO_DriveConfig
 831              		.syntax unified
 832              		.code	16
 833              		.thumb_func
 835              	GPIO_DriveConfig:
 836              	.LVL67:
 837              	.LFB58:
 481:Library/src/lcm32f06x_gpio.c **** 
 482:Library/src/lcm32f06x_gpio.c **** /**
 483:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_DriveConfig
 484:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: GPIO drive capability configuration.
 485:Library/src/lcm32f06x_gpio.c ****   *         CN: GPIO 驱动器功能配置。
 486:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 487:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 488:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 489:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 490:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 491:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 492:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Drive:
 493:Library/src/lcm32f06x_gpio.c ****   *         EN: Select the driver mode to be configured.
 494:Library/src/lcm32f06x_gpio.c ****   *         CN: 选择要配置的驱动模式。
 495:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_Drive_Level_strong
 496:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_Drive_Level_weak
 497:Library/src/lcm32f06x_gpio.c ****   * @retval None
 498:Library/src/lcm32f06x_gpio.c ****   */
 499:Library/src/lcm32f06x_gpio.c **** void GPIO_DriveConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint16_t GPIO_Drive)
 500:Library/src/lcm32f06x_gpio.c **** {
 838              		.loc 1 500 1 is_stmt 1 view -0
 839              		.cfi_startproc
 840              		@ args = 0, pretend = 0, frame = 0
 841              		@ frame_needed = 0, uses_anonymous_args = 0
 842              		@ link register save eliminated.
 501:Library/src/lcm32f06x_gpio.c ****   uint32_t tmppreg = 0;
 843              		.loc 1 501 3 view .LVU257
 502:Library/src/lcm32f06x_gpio.c **** 
 503:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 844              		.loc 1 503 3 view .LVU258
 504:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 845              		.loc 1 504 3 view .LVU259
 505:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_LEVEL(GPIO_Drive));
ARM GAS  /tmp/ccTxDPsK.s 			page 26


 846              		.loc 1 505 3 view .LVU260
 506:Library/src/lcm32f06x_gpio.c **** 
 507:Library/src/lcm32f06x_gpio.c ****   tmppreg = GPIOx->DR_BSRR;
 847              		.loc 1 507 3 view .LVU261
 848              		.loc 1 507 11 is_stmt 0 view .LVU262
 849 0000 036B     		ldr	r3, [r0, #48]
 850              	.LVL68:
 508:Library/src/lcm32f06x_gpio.c ****   if (GPIO_Drive == GPIO_Drive_Level_strong)
 851              		.loc 1 508 3 is_stmt 1 view .LVU263
 852              		.loc 1 508 6 is_stmt 0 view .LVU264
 853 0002 002A     		cmp	r2, #0
 854 0004 04D1     		bne	.L52
 509:Library/src/lcm32f06x_gpio.c ****   {
 510:Library/src/lcm32f06x_gpio.c ****     tmppreg &= ~GPIO_Pin;
 855              		.loc 1 510 5 is_stmt 1 view .LVU265
 856              		.loc 1 510 13 is_stmt 0 view .LVU266
 857 0006 8B43     		bics	r3, r1
 858              	.LVL69:
 511:Library/src/lcm32f06x_gpio.c ****     tmppreg |= (GPIO_Pin << 16);
 859              		.loc 1 511 5 is_stmt 1 view .LVU267
 860              		.loc 1 511 26 is_stmt 0 view .LVU268
 861 0008 0904     		lsls	r1, r1, #16
 862              	.LVL70:
 863              		.loc 1 511 13 view .LVU269
 864 000a 0B43     		orrs	r3, r1
 865              	.LVL71:
 866              	.L53:
 512:Library/src/lcm32f06x_gpio.c ****   }
 513:Library/src/lcm32f06x_gpio.c ****   else
 514:Library/src/lcm32f06x_gpio.c ****   {
 515:Library/src/lcm32f06x_gpio.c ****     tmppreg |= (GPIO_Pin);
 516:Library/src/lcm32f06x_gpio.c ****   }
 517:Library/src/lcm32f06x_gpio.c **** 
 518:Library/src/lcm32f06x_gpio.c ****   GPIOx->DR_BSRR = tmppreg;
 867              		.loc 1 518 3 is_stmt 1 view .LVU270
 868              		.loc 1 518 18 is_stmt 0 view .LVU271
 869 000c 0363     		str	r3, [r0, #48]
 519:Library/src/lcm32f06x_gpio.c **** }
 870              		.loc 1 519 1 view .LVU272
 871              		@ sp needed
 872 000e 7047     		bx	lr
 873              	.LVL72:
 874              	.L52:
 515:Library/src/lcm32f06x_gpio.c ****   }
 875              		.loc 1 515 5 is_stmt 1 view .LVU273
 515:Library/src/lcm32f06x_gpio.c ****   }
 876              		.loc 1 515 13 is_stmt 0 view .LVU274
 877 0010 0B43     		orrs	r3, r1
 878              	.LVL73:
 515:Library/src/lcm32f06x_gpio.c ****   }
 879              		.loc 1 515 13 view .LVU275
 880 0012 FBE7     		b	.L53
 881              		.cfi_endproc
 882              	.LFE58:
 884              		.section	.text.GPIO_BitToggle,"ax",%progbits
 885              		.align	1
 886              		.p2align 2,,3
ARM GAS  /tmp/ccTxDPsK.s 			page 27


 887              		.global	GPIO_BitToggle
 888              		.syntax unified
 889              		.code	16
 890              		.thumb_func
 892              	GPIO_BitToggle:
 893              	.LVL74:
 894              	.LFB59:
 520:Library/src/lcm32f06x_gpio.c **** 
 521:Library/src/lcm32f06x_gpio.c **** /**
 522:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_BitToggle
 523:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: GPIO flip configuration.
 524:Library/src/lcm32f06x_gpio.c ****   *         CN: GPIO 翻转配置。
 525:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 526:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 527:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 528:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 529:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 530:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 531:Library/src/lcm32f06x_gpio.c ****   * @retval None
 532:Library/src/lcm32f06x_gpio.c ****   */
 533:Library/src/lcm32f06x_gpio.c **** void GPIO_BitToggle(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
 534:Library/src/lcm32f06x_gpio.c **** {
 895              		.loc 1 534 1 is_stmt 1 view -0
 896              		.cfi_startproc
 897              		@ args = 0, pretend = 0, frame = 0
 898              		@ frame_needed = 0, uses_anonymous_args = 0
 899              		@ link register save eliminated.
 535:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 900              		.loc 1 535 3 view .LVU277
 536:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 901              		.loc 1 536 3 view .LVU278
 537:Library/src/lcm32f06x_gpio.c **** 
 538:Library/src/lcm32f06x_gpio.c ****   GPIOx->BTGLR = GPIO_Pin;
 902              		.loc 1 538 3 view .LVU279
 903              		.loc 1 538 16 is_stmt 0 view .LVU280
 904 0000 C162     		str	r1, [r0, #44]
 539:Library/src/lcm32f06x_gpio.c **** }
 905              		.loc 1 539 1 view .LVU281
 906              		@ sp needed
 907 0002 7047     		bx	lr
 908              		.cfi_endproc
 909              	.LFE59:
 911              		.section	.text.GPIO_InputCMOSCmd,"ax",%progbits
 912              		.align	1
 913              		.p2align 2,,3
 914              		.global	GPIO_InputCMOSCmd
 915              		.syntax unified
 916              		.code	16
 917              		.thumb_func
 919              	GPIO_InputCMOSCmd:
 920              	.LVL75:
 921              	.LFB60:
 540:Library/src/lcm32f06x_gpio.c **** 
 541:Library/src/lcm32f06x_gpio.c **** /**
 542:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_InputCMOSCmd
 543:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Configure CMOS and Schmitt triggers.
 544:Library/src/lcm32f06x_gpio.c ****   *         CN: 配置 CMOS 和 施密特触发器。
ARM GAS  /tmp/ccTxDPsK.s 			page 28


 545:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 546:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 547:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 548:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_Pin: 
 549:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the port bit to be written.
 550:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定要写入的端口。
 551:Library/src/lcm32f06x_gpio.c ****   * @param  NewState: 
 552:Library/src/lcm32f06x_gpio.c ****   *         EN: New state of the GPIOx peripheral.
 553:Library/src/lcm32f06x_gpio.c ****   *         CN: GPIOx 外设的新状态。
 554:Library/src/lcm32f06x_gpio.c ****   *             @arg ENABLE
 555:Library/src/lcm32f06x_gpio.c ****   *             @arg DISABLE
 556:Library/src/lcm32f06x_gpio.c ****   * @retval None
 557:Library/src/lcm32f06x_gpio.c ****   */
 558:Library/src/lcm32f06x_gpio.c **** void GPIO_InputCMOSCmd(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, FunctionalState NewState)
 559:Library/src/lcm32f06x_gpio.c **** {
 922              		.loc 1 559 1 is_stmt 1 view -0
 923              		.cfi_startproc
 924              		@ args = 0, pretend = 0, frame = 0
 925              		@ frame_needed = 0, uses_anonymous_args = 0
 926              		@ link register save eliminated.
 560:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
 927              		.loc 1 560 3 view .LVU283
 561:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN(GPIO_Pin));
 928              		.loc 1 561 3 view .LVU284
 562:Library/src/lcm32f06x_gpio.c **** 
 563:Library/src/lcm32f06x_gpio.c ****   if (NewState != DISABLE)
 929              		.loc 1 563 3 view .LVU285
 930              		.loc 1 563 6 is_stmt 0 view .LVU286
 931 0000 002A     		cmp	r2, #0
 932 0002 00D1     		bne	.L58
 564:Library/src/lcm32f06x_gpio.c ****   {
 565:Library/src/lcm32f06x_gpio.c ****     /* The CMOS as input */
 566:Library/src/lcm32f06x_gpio.c ****     GPIOx->CS_BSRR = GPIO_Pin;
 567:Library/src/lcm32f06x_gpio.c ****   }
 568:Library/src/lcm32f06x_gpio.c ****   else
 569:Library/src/lcm32f06x_gpio.c ****   {
 570:Library/src/lcm32f06x_gpio.c ****     /* The Schmitt trigger as default input */
 571:Library/src/lcm32f06x_gpio.c ****     GPIOx->CS_BSRR = GPIO_Pin << 16;
 933              		.loc 1 571 5 is_stmt 1 view .LVU287
 934              		.loc 1 571 31 is_stmt 0 view .LVU288
 935 0004 0904     		lsls	r1, r1, #16
 936              	.LVL76:
 937              	.L58:
 938              		.loc 1 571 20 view .LVU289
 939 0006 4163     		str	r1, [r0, #52]
 572:Library/src/lcm32f06x_gpio.c ****   }
 573:Library/src/lcm32f06x_gpio.c **** }
 940              		.loc 1 573 1 view .LVU290
 941              		@ sp needed
 942 0008 7047     		bx	lr
 943              		.cfi_endproc
 944              	.LFE60:
 946 000a C046     		.section	.text.GPIO_AnaModeSet,"ax",%progbits
 947              		.align	1
 948              		.p2align 2,,3
 949              		.global	GPIO_AnaModeSet
 950              		.syntax unified
ARM GAS  /tmp/ccTxDPsK.s 			page 29


 951              		.code	16
 952              		.thumb_func
 954              	GPIO_AnaModeSet:
 955              	.LVL77:
 956              	.LFB61:
 574:Library/src/lcm32f06x_gpio.c **** 
 575:Library/src/lcm32f06x_gpio.c **** /**
 576:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_AnaModeSet
 577:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Configure analog alternate function.
 578:Library/src/lcm32f06x_gpio.c ****   *         CN: 配置模拟复用功能。
 579:Library/src/lcm32f06x_gpio.c ****   * @param  GPIOx:
 580:Library/src/lcm32f06x_gpio.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 581:Library/src/lcm32f06x_gpio.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设。
 582:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_PinSource:
 583:Library/src/lcm32f06x_gpio.c ****   *         EN: Specifies the pin for the alternate function.
 584:Library/src/lcm32f06x_gpio.c ****   *         CN: 指定复用引脚。
 585:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_AN1: 
 586:Library/src/lcm32f06x_gpio.c ****   *         EN: Analog channel 0  enable/disable.
 587:Library/src/lcm32f06x_gpio.c ****   *         CN: 模拟通道 0 使能/禁止。
 588:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AN_ENABLE
 589:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AN_DISABLE
 590:Library/src/lcm32f06x_gpio.c ****   * @param  GPIO_AN2: 
 591:Library/src/lcm32f06x_gpio.c ****   *         EN: Analog channel 1  enable/disable.
 592:Library/src/lcm32f06x_gpio.c ****   *         CN: 模拟通道 1 使能/禁止。
 593:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AN_ENABLE
 594:Library/src/lcm32f06x_gpio.c ****   *             @arg GPIO_AN_DISABLE
 595:Library/src/lcm32f06x_gpio.c ****   * @retval None
 596:Library/src/lcm32f06x_gpio.c ****   */
 597:Library/src/lcm32f06x_gpio.c **** void GPIO_AnaModeSet(GPIO_TypeDef *GPIOx, uint16_t GPIO_PinSource, uint32_t GPIO_AN1, uint32_t GPIO
 598:Library/src/lcm32f06x_gpio.c **** {
 957              		.loc 1 598 1 is_stmt 1 view -0
 958              		.cfi_startproc
 959              		@ args = 0, pretend = 0, frame = 0
 960              		@ frame_needed = 0, uses_anonymous_args = 0
 599:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_0 = 0x00000000;
 961              		.loc 1 599 3 view .LVU292
 600:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_1 = 0x00000000;
 962              		.loc 1 600 3 view .LVU293
 601:Library/src/lcm32f06x_gpio.c **** 
 602:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
 963              		.loc 1 602 3 view .LVU294
 603:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_AN(GPIO_AN1));
 964              		.loc 1 603 3 view .LVU295
 604:Library/src/lcm32f06x_gpio.c ****   assert_param(IS_GPIO_AN(GPIO_AN2));
 965              		.loc 1 604 3 view .LVU296
 605:Library/src/lcm32f06x_gpio.c **** 
 606:Library/src/lcm32f06x_gpio.c ****   /* Set the pin as analog alternate function AN */
 607:Library/src/lcm32f06x_gpio.c ****   GPIOx->MODER |= (0x3 << (GPIO_PinSource << 1));
 966              		.loc 1 607 3 view .LVU297
 598:Library/src/lcm32f06x_gpio.c ****   uint32_t tmp_0 = 0x00000000;
 967              		.loc 1 598 1 is_stmt 0 view .LVU298
 968 0000 70B5     		push	{r4, r5, r6, lr}
 969              	.LCFI4:
 970              		.cfi_def_cfa_offset 16
 971              		.cfi_offset 4, -16
 972              		.cfi_offset 5, -12
 973              		.cfi_offset 6, -8
ARM GAS  /tmp/ccTxDPsK.s 			page 30


 974              		.cfi_offset 14, -4
 975              		.loc 1 607 24 view .LVU299
 976 0002 0324     		movs	r4, #3
 977              		.loc 1 607 43 view .LVU300
 978 0004 4E00     		lsls	r6, r1, #1
 979              		.loc 1 607 24 view .LVU301
 980 0006 B440     		lsls	r4, r4, r6
 981              		.loc 1 607 8 view .LVU302
 982 0008 0568     		ldr	r5, [r0]
 608:Library/src/lcm32f06x_gpio.c ****   
 609:Library/src/lcm32f06x_gpio.c ****   /* Clear the bits to be set  */
 610:Library/src/lcm32f06x_gpio.c ****   tmp_0 = GPIOx->AFRL & ~(0xF << (GPIO_PinSource << 2));
 611:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 612:Library/src/lcm32f06x_gpio.c **** 
 613:Library/src/lcm32f06x_gpio.c ****   if (GPIO_PinSource < 8)
 614:Library/src/lcm32f06x_gpio.c ****   {
 615:Library/src/lcm32f06x_gpio.c ****     GPIOx->AFRL = tmp_0 | ((GPIO_AN1 | (GPIO_AN2 << 1)) << (GPIO_PinSource << 2));
 983              		.loc 1 615 50 view .LVU303
 984 000a 5B00     		lsls	r3, r3, #1
 985              	.LVL78:
 607:Library/src/lcm32f06x_gpio.c ****   
 986              		.loc 1 607 16 view .LVU304
 987 000c 2C43     		orrs	r4, r5
 988 000e 0460     		str	r4, [r0]
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 989              		.loc 1 610 3 is_stmt 1 view .LVU305
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 990              		.loc 1 610 16 is_stmt 0 view .LVU306
 991 0010 456A     		ldr	r5, [r0, #36]
 992              	.LVL79:
 611:Library/src/lcm32f06x_gpio.c **** 
 993              		.loc 1 611 3 is_stmt 1 view .LVU307
 994              		.loc 1 615 38 is_stmt 0 view .LVU308
 995 0012 1343     		orrs	r3, r2
 611:Library/src/lcm32f06x_gpio.c **** 
 996              		.loc 1 611 16 view .LVU309
 997 0014 846A     		ldr	r4, [r0, #40]
 998              	.LVL80:
 613:Library/src/lcm32f06x_gpio.c ****   {
 999              		.loc 1 613 3 is_stmt 1 view .LVU310
 613:Library/src/lcm32f06x_gpio.c ****   {
 1000              		.loc 1 613 6 is_stmt 0 view .LVU311
 1001 0016 0729     		cmp	r1, #7
 1002 0018 07D8     		bhi	.L60
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 1003              		.loc 1 610 31 view .LVU312
 1004 001a 0F22     		movs	r2, #15
 1005              	.LVL81:
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 1006              		.loc 1 610 50 view .LVU313
 1007 001c 8900     		lsls	r1, r1, #2
 1008              	.LVL82:
 1009              		.loc 1 615 5 is_stmt 1 view .LVU314
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 1010              		.loc 1 610 31 is_stmt 0 view .LVU315
 1011 001e 8A40     		lsls	r2, r2, r1
 1012              		.loc 1 615 57 view .LVU316
ARM GAS  /tmp/ccTxDPsK.s 			page 31


 1013 0020 8B40     		lsls	r3, r3, r1
 610:Library/src/lcm32f06x_gpio.c ****   tmp_1 = GPIOx->AFRH & ~(0xf << ((GPIO_PinSource - 8) << 2));
 1014              		.loc 1 610 9 view .LVU317
 1015 0022 9543     		bics	r5, r2
 1016              	.LVL83:
 1017              		.loc 1 615 25 view .LVU318
 1018 0024 1D43     		orrs	r5, r3
 1019              		.loc 1 615 17 view .LVU319
 1020 0026 4562     		str	r5, [r0, #36]
 1021              	.LVL84:
 1022              	.L59:
 616:Library/src/lcm32f06x_gpio.c ****   }
 617:Library/src/lcm32f06x_gpio.c ****   else
 618:Library/src/lcm32f06x_gpio.c ****   {
 619:Library/src/lcm32f06x_gpio.c ****     GPIOx->AFRH = tmp_1 | ((GPIO_AN1 | (GPIO_AN2 << 1)) << ((GPIO_PinSource - 8) << 2));
 620:Library/src/lcm32f06x_gpio.c ****   }
 621:Library/src/lcm32f06x_gpio.c **** }
 1023              		.loc 1 621 1 view .LVU320
 1024              		@ sp needed
 1025 0028 70BD     		pop	{r4, r5, r6, pc}
 1026              	.LVL85:
 1027              	.L60:
 611:Library/src/lcm32f06x_gpio.c **** 
 1028              		.loc 1 611 31 view .LVU321
 1029 002a 0F22     		movs	r2, #15
 1030              	.LVL86:
 611:Library/src/lcm32f06x_gpio.c **** 
 1031              		.loc 1 611 51 view .LVU322
 1032 002c 0839     		subs	r1, r1, #8
 1033              	.LVL87:
 611:Library/src/lcm32f06x_gpio.c **** 
 1034              		.loc 1 611 56 view .LVU323
 1035 002e 8900     		lsls	r1, r1, #2
 619:Library/src/lcm32f06x_gpio.c ****   }
 1036              		.loc 1 619 5 is_stmt 1 view .LVU324
 611:Library/src/lcm32f06x_gpio.c **** 
 1037              		.loc 1 611 31 is_stmt 0 view .LVU325
 1038 0030 8A40     		lsls	r2, r2, r1
 619:Library/src/lcm32f06x_gpio.c ****   }
 1039              		.loc 1 619 57 view .LVU326
 1040 0032 8B40     		lsls	r3, r3, r1
 611:Library/src/lcm32f06x_gpio.c **** 
 1041              		.loc 1 611 9 view .LVU327
 1042 0034 9443     		bics	r4, r2
 1043              	.LVL88:
 619:Library/src/lcm32f06x_gpio.c ****   }
 1044              		.loc 1 619 25 view .LVU328
 1045 0036 1C43     		orrs	r4, r3
 619:Library/src/lcm32f06x_gpio.c ****   }
 1046              		.loc 1 619 17 view .LVU329
 1047 0038 8462     		str	r4, [r0, #40]
 1048              		.loc 1 621 1 view .LVU330
 1049 003a F5E7     		b	.L59
 1050              		.cfi_endproc
 1051              	.LFE61:
 1053              		.section	.text.GPIO_ResetPB2Config,"ax",%progbits
 1054              		.align	1
ARM GAS  /tmp/ccTxDPsK.s 			page 32


 1055              		.p2align 2,,3
 1056              		.global	GPIO_ResetPB2Config
 1057              		.syntax unified
 1058              		.code	16
 1059              		.thumb_func
 1061              	GPIO_ResetPB2Config:
 1062              	.LVL89:
 1063              	.LFB62:
 622:Library/src/lcm32f06x_gpio.c **** 
 623:Library/src/lcm32f06x_gpio.c **** /**
 624:Library/src/lcm32f06x_gpio.c ****   * @name   GPIO_ResetPB2Config
 625:Library/src/lcm32f06x_gpio.c ****   * @brief  EN: Reset pin PB2 is used as a regular GPIO.
 626:Library/src/lcm32f06x_gpio.c ****   *         CN: reset引脚PB2作为普通GPIO使用。
 627:Library/src/lcm32f06x_gpio.c ****   * @param  NewState: 
 628:Library/src/lcm32f06x_gpio.c ****   *         EN: Enable/disable.
 629:Library/src/lcm32f06x_gpio.c ****   *         CN: 使能/关闭。
 630:Library/src/lcm32f06x_gpio.c ****   * @retval None
 631:Library/src/lcm32f06x_gpio.c ****   */
 632:Library/src/lcm32f06x_gpio.c **** void GPIO_ResetPB2Config(uint32_t NewState)
 633:Library/src/lcm32f06x_gpio.c **** {
 1064              		.loc 1 633 1 is_stmt 1 view -0
 1065              		.cfi_startproc
 1066              		@ args = 0, pretend = 0, frame = 0
 1067              		@ frame_needed = 0, uses_anonymous_args = 0
 634:Library/src/lcm32f06x_gpio.c ****   if (NewState != DISABLE)
 1068              		.loc 1 634 3 view .LVU332
 633:Library/src/lcm32f06x_gpio.c ****   if (NewState != DISABLE)
 1069              		.loc 1 633 1 is_stmt 0 view .LVU333
 1070 0000 70B5     		push	{r4, r5, r6, lr}
 1071              	.LCFI5:
 1072              		.cfi_def_cfa_offset 16
 1073              		.cfi_offset 4, -16
 1074              		.cfi_offset 5, -12
 1075              		.cfi_offset 6, -8
 1076              		.cfi_offset 14, -4
 1077              		.loc 1 634 6 view .LVU334
 1078 0002 0028     		cmp	r0, #0
 1079 0004 0ED0     		beq	.L63
 635:Library/src/lcm32f06x_gpio.c ****   {
 636:Library/src/lcm32f06x_gpio.c ****     chipctrl_access();
 1080              		.loc 1 636 5 is_stmt 1 view .LVU335
 1081              	.LBB26:
 1082              	.LBI26:
 1083              		.file 2 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
ARM GAS  /tmp/ccTxDPsK.s 			page 33


  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
ARM GAS  /tmp/ccTxDPsK.s 			page 34


  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
ARM GAS  /tmp/ccTxDPsK.s 			page 35


 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccTxDPsK.s 			page 36


 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/ccTxDPsK.s 			page 37


 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 1084              		.loc 2 258 27 view .LVU336
 1085              	.LBB27:
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 1086              		.loc 2 260 3 view .LVU337
 1087              		.syntax divided
 1088              	@ 260 "Core/cmsis_gcc.h" 1
 1089 0006 BFF36F8F 		isb 0xF
 1090              	@ 0 "" 2
 1091              		.thumb
 1092              		.syntax unified
 1093              	.LBE27:
 1094              	.LBE26:
 1095              		.loc 1 636 5 discriminator 1 view .LVU338
 1096              	.LBB28:
 1097              	.LBI28:
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccTxDPsK.s 			page 38


 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
ARM GAS  /tmp/ccTxDPsK.s 			page 39


 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
ARM GAS  /tmp/ccTxDPsK.s 			page 40


 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccTxDPsK.s 			page 41


 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
ARM GAS  /tmp/ccTxDPsK.s 			page 42


 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccTxDPsK.s 			page 43


 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
ARM GAS  /tmp/ccTxDPsK.s 			page 44


 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccTxDPsK.s 			page 45


 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
ARM GAS  /tmp/ccTxDPsK.s 			page 46


 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
ARM GAS  /tmp/ccTxDPsK.s 			page 47


 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
ARM GAS  /tmp/ccTxDPsK.s 			page 48


 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
ARM GAS  /tmp/ccTxDPsK.s 			page 49


 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 963:Core/cmsis_gcc.h **** }
 964:Core/cmsis_gcc.h **** 
 965:Core/cmsis_gcc.h **** 
 966:Core/cmsis_gcc.h **** /**
 967:Core/cmsis_gcc.h ****   \brief   Get Control Register
 968:Core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
ARM GAS  /tmp/ccTxDPsK.s 			page 50


 969:Core/cmsis_gcc.h ****   \return               Control Register value
 970:Core/cmsis_gcc.h ****  */
 971:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 972:Core/cmsis_gcc.h **** {
 973:Core/cmsis_gcc.h ****   uint32_t result;
 974:Core/cmsis_gcc.h **** 
 975:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 976:Core/cmsis_gcc.h ****   return(result);
 977:Core/cmsis_gcc.h **** }
 978:Core/cmsis_gcc.h **** 
 979:Core/cmsis_gcc.h **** 
 980:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 981:Core/cmsis_gcc.h **** /**
 982:Core/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 983:Core/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 984:Core/cmsis_gcc.h ****   \return               non-secure Control Register value
 985:Core/cmsis_gcc.h ****  */
 986:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 987:Core/cmsis_gcc.h **** {
 988:Core/cmsis_gcc.h ****   uint32_t result;
 989:Core/cmsis_gcc.h **** 
 990:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 991:Core/cmsis_gcc.h ****   return(result);
 992:Core/cmsis_gcc.h **** }
 993:Core/cmsis_gcc.h **** #endif
 994:Core/cmsis_gcc.h **** 
 995:Core/cmsis_gcc.h **** 
 996:Core/cmsis_gcc.h **** /**
 997:Core/cmsis_gcc.h ****   \brief   Set Control Register
 998:Core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 999:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1000:Core/cmsis_gcc.h ****  */
1001:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1002:Core/cmsis_gcc.h **** {
1003:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1004:Core/cmsis_gcc.h ****   __ISB();
1005:Core/cmsis_gcc.h **** }
1006:Core/cmsis_gcc.h **** 
1007:Core/cmsis_gcc.h **** 
1008:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1009:Core/cmsis_gcc.h **** /**
1010:Core/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
1011:Core/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
1012:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1013:Core/cmsis_gcc.h ****  */
1014:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1015:Core/cmsis_gcc.h **** {
1016:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1017:Core/cmsis_gcc.h ****   __ISB();
1018:Core/cmsis_gcc.h **** }
1019:Core/cmsis_gcc.h **** #endif
1020:Core/cmsis_gcc.h **** 
1021:Core/cmsis_gcc.h **** 
1022:Core/cmsis_gcc.h **** /**
1023:Core/cmsis_gcc.h ****   \brief   Get IPSR Register
1024:Core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
1025:Core/cmsis_gcc.h ****   \return               IPSR Register value
ARM GAS  /tmp/ccTxDPsK.s 			page 51


1026:Core/cmsis_gcc.h ****  */
1027:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1028:Core/cmsis_gcc.h **** {
1029:Core/cmsis_gcc.h ****   uint32_t result;
1030:Core/cmsis_gcc.h **** 
1031:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1032:Core/cmsis_gcc.h ****   return(result);
1033:Core/cmsis_gcc.h **** }
1034:Core/cmsis_gcc.h **** 
1035:Core/cmsis_gcc.h **** 
1036:Core/cmsis_gcc.h **** /**
1037:Core/cmsis_gcc.h ****   \brief   Get APSR Register
1038:Core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
1039:Core/cmsis_gcc.h ****   \return               APSR Register value
1040:Core/cmsis_gcc.h ****  */
1041:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1042:Core/cmsis_gcc.h **** {
1043:Core/cmsis_gcc.h ****   uint32_t result;
1044:Core/cmsis_gcc.h **** 
1045:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1046:Core/cmsis_gcc.h ****   return(result);
1047:Core/cmsis_gcc.h **** }
1048:Core/cmsis_gcc.h **** 
1049:Core/cmsis_gcc.h **** 
1050:Core/cmsis_gcc.h **** /**
1051:Core/cmsis_gcc.h ****   \brief   Get xPSR Register
1052:Core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
1053:Core/cmsis_gcc.h ****   \return               xPSR Register value
1054:Core/cmsis_gcc.h ****  */
1055:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1056:Core/cmsis_gcc.h **** {
1057:Core/cmsis_gcc.h ****   uint32_t result;
1058:Core/cmsis_gcc.h **** 
1059:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1060:Core/cmsis_gcc.h ****   return(result);
1061:Core/cmsis_gcc.h **** }
1062:Core/cmsis_gcc.h **** 
1063:Core/cmsis_gcc.h **** 
1064:Core/cmsis_gcc.h **** /**
1065:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
1066:Core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
1067:Core/cmsis_gcc.h ****   \return               PSP Register value
1068:Core/cmsis_gcc.h ****  */
1069:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1070:Core/cmsis_gcc.h **** {
1071:Core/cmsis_gcc.h ****   uint32_t result;
1072:Core/cmsis_gcc.h **** 
1073:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
1074:Core/cmsis_gcc.h ****   return(result);
1075:Core/cmsis_gcc.h **** }
1076:Core/cmsis_gcc.h **** 
1077:Core/cmsis_gcc.h **** 
1078:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1079:Core/cmsis_gcc.h **** /**
1080:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
1081:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
1082:Core/cmsis_gcc.h ****   \return               PSP Register value
ARM GAS  /tmp/ccTxDPsK.s 			page 52


1083:Core/cmsis_gcc.h ****  */
1084:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1085:Core/cmsis_gcc.h **** {
1086:Core/cmsis_gcc.h ****   uint32_t result;
1087:Core/cmsis_gcc.h **** 
1088:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
1089:Core/cmsis_gcc.h ****   return(result);
1090:Core/cmsis_gcc.h **** }
1091:Core/cmsis_gcc.h **** #endif
1092:Core/cmsis_gcc.h **** 
1093:Core/cmsis_gcc.h **** 
1094:Core/cmsis_gcc.h **** /**
1095:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
1096:Core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
1097:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1098:Core/cmsis_gcc.h ****  */
1099:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1100:Core/cmsis_gcc.h **** {
1101:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1102:Core/cmsis_gcc.h **** }
1103:Core/cmsis_gcc.h **** 
1104:Core/cmsis_gcc.h **** 
1105:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1106:Core/cmsis_gcc.h **** /**
1107:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
1108:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
1109:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1110:Core/cmsis_gcc.h ****  */
1111:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1112:Core/cmsis_gcc.h **** {
1113:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1114:Core/cmsis_gcc.h **** }
1115:Core/cmsis_gcc.h **** #endif
1116:Core/cmsis_gcc.h **** 
1117:Core/cmsis_gcc.h **** 
1118:Core/cmsis_gcc.h **** /**
1119:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
1120:Core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
1121:Core/cmsis_gcc.h ****   \return               MSP Register value
1122:Core/cmsis_gcc.h ****  */
1123:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1124:Core/cmsis_gcc.h **** {
1125:Core/cmsis_gcc.h ****   uint32_t result;
1126:Core/cmsis_gcc.h **** 
1127:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
1128:Core/cmsis_gcc.h ****   return(result);
1129:Core/cmsis_gcc.h **** }
1130:Core/cmsis_gcc.h **** 
1131:Core/cmsis_gcc.h **** 
1132:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1133:Core/cmsis_gcc.h **** /**
1134:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
1135:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
1136:Core/cmsis_gcc.h ****   \return               MSP Register value
1137:Core/cmsis_gcc.h ****  */
1138:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1139:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccTxDPsK.s 			page 53


1140:Core/cmsis_gcc.h ****   uint32_t result;
1141:Core/cmsis_gcc.h **** 
1142:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1143:Core/cmsis_gcc.h ****   return(result);
1144:Core/cmsis_gcc.h **** }
1145:Core/cmsis_gcc.h **** #endif
1146:Core/cmsis_gcc.h **** 
1147:Core/cmsis_gcc.h **** 
1148:Core/cmsis_gcc.h **** /**
1149:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
1150:Core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
1151:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1152:Core/cmsis_gcc.h ****  */
1153:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1154:Core/cmsis_gcc.h **** {
1155:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1156:Core/cmsis_gcc.h **** }
1157:Core/cmsis_gcc.h **** 
1158:Core/cmsis_gcc.h **** 
1159:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1160:Core/cmsis_gcc.h **** /**
1161:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
1162:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1163:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1164:Core/cmsis_gcc.h ****  */
1165:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1166:Core/cmsis_gcc.h **** {
1167:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1168:Core/cmsis_gcc.h **** }
1169:Core/cmsis_gcc.h **** #endif
1170:Core/cmsis_gcc.h **** 
1171:Core/cmsis_gcc.h **** 
1172:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1173:Core/cmsis_gcc.h **** /**
1174:Core/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
1175:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1176:Core/cmsis_gcc.h ****   \return               SP Register value
1177:Core/cmsis_gcc.h ****  */
1178:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1179:Core/cmsis_gcc.h **** {
1180:Core/cmsis_gcc.h ****   uint32_t result;
1181:Core/cmsis_gcc.h **** 
1182:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1183:Core/cmsis_gcc.h ****   return(result);
1184:Core/cmsis_gcc.h **** }
1185:Core/cmsis_gcc.h **** 
1186:Core/cmsis_gcc.h **** 
1187:Core/cmsis_gcc.h **** /**
1188:Core/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
1189:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1190:Core/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
1191:Core/cmsis_gcc.h ****  */
1192:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1193:Core/cmsis_gcc.h **** {
1194:Core/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1195:Core/cmsis_gcc.h **** }
1196:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/ccTxDPsK.s 			page 54


1197:Core/cmsis_gcc.h **** 
1198:Core/cmsis_gcc.h **** 
1199:Core/cmsis_gcc.h **** /**
1200:Core/cmsis_gcc.h ****   \brief   Get Priority Mask
1201:Core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202:Core/cmsis_gcc.h ****   \return               Priority Mask value
1203:Core/cmsis_gcc.h ****  */
1204:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 1098              		.loc 2 1204 31 view .LVU339
 1099              	.LBB29:
1205:Core/cmsis_gcc.h **** {
1206:Core/cmsis_gcc.h ****   uint32_t result;
 1100              		.loc 2 1206 3 view .LVU340
1207:Core/cmsis_gcc.h **** 
1208:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
 1101              		.loc 2 1208 3 view .LVU341
 1102              		.syntax divided
 1103              	@ 1208 "Core/cmsis_gcc.h" 1
 1104 000a EFF31083 		MRS r3, primask
 1105              	@ 0 "" 2
 1106              	.LVL90:
1209:Core/cmsis_gcc.h ****   return(result);
 1107              		.loc 2 1209 3 view .LVU342
 1108              		.loc 2 1209 3 is_stmt 0 view .LVU343
 1109              		.thumb
 1110              		.syntax unified
 1111              	.LBE29:
 1112              	.LBE28:
 1113              		.loc 1 636 5 is_stmt 1 discriminator 2 view .LVU344
 1114              	.LBB30:
 1115              	.LBI30:
 960:Core/cmsis_gcc.h **** {
 1116              		.loc 2 960 27 view .LVU345
 1117              	.LBB31:
 962:Core/cmsis_gcc.h **** }
 1118              		.loc 2 962 3 view .LVU346
 1119              		.syntax divided
 1120              	@ 962 "Core/cmsis_gcc.h" 1
 1121 000e 72B6     		cpsid i
 1122              	@ 0 "" 2
 1123              		.thumb
 1124              		.syntax unified
 1125              	.LBE31:
 1126              	.LBE30:
 1127              		.loc 1 636 5 discriminator 3 view .LVU347
 1128 0010 274B     		ldr	r3, .L70
 1129 0012 284A     		ldr	r2, .L70+4
 637:Library/src/lcm32f06x_gpio.c ****     CHIPCTRL->BDCR_b.RST_CFG = 0; // PB2作为通用GPIO /PF2 acts as a universal GPIO
 1130              		.loc 1 637 30 is_stmt 0 view .LVU348
 1131 0014 2849     		ldr	r1, .L70+8
 636:Library/src/lcm32f06x_gpio.c ****     CHIPCTRL->BDCR_b.RST_CFG = 0; // PB2作为通用GPIO /PF2 acts as a universal GPIO
 1132              		.loc 1 636 5 discriminator 3 view .LVU349
 1133 0016 1A60     		str	r2, [r3]
 636:Library/src/lcm32f06x_gpio.c ****     CHIPCTRL->BDCR_b.RST_CFG = 0; // PB2作为通用GPIO /PF2 acts as a universal GPIO
 1134              		.loc 1 636 22 is_stmt 1 discriminator 3 view .LVU350
 1135              		.loc 1 637 5 view .LVU351
 1136              		.loc 1 637 30 is_stmt 0 view .LVU352
ARM GAS  /tmp/ccTxDPsK.s 			page 55


 1137 0018 284A     		ldr	r2, .L70+12
 1138 001a 936A     		ldr	r3, [r2, #40]
 1139 001c 0B40     		ands	r3, r1
 1140 001e 9362     		str	r3, [r2, #40]
 638:Library/src/lcm32f06x_gpio.c ****     __dekey();
 1141              		.loc 1 638 5 is_stmt 1 view .LVU353
 1142              	.LBB32:
 1143              	.LBI32:
 949:Core/cmsis_gcc.h **** {
 1144              		.loc 2 949 27 view .LVU354
 1145              	.LBB33:
 951:Core/cmsis_gcc.h **** }
 1146              		.loc 2 951 3 view .LVU355
 1147              		.syntax divided
 1148              	@ 951 "Core/cmsis_gcc.h" 1
 1149 0020 62B6     		cpsie i
 1150              	@ 0 "" 2
 1151              		.thumb
 1152              		.syntax unified
 1153              	.LBE33:
 1154              	.LBE32:
 1155              		.loc 1 638 14 discriminator 1 view .LVU356
 1156              	.LVL91:
 1157              	.L62:
 639:Library/src/lcm32f06x_gpio.c ****   }
 640:Library/src/lcm32f06x_gpio.c ****   else
 641:Library/src/lcm32f06x_gpio.c ****   {
 642:Library/src/lcm32f06x_gpio.c ****     RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
 643:Library/src/lcm32f06x_gpio.c ****     if((GPIOB->MODER & 0x20) && ((GPIOB->AFRL & (0xF << 8)) == 0) && (*(volatile uint16_t *)(0x1fff
 644:Library/src/lcm32f06x_gpio.c ****     {
 645:Library/src/lcm32f06x_gpio.c ****         GPIOB->MODER &= 0xFFFFFFCF;
 646:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR |= 1 << 2;
 647:Library/src/lcm32f06x_gpio.c ****         delay10us(1);
 648:Library/src/lcm32f06x_gpio.c ****         chipctrl_access();
 649:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 650:Library/src/lcm32f06x_gpio.c ****         __dekey();
 651:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR = 1 << 18;
 652:Library/src/lcm32f06x_gpio.c ****         GPIOB->MODER |= 2 << 4;
 653:Library/src/lcm32f06x_gpio.c ****     }
 654:Library/src/lcm32f06x_gpio.c ****     else
 655:Library/src/lcm32f06x_gpio.c ****     {
 656:Library/src/lcm32f06x_gpio.c ****         chipctrl_access();
 657:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 658:Library/src/lcm32f06x_gpio.c ****         __dekey(); 
 659:Library/src/lcm32f06x_gpio.c ****     }
 660:Library/src/lcm32f06x_gpio.c ****   }
 661:Library/src/lcm32f06x_gpio.c **** }
 1158              		.loc 1 661 1 is_stmt 0 view .LVU357
 1159              		@ sp needed
 1160 0022 70BD     		pop	{r4, r5, r6, pc}
 1161              	.LVL92:
 1162              	.L63:
 642:Library/src/lcm32f06x_gpio.c ****     if((GPIOB->MODER & 0x20) && ((GPIOB->AFRL & (0xF << 8)) == 0) && (*(volatile uint16_t *)(0x1fff
 1163              		.loc 1 642 5 is_stmt 1 view .LVU358
 643:Library/src/lcm32f06x_gpio.c ****     {
 1164              		.loc 1 643 22 is_stmt 0 view .LVU359
 1165 0024 2025     		movs	r5, #32
ARM GAS  /tmp/ccTxDPsK.s 			page 56


 643:Library/src/lcm32f06x_gpio.c ****     {
 1166              		.loc 1 643 14 view .LVU360
 1167 0026 264C     		ldr	r4, .L70+16
 642:Library/src/lcm32f06x_gpio.c ****     if((GPIOB->MODER & 0x20) && ((GPIOB->AFRL & (0xF << 8)) == 0) && (*(volatile uint16_t *)(0x1fff
 1168              		.loc 1 642 5 view .LVU361
 1169 0028 0121     		movs	r1, #1
 1170 002a 0220     		movs	r0, #2
 1171              	.LVL93:
 642:Library/src/lcm32f06x_gpio.c ****     if((GPIOB->MODER & 0x20) && ((GPIOB->AFRL & (0xF << 8)) == 0) && (*(volatile uint16_t *)(0x1fff
 1172              		.loc 1 642 5 view .LVU362
 1173 002c FFF7FEFF 		bl	RCC_AHBPeriphClockCmd
 1174              	.LVL94:
 643:Library/src/lcm32f06x_gpio.c ****     {
 1175              		.loc 1 643 5 is_stmt 1 view .LVU363
 643:Library/src/lcm32f06x_gpio.c ****     {
 1176              		.loc 1 643 14 is_stmt 0 view .LVU364
 1177 0030 2368     		ldr	r3, [r4]
 643:Library/src/lcm32f06x_gpio.c ****     {
 1178              		.loc 1 643 7 view .LVU365
 1179 0032 1D42     		tst	r5, r3
 1180 0034 0AD0     		beq	.L65
 643:Library/src/lcm32f06x_gpio.c ****     {
 1181              		.loc 1 643 47 discriminator 1 view .LVU366
 1182 0036 F023     		movs	r3, #240
 643:Library/src/lcm32f06x_gpio.c ****     {
 1183              		.loc 1 643 40 discriminator 1 view .LVU367
 1184 0038 626A     		ldr	r2, [r4, #36]
 643:Library/src/lcm32f06x_gpio.c ****     {
 1185              		.loc 1 643 47 discriminator 1 view .LVU368
 1186 003a 1B01     		lsls	r3, r3, #4
 643:Library/src/lcm32f06x_gpio.c ****     {
 1187              		.loc 1 643 30 discriminator 1 view .LVU369
 1188 003c 1A42     		tst	r2, r3
 1189 003e 05D1     		bne	.L65
 643:Library/src/lcm32f06x_gpio.c ****     {
 1190              		.loc 1 643 71 discriminator 2 view .LVU370
 1191 0040 204B     		ldr	r3, .L70+20
 1192 0042 1A88     		ldrh	r2, [r3]
 643:Library/src/lcm32f06x_gpio.c ****     {
 1193              		.loc 1 643 67 discriminator 2 view .LVU371
 1194 0044 FF23     		movs	r3, #255
 1195 0046 5B00     		lsls	r3, r3, #1
 1196 0048 9A42     		cmp	r2, r3
 1197 004a 0FD0     		beq	.L69
 1198              	.L65:
 656:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1199              		.loc 1 656 9 is_stmt 1 view .LVU372
 1200              	.LBB34:
 1201              	.LBI34:
 258:Core/cmsis_gcc.h **** {
 1202              		.loc 2 258 27 view .LVU373
 1203              	.LBB35:
 260:Core/cmsis_gcc.h **** }
 1204              		.loc 2 260 3 view .LVU374
 1205              		.syntax divided
 1206              	@ 260 "Core/cmsis_gcc.h" 1
 1207 004c BFF36F8F 		isb 0xF
ARM GAS  /tmp/ccTxDPsK.s 			page 57


 1208              	@ 0 "" 2
 1209              		.thumb
 1210              		.syntax unified
 1211              	.LBE35:
 1212              	.LBE34:
 656:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1213              		.loc 1 656 9 discriminator 1 view .LVU375
 1214              	.LBB36:
 1215              	.LBI36:
1204:Core/cmsis_gcc.h **** {
 1216              		.loc 2 1204 31 view .LVU376
 1217              	.LBB37:
1206:Core/cmsis_gcc.h **** 
 1218              		.loc 2 1206 3 view .LVU377
1208:Core/cmsis_gcc.h ****   return(result);
 1219              		.loc 2 1208 3 view .LVU378
 1220              		.syntax divided
 1221              	@ 1208 "Core/cmsis_gcc.h" 1
 1222 0050 EFF31083 		MRS r3, primask
 1223              	@ 0 "" 2
 1224              	.LVL95:
 1225              		.loc 2 1209 3 view .LVU379
 1226              		.loc 2 1209 3 is_stmt 0 view .LVU380
 1227              		.thumb
 1228              		.syntax unified
 1229              	.LBE37:
 1230              	.LBE36:
 656:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1231              		.loc 1 656 9 is_stmt 1 discriminator 2 view .LVU381
 1232              	.LBB38:
 1233              	.LBI38:
 960:Core/cmsis_gcc.h **** {
 1234              		.loc 2 960 27 view .LVU382
 1235              	.LBB39:
 962:Core/cmsis_gcc.h **** }
 1236              		.loc 2 962 3 view .LVU383
 1237              		.syntax divided
 1238              	@ 962 "Core/cmsis_gcc.h" 1
 1239 0054 72B6     		cpsid i
 1240              	@ 0 "" 2
 1241              		.thumb
 1242              		.syntax unified
 1243              	.LBE39:
 1244              	.LBE38:
 656:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1245              		.loc 1 656 9 discriminator 3 view .LVU384
 1246 0056 164B     		ldr	r3, .L70
 1247 0058 164A     		ldr	r2, .L70+4
 1248 005a 1A60     		str	r2, [r3]
 656:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1249              		.loc 1 656 26 discriminator 3 view .LVU385
 657:Library/src/lcm32f06x_gpio.c ****         __dekey(); 
 1250              		.loc 1 657 9 view .LVU386
 657:Library/src/lcm32f06x_gpio.c ****         __dekey(); 
 1251              		.loc 1 657 34 is_stmt 0 view .LVU387
 1252 005c 8023     		movs	r3, #128
 1253 005e 174A     		ldr	r2, .L70+12
ARM GAS  /tmp/ccTxDPsK.s 			page 58


 1254 0060 DB01     		lsls	r3, r3, #7
 1255 0062 916A     		ldr	r1, [r2, #40]
 1256 0064 0B43     		orrs	r3, r1
 1257 0066 9362     		str	r3, [r2, #40]
 658:Library/src/lcm32f06x_gpio.c ****     }
 1258              		.loc 1 658 9 is_stmt 1 view .LVU388
 1259              	.LBB40:
 1260              	.LBI40:
 949:Core/cmsis_gcc.h **** {
 1261              		.loc 2 949 27 view .LVU389
 1262              	.LBB41:
 951:Core/cmsis_gcc.h **** }
 1263              		.loc 2 951 3 view .LVU390
 1264              		.syntax divided
 1265              	@ 951 "Core/cmsis_gcc.h" 1
 1266 0068 62B6     		cpsie i
 1267              	@ 0 "" 2
 1268              		.thumb
 1269              		.syntax unified
 1270              	.LBE41:
 1271              	.LBE40:
 658:Library/src/lcm32f06x_gpio.c ****     }
 1272              		.loc 1 658 18 view .LVU391
 1273              		.loc 1 661 1 is_stmt 0 view .LVU392
 1274 006a DAE7     		b	.L62
 1275              	.L69:
 645:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR |= 1 << 2;
 1276              		.loc 1 645 9 is_stmt 1 view .LVU393
 645:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR |= 1 << 2;
 1277              		.loc 1 645 22 is_stmt 0 view .LVU394
 1278 006c 3022     		movs	r2, #48
 645:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR |= 1 << 2;
 1279              		.loc 1 645 14 view .LVU395
 1280 006e 2368     		ldr	r3, [r4]
 647:Library/src/lcm32f06x_gpio.c ****         chipctrl_access();
 1281              		.loc 1 647 9 view .LVU396
 1282 0070 0120     		movs	r0, #1
 645:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR |= 1 << 2;
 1283              		.loc 1 645 22 view .LVU397
 1284 0072 9343     		bics	r3, r2
 1285 0074 2360     		str	r3, [r4]
 646:Library/src/lcm32f06x_gpio.c ****         delay10us(1);
 1286              		.loc 1 646 9 is_stmt 1 view .LVU398
 646:Library/src/lcm32f06x_gpio.c ****         delay10us(1);
 1287              		.loc 1 646 14 is_stmt 0 view .LVU399
 1288 0076 E368     		ldr	r3, [r4, #12]
 646:Library/src/lcm32f06x_gpio.c ****         delay10us(1);
 1289              		.loc 1 646 24 view .LVU400
 1290 0078 2C3A     		subs	r2, r2, #44
 1291 007a 1343     		orrs	r3, r2
 1292 007c E360     		str	r3, [r4, #12]
 647:Library/src/lcm32f06x_gpio.c ****         chipctrl_access();
 1293              		.loc 1 647 9 is_stmt 1 view .LVU401
 1294 007e FFF7FEFF 		bl	delay10us
 1295              	.LVL96:
 648:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1296              		.loc 1 648 9 view .LVU402
ARM GAS  /tmp/ccTxDPsK.s 			page 59


 1297              	.LBB42:
 1298              	.LBI42:
 258:Core/cmsis_gcc.h **** {
 1299              		.loc 2 258 27 view .LVU403
 1300              	.LBB43:
 260:Core/cmsis_gcc.h **** }
 1301              		.loc 2 260 3 view .LVU404
 1302              		.syntax divided
 1303              	@ 260 "Core/cmsis_gcc.h" 1
 1304 0082 BFF36F8F 		isb 0xF
 1305              	@ 0 "" 2
 1306              		.thumb
 1307              		.syntax unified
 1308              	.LBE43:
 1309              	.LBE42:
 648:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1310              		.loc 1 648 9 discriminator 1 view .LVU405
 1311              	.LBB44:
 1312              	.LBI44:
1204:Core/cmsis_gcc.h **** {
 1313              		.loc 2 1204 31 view .LVU406
 1314              	.LBB45:
1206:Core/cmsis_gcc.h **** 
 1315              		.loc 2 1206 3 view .LVU407
1208:Core/cmsis_gcc.h ****   return(result);
 1316              		.loc 2 1208 3 view .LVU408
 1317              		.syntax divided
 1318              	@ 1208 "Core/cmsis_gcc.h" 1
 1319 0086 EFF31083 		MRS r3, primask
 1320              	@ 0 "" 2
 1321              	.LVL97:
 1322              		.loc 2 1209 3 view .LVU409
 1323              		.loc 2 1209 3 is_stmt 0 view .LVU410
 1324              		.thumb
 1325              		.syntax unified
 1326              	.LBE45:
 1327              	.LBE44:
 648:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1328              		.loc 1 648 9 is_stmt 1 discriminator 2 view .LVU411
 1329              	.LBB46:
 1330              	.LBI46:
 960:Core/cmsis_gcc.h **** {
 1331              		.loc 2 960 27 view .LVU412
 1332              	.LBB47:
 962:Core/cmsis_gcc.h **** }
 1333              		.loc 2 962 3 view .LVU413
 1334              		.syntax divided
 1335              	@ 962 "Core/cmsis_gcc.h" 1
 1336 008a 72B6     		cpsid i
 1337              	@ 0 "" 2
 1338              		.thumb
 1339              		.syntax unified
 1340              	.LBE47:
 1341              	.LBE46:
 648:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1342              		.loc 1 648 9 discriminator 3 view .LVU414
 1343 008c 084B     		ldr	r3, .L70
ARM GAS  /tmp/ccTxDPsK.s 			page 60


 1344 008e 094A     		ldr	r2, .L70+4
 1345 0090 1A60     		str	r2, [r3]
 648:Library/src/lcm32f06x_gpio.c ****         CHIPCTRL->BDCR_b.RST_CFG = 1; // PB2作为复位引脚 /PF2 serves as the reset pin
 1346              		.loc 1 648 26 discriminator 3 view .LVU415
 649:Library/src/lcm32f06x_gpio.c ****         __dekey();
 1347              		.loc 1 649 9 view .LVU416
 649:Library/src/lcm32f06x_gpio.c ****         __dekey();
 1348              		.loc 1 649 34 is_stmt 0 view .LVU417
 1349 0092 8023     		movs	r3, #128
 1350 0094 094A     		ldr	r2, .L70+12
 1351 0096 DB01     		lsls	r3, r3, #7
 1352 0098 916A     		ldr	r1, [r2, #40]
 1353 009a 0B43     		orrs	r3, r1
 1354 009c 9362     		str	r3, [r2, #40]
 650:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR = 1 << 18;
 1355              		.loc 1 650 9 is_stmt 1 view .LVU418
 1356              	.LBB48:
 1357              	.LBI48:
 949:Core/cmsis_gcc.h **** {
 1358              		.loc 2 949 27 view .LVU419
 1359              	.LBB49:
 951:Core/cmsis_gcc.h **** }
 1360              		.loc 2 951 3 view .LVU420
 1361              		.syntax divided
 1362              	@ 951 "Core/cmsis_gcc.h" 1
 1363 009e 62B6     		cpsie i
 1364              	@ 0 "" 2
 1365              		.thumb
 1366              		.syntax unified
 1367              	.LBE49:
 1368              	.LBE48:
 650:Library/src/lcm32f06x_gpio.c ****         GPIOB->PU_BSRR = 1 << 18;
 1369              		.loc 1 650 18 discriminator 1 view .LVU421
 651:Library/src/lcm32f06x_gpio.c ****         GPIOB->MODER |= 2 << 4;
 1370              		.loc 1 651 9 view .LVU422
 651:Library/src/lcm32f06x_gpio.c ****         GPIOB->MODER |= 2 << 4;
 1371              		.loc 1 651 24 is_stmt 0 view .LVU423
 1372 00a0 8023     		movs	r3, #128
 1373 00a2 DB02     		lsls	r3, r3, #11
 1374 00a4 E360     		str	r3, [r4, #12]
 652:Library/src/lcm32f06x_gpio.c ****     }
 1375              		.loc 1 652 9 is_stmt 1 view .LVU424
 652:Library/src/lcm32f06x_gpio.c ****     }
 1376              		.loc 1 652 14 is_stmt 0 view .LVU425
 1377 00a6 2368     		ldr	r3, [r4]
 652:Library/src/lcm32f06x_gpio.c ****     }
 1378              		.loc 1 652 22 view .LVU426
 1379 00a8 2B43     		orrs	r3, r5
 1380 00aa 2360     		str	r3, [r4]
 1381 00ac B9E7     		b	.L62
 1382              	.L71:
 1383 00ae C046     		.align	2
 1384              	.L70:
 1385 00b0 20700140 		.word	1073836064
 1386 00b4 65432187 		.word	-2027863195
 1387 00b8 FFBFFFFF 		.word	-16385
 1388 00bc 00700140 		.word	1073836032
ARM GAS  /tmp/ccTxDPsK.s 			page 61


 1389 00c0 00020048 		.word	1207960064
 1390 00c4 1CF7FF1F 		.word	536868636
 1391              		.cfi_endproc
 1392              	.LFE62:
 1394              		.text
 1395              	.Letext0:
 1396              		.file 3 "Library/inc/lcm32f06x.h"
 1397              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 1398              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 1399              		.file 6 "Library/inc/lcm32f06x_gpio.h"
 1400              		.file 7 "Library/inc/lcm32f06x_rcc.h"
ARM GAS  /tmp/ccTxDPsK.s 			page 62


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_gpio.c
     /tmp/ccTxDPsK.s:17     .text.GPIO_DeInit:00000000 $t
     /tmp/ccTxDPsK.s:24     .text.GPIO_DeInit:00000000 GPIO_DeInit
     /tmp/ccTxDPsK.s:89     .text.GPIO_DeInit:00000038 $d
     /tmp/ccTxDPsK.s:94     .text.GPIO_Init:00000000 $t
     /tmp/ccTxDPsK.s:101    .text.GPIO_Init:00000000 GPIO_Init
     /tmp/ccTxDPsK.s:359    .text.GPIO_StructInit:00000000 $t
     /tmp/ccTxDPsK.s:366    .text.GPIO_StructInit:00000000 GPIO_StructInit
     /tmp/ccTxDPsK.s:388    .text.GPIO_StructInit:00000008 $d
     /tmp/ccTxDPsK.s:393    .text.GPIO_PinLockConfig:00000000 $t
     /tmp/ccTxDPsK.s:400    .text.GPIO_PinLockConfig:00000000 GPIO_PinLockConfig
     /tmp/ccTxDPsK.s:475    .text.GPIO_ReadInputDataBit:00000000 $t
     /tmp/ccTxDPsK.s:482    .text.GPIO_ReadInputDataBit:00000000 GPIO_ReadInputDataBit
     /tmp/ccTxDPsK.s:514    .text.GPIO_ReadInputData:00000000 $t
     /tmp/ccTxDPsK.s:521    .text.GPIO_ReadInputData:00000000 GPIO_ReadInputData
     /tmp/ccTxDPsK.s:544    .text.GPIO_ReadOutputDataBit:00000000 $t
     /tmp/ccTxDPsK.s:551    .text.GPIO_ReadOutputDataBit:00000000 GPIO_ReadOutputDataBit
     /tmp/ccTxDPsK.s:583    .text.GPIO_ReadOutputData:00000000 $t
     /tmp/ccTxDPsK.s:590    .text.GPIO_ReadOutputData:00000000 GPIO_ReadOutputData
     /tmp/ccTxDPsK.s:613    .text.GPIO_SetBits:00000000 $t
     /tmp/ccTxDPsK.s:620    .text.GPIO_SetBits:00000000 GPIO_SetBits
     /tmp/ccTxDPsK.s:640    .text.GPIO_ResetBits:00000000 $t
     /tmp/ccTxDPsK.s:647    .text.GPIO_ResetBits:00000000 GPIO_ResetBits
     /tmp/ccTxDPsK.s:670    .text.GPIO_WriteBit:00000000 $t
     /tmp/ccTxDPsK.s:677    .text.GPIO_WriteBit:00000000 GPIO_WriteBit
     /tmp/ccTxDPsK.s:706    .text.GPIO_Write:00000000 $t
     /tmp/ccTxDPsK.s:713    .text.GPIO_Write:00000000 GPIO_Write
     /tmp/ccTxDPsK.s:732    .text.GPIO_PinAFConfig:00000000 $t
     /tmp/ccTxDPsK.s:739    .text.GPIO_PinAFConfig:00000000 GPIO_PinAFConfig
     /tmp/ccTxDPsK.s:828    .text.GPIO_DriveConfig:00000000 $t
     /tmp/ccTxDPsK.s:835    .text.GPIO_DriveConfig:00000000 GPIO_DriveConfig
     /tmp/ccTxDPsK.s:885    .text.GPIO_BitToggle:00000000 $t
     /tmp/ccTxDPsK.s:892    .text.GPIO_BitToggle:00000000 GPIO_BitToggle
     /tmp/ccTxDPsK.s:912    .text.GPIO_InputCMOSCmd:00000000 $t
     /tmp/ccTxDPsK.s:919    .text.GPIO_InputCMOSCmd:00000000 GPIO_InputCMOSCmd
     /tmp/ccTxDPsK.s:947    .text.GPIO_AnaModeSet:00000000 $t
     /tmp/ccTxDPsK.s:954    .text.GPIO_AnaModeSet:00000000 GPIO_AnaModeSet
     /tmp/ccTxDPsK.s:1054   .text.GPIO_ResetPB2Config:00000000 $t
     /tmp/ccTxDPsK.s:1061   .text.GPIO_ResetPB2Config:00000000 GPIO_ResetPB2Config
     /tmp/ccTxDPsK.s:1385   .text.GPIO_ResetPB2Config:000000b0 $d

UNDEFINED SYMBOLS
RCC_AHBPeriphResetCmd
RCC_AHBPeriphClockCmd
delay10us
