ARM GAS  /tmp/cc3WhKxr.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_it.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Hardware/lcm32f06x_it.c"
  16              		.section	.text.NMI_Handler,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	NMI_Handler
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	NMI_Handler:
  25              	.LFB45:
   1:Hardware/lcm32f06x_it.c **** /**
   2:Hardware/lcm32f06x_it.c ****  ******************************************************************************
   3:Hardware/lcm32f06x_it.c ****  * @file    lcm32f06x_it.c
   4:Hardware/lcm32f06x_it.c ****  * @author  System R&D Team
   5:Hardware/lcm32f06x_it.c ****  * @version V2.0.2
   6:Hardware/lcm32f06x_it.c ****  * @date    10-April-2025
   7:Hardware/lcm32f06x_it.c ****  * @brief   Main Interrupt Service Routines.
   8:Hardware/lcm32f06x_it.c ****  *          This file provides template for all exceptions handler and
   9:Hardware/lcm32f06x_it.c ****  *          peripherals interrupt service routine.
  10:Hardware/lcm32f06x_it.c ****  ******************************************************************************
  11:Hardware/lcm32f06x_it.c ****  * @attention
  12:Hardware/lcm32f06x_it.c ****  *
  13:Hardware/lcm32f06x_it.c ****  * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  14:Hardware/lcm32f06x_it.c ****  * All rights reserved.
  15:Hardware/lcm32f06x_it.c ****  *
  16:Hardware/lcm32f06x_it.c ****  * This software is licensed under terms that can be found in the LICENSE file
  17:Hardware/lcm32f06x_it.c ****  * in the root directory of this software component.
  18:Hardware/lcm32f06x_it.c ****  * If no LICENSE file comes with this software, it is provided AS-IS.
  19:Hardware/lcm32f06x_it.c ****  *
  20:Hardware/lcm32f06x_it.c ****  ******************************************************************************
  21:Hardware/lcm32f06x_it.c ****  */
  22:Hardware/lcm32f06x_it.c **** 
  23:Hardware/lcm32f06x_it.c **** /* Includes ------------------------------------------------------------------*/
  24:Hardware/lcm32f06x_it.c **** #include "global.h"
  25:Hardware/lcm32f06x_it.c **** #include "lcm32f06x_it.h"
  26:Hardware/lcm32f06x_it.c **** /* Private typedef -----------------------------------------------------------*/
  27:Hardware/lcm32f06x_it.c **** /* Private define ------------------------------------------------------------*/
  28:Hardware/lcm32f06x_it.c **** /* Private macro -------------------------------------------------------------*/
  29:Hardware/lcm32f06x_it.c **** /* Private variables ---------------------------------------------------------*/
  30:Hardware/lcm32f06x_it.c **** /* Private function prototypes -----------------------------------------------*/
  31:Hardware/lcm32f06x_it.c **** /* Private functions ---------------------------------------------------------*/
  32:Hardware/lcm32f06x_it.c **** 
  33:Hardware/lcm32f06x_it.c **** /******************************************************************************/
ARM GAS  /tmp/cc3WhKxr.s 			page 2


  34:Hardware/lcm32f06x_it.c **** /*            Cortex-M0 Processor Exceptions Handlers                         */
  35:Hardware/lcm32f06x_it.c **** /******************************************************************************/
  36:Hardware/lcm32f06x_it.c **** 
  37:Hardware/lcm32f06x_it.c **** /**
  38:Hardware/lcm32f06x_it.c ****  * @name   NMI_Handler
  39:Hardware/lcm32f06x_it.c ****  * @brief  EN: This function handles NMI exception.
  40:Hardware/lcm32f06x_it.c ****  *         CN: 此函数用于处理NMI异常。
  41:Hardware/lcm32f06x_it.c ****  * @param  None
  42:Hardware/lcm32f06x_it.c ****  * @retval None
  43:Hardware/lcm32f06x_it.c ****  */
  44:Hardware/lcm32f06x_it.c **** void NMI_Handler(void)
  45:Hardware/lcm32f06x_it.c **** {
  26              		.loc 1 45 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 0
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  30              		@ link register save eliminated.
  46:Hardware/lcm32f06x_it.c **** }
  31              		.loc 1 46 1 view .LVU1
  32              		@ sp needed
  33 0000 7047     		bx	lr
  34              		.cfi_endproc
  35              	.LFE45:
  37 0002 C046     		.section	.text.HardFault_Handler,"ax",%progbits
  38              		.align	1
  39              		.p2align 2,,3
  40              		.global	HardFault_Handler
  41              		.syntax unified
  42              		.code	16
  43              		.thumb_func
  45              	HardFault_Handler:
  46              	.LFB46:
  47:Hardware/lcm32f06x_it.c **** 
  48:Hardware/lcm32f06x_it.c **** /**
  49:Hardware/lcm32f06x_it.c ****  * @name   HardFault_Handler
  50:Hardware/lcm32f06x_it.c ****  * @brief  EN: This function handles Hard Fault exception.
  51:Hardware/lcm32f06x_it.c ****  *         CN: 此函数用于处理硬件错误异常。
  52:Hardware/lcm32f06x_it.c ****  * @param  None
  53:Hardware/lcm32f06x_it.c ****  * @retval None
  54:Hardware/lcm32f06x_it.c ****  */
  55:Hardware/lcm32f06x_it.c **** void HardFault_Handler(void)
  56:Hardware/lcm32f06x_it.c **** {
  47              		.loc 1 56 1 view -0
  48              		.cfi_startproc
  49              		@ Volatile: function does not return.
  50              		@ args = 0, pretend = 0, frame = 0
  51              		@ frame_needed = 0, uses_anonymous_args = 0
  57:Hardware/lcm32f06x_it.c ****   delay10us(3);
  52              		.loc 1 57 3 view .LVU3
  53 0000 0320     		movs	r0, #3
  56:Hardware/lcm32f06x_it.c ****   delay10us(3);
  54              		.loc 1 56 1 is_stmt 0 view .LVU4
  55 0002 10B5     		push	{r4, lr}
  56              	.LCFI0:
  57              		.cfi_def_cfa_offset 8
  58              		.cfi_offset 4, -8
  59              		.cfi_offset 14, -4
ARM GAS  /tmp/cc3WhKxr.s 			page 3


  60              		.loc 1 57 3 view .LVU5
  61 0004 FFF7FEFF 		bl	delay10us
  62              	.LVL0:
  58:Hardware/lcm32f06x_it.c ****   NVIC_SystemReset();
  63              		.loc 1 58 3 is_stmt 1 view .LVU6
  64              	.LBB12:
  65              	.LBI12:
  66              		.file 2 "Core/core_cm0.h"
   1:Core/core_cm0.h **** /**************************************************************************//**
   2:Core/core_cm0.h ****  * @file     core_cm0.h
   3:Core/core_cm0.h ****  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
   4:Core/core_cm0.h ****  * @version  V5.0.8
   5:Core/core_cm0.h ****  * @date     21. August 2019
   6:Core/core_cm0.h ****  ******************************************************************************/
   7:Core/core_cm0.h **** /*
   8:Core/core_cm0.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Core/core_cm0.h ****  *
  10:Core/core_cm0.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/core_cm0.h ****  *
  12:Core/core_cm0.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/core_cm0.h ****  * not use this file except in compliance with the License.
  14:Core/core_cm0.h ****  * You may obtain a copy of the License at
  15:Core/core_cm0.h ****  *
  16:Core/core_cm0.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/core_cm0.h ****  *
  18:Core/core_cm0.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/core_cm0.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/core_cm0.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/core_cm0.h ****  * See the License for the specific language governing permissions and
  22:Core/core_cm0.h ****  * limitations under the License.
  23:Core/core_cm0.h ****  */
  24:Core/core_cm0.h **** 
  25:Core/core_cm0.h **** #if   defined ( __ICCARM__ )
  26:Core/core_cm0.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Core/core_cm0.h **** #elif defined (__clang__)
  28:Core/core_cm0.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Core/core_cm0.h **** #endif
  30:Core/core_cm0.h **** 
  31:Core/core_cm0.h **** #ifndef __CORE_CM0_H_GENERIC
  32:Core/core_cm0.h **** #define __CORE_CM0_H_GENERIC
  33:Core/core_cm0.h **** 
  34:Core/core_cm0.h **** #include <stdint.h>
  35:Core/core_cm0.h **** 
  36:Core/core_cm0.h **** #ifdef __cplusplus
  37:Core/core_cm0.h ****  extern "C" {
  38:Core/core_cm0.h **** #endif
  39:Core/core_cm0.h **** 
  40:Core/core_cm0.h **** /**
  41:Core/core_cm0.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Core/core_cm0.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Core/core_cm0.h **** 
  44:Core/core_cm0.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  45:Core/core_cm0.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Core/core_cm0.h **** 
  47:Core/core_cm0.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Core/core_cm0.h ****      Unions are used for effective representation of core registers.
  49:Core/core_cm0.h **** 
ARM GAS  /tmp/cc3WhKxr.s 			page 4


  50:Core/core_cm0.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Core/core_cm0.h ****      Function-like macros are used to allow more efficient code.
  52:Core/core_cm0.h ****  */
  53:Core/core_cm0.h **** 
  54:Core/core_cm0.h **** 
  55:Core/core_cm0.h **** /*******************************************************************************
  56:Core/core_cm0.h ****  *                 CMSIS definitions
  57:Core/core_cm0.h ****  ******************************************************************************/
  58:Core/core_cm0.h **** /**
  59:Core/core_cm0.h ****   \ingroup Cortex_M0
  60:Core/core_cm0.h ****   @{
  61:Core/core_cm0.h ****  */
  62:Core/core_cm0.h **** 
  63:Core/core_cm0.h **** #include "cmsis_version.h"
  64:Core/core_cm0.h ****  
  65:Core/core_cm0.h **** /*  CMSIS CM0 definitions */
  66:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
  67:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
  68:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
  69:Core/core_cm0.h ****                                     __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
  70:Core/core_cm0.h **** 
  71:Core/core_cm0.h **** #define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
  72:Core/core_cm0.h **** 
  73:Core/core_cm0.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Core/core_cm0.h ****     This core does not support an FPU at all
  75:Core/core_cm0.h **** */
  76:Core/core_cm0.h **** #define __FPU_USED       0U
  77:Core/core_cm0.h **** 
  78:Core/core_cm0.h **** #if defined ( __CC_ARM )
  79:Core/core_cm0.h ****   #if defined __TARGET_FPU_VFP
  80:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  81:Core/core_cm0.h ****   #endif
  82:Core/core_cm0.h **** 
  83:Core/core_cm0.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  84:Core/core_cm0.h ****   #if defined __ARM_FP
  85:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86:Core/core_cm0.h ****   #endif
  87:Core/core_cm0.h **** 
  88:Core/core_cm0.h **** #elif defined ( __GNUC__ )
  89:Core/core_cm0.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  90:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  91:Core/core_cm0.h ****   #endif
  92:Core/core_cm0.h **** 
  93:Core/core_cm0.h **** #elif defined ( __ICCARM__ )
  94:Core/core_cm0.h ****   #if defined __ARMVFP__
  95:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  96:Core/core_cm0.h ****   #endif
  97:Core/core_cm0.h **** 
  98:Core/core_cm0.h **** #elif defined ( __TI_ARM__ )
  99:Core/core_cm0.h ****   #if defined __TI_VFP_SUPPORT__
 100:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 101:Core/core_cm0.h ****   #endif
 102:Core/core_cm0.h **** 
 103:Core/core_cm0.h **** #elif defined ( __TASKING__ )
 104:Core/core_cm0.h ****   #if defined __FPU_VFP__
 105:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 106:Core/core_cm0.h ****   #endif
ARM GAS  /tmp/cc3WhKxr.s 			page 5


 107:Core/core_cm0.h **** 
 108:Core/core_cm0.h **** #elif defined ( __CSMC__ )
 109:Core/core_cm0.h ****   #if ( __CSMC__ & 0x400U)
 110:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 111:Core/core_cm0.h ****   #endif
 112:Core/core_cm0.h **** 
 113:Core/core_cm0.h **** #endif
 114:Core/core_cm0.h **** 
 115:Core/core_cm0.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 116:Core/core_cm0.h **** 
 117:Core/core_cm0.h **** 
 118:Core/core_cm0.h **** #ifdef __cplusplus
 119:Core/core_cm0.h **** }
 120:Core/core_cm0.h **** #endif
 121:Core/core_cm0.h **** 
 122:Core/core_cm0.h **** #endif /* __CORE_CM0_H_GENERIC */
 123:Core/core_cm0.h **** 
 124:Core/core_cm0.h **** #ifndef __CMSIS_GENERIC
 125:Core/core_cm0.h **** 
 126:Core/core_cm0.h **** #ifndef __CORE_CM0_H_DEPENDANT
 127:Core/core_cm0.h **** #define __CORE_CM0_H_DEPENDANT
 128:Core/core_cm0.h **** 
 129:Core/core_cm0.h **** #ifdef __cplusplus
 130:Core/core_cm0.h ****  extern "C" {
 131:Core/core_cm0.h **** #endif
 132:Core/core_cm0.h **** 
 133:Core/core_cm0.h **** /* check device defines and use defaults */
 134:Core/core_cm0.h **** #if defined __CHECK_DEVICE_DEFINES
 135:Core/core_cm0.h ****   #ifndef __CM0_REV
 136:Core/core_cm0.h ****     #define __CM0_REV               0x0000U
 137:Core/core_cm0.h ****     #warning "__CM0_REV not defined in device header file; using default!"
 138:Core/core_cm0.h ****   #endif
 139:Core/core_cm0.h **** 
 140:Core/core_cm0.h ****   #ifndef __NVIC_PRIO_BITS
 141:Core/core_cm0.h ****     #define __NVIC_PRIO_BITS          2U
 142:Core/core_cm0.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 143:Core/core_cm0.h ****   #endif
 144:Core/core_cm0.h **** 
 145:Core/core_cm0.h ****   #ifndef __Vendor_SysTickConfig
 146:Core/core_cm0.h ****     #define __Vendor_SysTickConfig    0U
 147:Core/core_cm0.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 148:Core/core_cm0.h ****   #endif
 149:Core/core_cm0.h **** #endif
 150:Core/core_cm0.h **** 
 151:Core/core_cm0.h **** /* IO definitions (access restrictions to peripheral registers) */
 152:Core/core_cm0.h **** /**
 153:Core/core_cm0.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 154:Core/core_cm0.h **** 
 155:Core/core_cm0.h ****     <strong>IO Type Qualifiers</strong> are used
 156:Core/core_cm0.h ****     \li to specify the access to peripheral variables.
 157:Core/core_cm0.h ****     \li for automatic generation of peripheral register debug information.
 158:Core/core_cm0.h **** */
 159:Core/core_cm0.h **** #ifdef __cplusplus
 160:Core/core_cm0.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 161:Core/core_cm0.h **** #else
 162:Core/core_cm0.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 163:Core/core_cm0.h **** #endif
ARM GAS  /tmp/cc3WhKxr.s 			page 6


 164:Core/core_cm0.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 165:Core/core_cm0.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 166:Core/core_cm0.h **** 
 167:Core/core_cm0.h **** /* following defines should be used for structure members */
 168:Core/core_cm0.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 169:Core/core_cm0.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 170:Core/core_cm0.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 171:Core/core_cm0.h **** 
 172:Core/core_cm0.h **** /*@} end of group Cortex_M0 */
 173:Core/core_cm0.h **** 
 174:Core/core_cm0.h **** 
 175:Core/core_cm0.h **** 
 176:Core/core_cm0.h **** /*******************************************************************************
 177:Core/core_cm0.h ****  *                 Register Abstraction
 178:Core/core_cm0.h ****   Core Register contain:
 179:Core/core_cm0.h ****   - Core Register
 180:Core/core_cm0.h ****   - Core NVIC Register
 181:Core/core_cm0.h ****   - Core SCB Register
 182:Core/core_cm0.h ****   - Core SysTick Register
 183:Core/core_cm0.h ****  ******************************************************************************/
 184:Core/core_cm0.h **** /**
 185:Core/core_cm0.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 186:Core/core_cm0.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 187:Core/core_cm0.h **** */
 188:Core/core_cm0.h **** 
 189:Core/core_cm0.h **** /**
 190:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 191:Core/core_cm0.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 192:Core/core_cm0.h ****   \brief      Core Register type definitions.
 193:Core/core_cm0.h ****   @{
 194:Core/core_cm0.h ****  */
 195:Core/core_cm0.h **** 
 196:Core/core_cm0.h **** /**
 197:Core/core_cm0.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 198:Core/core_cm0.h ****  */
 199:Core/core_cm0.h **** typedef union
 200:Core/core_cm0.h **** {
 201:Core/core_cm0.h ****   struct
 202:Core/core_cm0.h ****   {
 203:Core/core_cm0.h ****     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
 204:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 205:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 206:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 207:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 208:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 209:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 210:Core/core_cm0.h **** } APSR_Type;
 211:Core/core_cm0.h **** 
 212:Core/core_cm0.h **** /* APSR Register Definitions */
 213:Core/core_cm0.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 214:Core/core_cm0.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 215:Core/core_cm0.h **** 
 216:Core/core_cm0.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 217:Core/core_cm0.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 218:Core/core_cm0.h **** 
 219:Core/core_cm0.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 220:Core/core_cm0.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
ARM GAS  /tmp/cc3WhKxr.s 			page 7


 221:Core/core_cm0.h **** 
 222:Core/core_cm0.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 223:Core/core_cm0.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 224:Core/core_cm0.h **** 
 225:Core/core_cm0.h **** 
 226:Core/core_cm0.h **** /**
 227:Core/core_cm0.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 228:Core/core_cm0.h ****  */
 229:Core/core_cm0.h **** typedef union
 230:Core/core_cm0.h **** {
 231:Core/core_cm0.h ****   struct
 232:Core/core_cm0.h ****   {
 233:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 234:Core/core_cm0.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 235:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 236:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 237:Core/core_cm0.h **** } IPSR_Type;
 238:Core/core_cm0.h **** 
 239:Core/core_cm0.h **** /* IPSR Register Definitions */
 240:Core/core_cm0.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 241:Core/core_cm0.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 242:Core/core_cm0.h **** 
 243:Core/core_cm0.h **** 
 244:Core/core_cm0.h **** /**
 245:Core/core_cm0.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 246:Core/core_cm0.h ****  */
 247:Core/core_cm0.h **** typedef union
 248:Core/core_cm0.h **** {
 249:Core/core_cm0.h ****   struct
 250:Core/core_cm0.h ****   {
 251:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 252:Core/core_cm0.h ****     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
 253:Core/core_cm0.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 254:Core/core_cm0.h ****     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
 255:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 256:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 257:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 258:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 259:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 260:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 261:Core/core_cm0.h **** } xPSR_Type;
 262:Core/core_cm0.h **** 
 263:Core/core_cm0.h **** /* xPSR Register Definitions */
 264:Core/core_cm0.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 265:Core/core_cm0.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 266:Core/core_cm0.h **** 
 267:Core/core_cm0.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 268:Core/core_cm0.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 269:Core/core_cm0.h **** 
 270:Core/core_cm0.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 271:Core/core_cm0.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 272:Core/core_cm0.h **** 
 273:Core/core_cm0.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 274:Core/core_cm0.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 275:Core/core_cm0.h **** 
 276:Core/core_cm0.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 277:Core/core_cm0.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
ARM GAS  /tmp/cc3WhKxr.s 			page 8


 278:Core/core_cm0.h **** 
 279:Core/core_cm0.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 280:Core/core_cm0.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 281:Core/core_cm0.h **** 
 282:Core/core_cm0.h **** 
 283:Core/core_cm0.h **** /**
 284:Core/core_cm0.h ****   \brief  Union type to access the Control Registers (CONTROL).
 285:Core/core_cm0.h ****  */
 286:Core/core_cm0.h **** typedef union
 287:Core/core_cm0.h **** {
 288:Core/core_cm0.h ****   struct
 289:Core/core_cm0.h ****   {
 290:Core/core_cm0.h ****     uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
 291:Core/core_cm0.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 292:Core/core_cm0.h ****     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 293:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 294:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 295:Core/core_cm0.h **** } CONTROL_Type;
 296:Core/core_cm0.h **** 
 297:Core/core_cm0.h **** /* CONTROL Register Definitions */
 298:Core/core_cm0.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 299:Core/core_cm0.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 300:Core/core_cm0.h **** 
 301:Core/core_cm0.h **** /*@} end of group CMSIS_CORE */
 302:Core/core_cm0.h **** 
 303:Core/core_cm0.h **** 
 304:Core/core_cm0.h **** /**
 305:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 306:Core/core_cm0.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 307:Core/core_cm0.h ****   \brief      Type definitions for the NVIC Registers
 308:Core/core_cm0.h ****   @{
 309:Core/core_cm0.h ****  */
 310:Core/core_cm0.h **** 
 311:Core/core_cm0.h **** /**
 312:Core/core_cm0.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 313:Core/core_cm0.h ****  */
 314:Core/core_cm0.h **** typedef struct
 315:Core/core_cm0.h **** {
 316:Core/core_cm0.h ****   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 317:Core/core_cm0.h ****         uint32_t RESERVED0[31U];
 318:Core/core_cm0.h ****   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 319:Core/core_cm0.h ****         uint32_t RESERVED1[31U];
 320:Core/core_cm0.h ****   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 321:Core/core_cm0.h ****         uint32_t RESERVED2[31U];
 322:Core/core_cm0.h ****   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 323:Core/core_cm0.h ****         uint32_t RESERVED3[31U];
 324:Core/core_cm0.h ****         uint32_t RESERVED4[64U];
 325:Core/core_cm0.h ****   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 326:Core/core_cm0.h **** }  NVIC_Type;
 327:Core/core_cm0.h **** 
 328:Core/core_cm0.h **** /*@} end of group CMSIS_NVIC */
 329:Core/core_cm0.h **** 
 330:Core/core_cm0.h **** 
 331:Core/core_cm0.h **** /**
 332:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 333:Core/core_cm0.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 334:Core/core_cm0.h ****   \brief    Type definitions for the System Control Block Registers
ARM GAS  /tmp/cc3WhKxr.s 			page 9


 335:Core/core_cm0.h ****   @{
 336:Core/core_cm0.h ****  */
 337:Core/core_cm0.h **** 
 338:Core/core_cm0.h **** /**
 339:Core/core_cm0.h ****   \brief  Structure type to access the System Control Block (SCB).
 340:Core/core_cm0.h ****  */
 341:Core/core_cm0.h **** typedef struct
 342:Core/core_cm0.h **** {
 343:Core/core_cm0.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 344:Core/core_cm0.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 345:Core/core_cm0.h ****         uint32_t RESERVED0;
 346:Core/core_cm0.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 347:Core/core_cm0.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 348:Core/core_cm0.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 349:Core/core_cm0.h ****         uint32_t RESERVED1;
 350:Core/core_cm0.h ****   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registe
 351:Core/core_cm0.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 352:Core/core_cm0.h **** } SCB_Type;
 353:Core/core_cm0.h **** 
 354:Core/core_cm0.h **** /* SCB CPUID Register Definitions */
 355:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 356:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 357:Core/core_cm0.h **** 
 358:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 359:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 360:Core/core_cm0.h **** 
 361:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 362:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 363:Core/core_cm0.h **** 
 364:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 365:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 366:Core/core_cm0.h **** 
 367:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 368:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 369:Core/core_cm0.h **** 
 370:Core/core_cm0.h **** /* SCB Interrupt Control State Register Definitions */
 371:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 372:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 373:Core/core_cm0.h **** 
 374:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 375:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 376:Core/core_cm0.h **** 
 377:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 378:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 379:Core/core_cm0.h **** 
 380:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 381:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 382:Core/core_cm0.h **** 
 383:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 384:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 385:Core/core_cm0.h **** 
 386:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 387:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 388:Core/core_cm0.h **** 
 389:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 390:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 391:Core/core_cm0.h **** 
ARM GAS  /tmp/cc3WhKxr.s 			page 10


 392:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 393:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 394:Core/core_cm0.h **** 
 395:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 396:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 397:Core/core_cm0.h **** 
 398:Core/core_cm0.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 399:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 400:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 401:Core/core_cm0.h **** 
 402:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 403:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 404:Core/core_cm0.h **** 
 405:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 406:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 407:Core/core_cm0.h **** 
 408:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 409:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 410:Core/core_cm0.h **** 
 411:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 412:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 413:Core/core_cm0.h **** 
 414:Core/core_cm0.h **** /* SCB System Control Register Definitions */
 415:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 416:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 417:Core/core_cm0.h **** 
 418:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 419:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 420:Core/core_cm0.h **** 
 421:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 422:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 423:Core/core_cm0.h **** 
 424:Core/core_cm0.h **** /* SCB Configuration Control Register Definitions */
 425:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 426:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 427:Core/core_cm0.h **** 
 428:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 429:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 430:Core/core_cm0.h **** 
 431:Core/core_cm0.h **** /* SCB System Handler Control and State Register Definitions */
 432:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 433:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 434:Core/core_cm0.h **** 
 435:Core/core_cm0.h **** /*@} end of group CMSIS_SCB */
 436:Core/core_cm0.h **** 
 437:Core/core_cm0.h **** 
 438:Core/core_cm0.h **** /**
 439:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 440:Core/core_cm0.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 441:Core/core_cm0.h ****   \brief    Type definitions for the System Timer Registers.
 442:Core/core_cm0.h ****   @{
 443:Core/core_cm0.h ****  */
 444:Core/core_cm0.h **** 
 445:Core/core_cm0.h **** /**
 446:Core/core_cm0.h ****   \brief  Structure type to access the System Timer (SysTick).
 447:Core/core_cm0.h ****  */
 448:Core/core_cm0.h **** typedef struct
ARM GAS  /tmp/cc3WhKxr.s 			page 11


 449:Core/core_cm0.h **** {
 450:Core/core_cm0.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 451:Core/core_cm0.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 452:Core/core_cm0.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 453:Core/core_cm0.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 454:Core/core_cm0.h **** } SysTick_Type;
 455:Core/core_cm0.h **** 
 456:Core/core_cm0.h **** /* SysTick Control / Status Register Definitions */
 457:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 458:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 459:Core/core_cm0.h **** 
 460:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 461:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 462:Core/core_cm0.h **** 
 463:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 464:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 465:Core/core_cm0.h **** 
 466:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 467:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 468:Core/core_cm0.h **** 
 469:Core/core_cm0.h **** /* SysTick Reload Register Definitions */
 470:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 471:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 472:Core/core_cm0.h **** 
 473:Core/core_cm0.h **** /* SysTick Current Register Definitions */
 474:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 475:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 476:Core/core_cm0.h **** 
 477:Core/core_cm0.h **** /* SysTick Calibration Register Definitions */
 478:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 479:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 480:Core/core_cm0.h **** 
 481:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 482:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 483:Core/core_cm0.h **** 
 484:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 485:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 486:Core/core_cm0.h **** 
 487:Core/core_cm0.h **** /*@} end of group CMSIS_SysTick */
 488:Core/core_cm0.h **** 
 489:Core/core_cm0.h **** 
 490:Core/core_cm0.h **** /**
 491:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 492:Core/core_cm0.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
 493:Core/core_cm0.h ****   \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ove
 494:Core/core_cm0.h ****             Therefore they are not covered by the Cortex-M0 header file.
 495:Core/core_cm0.h ****   @{
 496:Core/core_cm0.h ****  */
 497:Core/core_cm0.h **** /*@} end of group CMSIS_CoreDebug */
 498:Core/core_cm0.h **** 
 499:Core/core_cm0.h **** 
 500:Core/core_cm0.h **** /**
 501:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 502:Core/core_cm0.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
 503:Core/core_cm0.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 504:Core/core_cm0.h ****   @{
 505:Core/core_cm0.h ****  */
ARM GAS  /tmp/cc3WhKxr.s 			page 12


 506:Core/core_cm0.h **** 
 507:Core/core_cm0.h **** /**
 508:Core/core_cm0.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
 509:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 510:Core/core_cm0.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
 511:Core/core_cm0.h ****   \return           Masked and shifted value.
 512:Core/core_cm0.h **** */
 513:Core/core_cm0.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 514:Core/core_cm0.h **** 
 515:Core/core_cm0.h **** /**
 516:Core/core_cm0.h ****   \brief     Mask and shift a register value to extract a bit filed value.
 517:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 518:Core/core_cm0.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
 519:Core/core_cm0.h ****   \return           Masked and shifted bit field value.
 520:Core/core_cm0.h **** */
 521:Core/core_cm0.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 522:Core/core_cm0.h **** 
 523:Core/core_cm0.h **** /*@} end of group CMSIS_core_bitfield */
 524:Core/core_cm0.h **** 
 525:Core/core_cm0.h **** 
 526:Core/core_cm0.h **** /**
 527:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 528:Core/core_cm0.h ****   \defgroup   CMSIS_core_base     Core Definitions
 529:Core/core_cm0.h ****   \brief      Definitions for base addresses, unions, and structures.
 530:Core/core_cm0.h ****   @{
 531:Core/core_cm0.h ****  */
 532:Core/core_cm0.h **** 
 533:Core/core_cm0.h **** /* Memory mapping of Core Hardware */
 534:Core/core_cm0.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
 535:Core/core_cm0.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 536:Core/core_cm0.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 537:Core/core_cm0.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
 538:Core/core_cm0.h **** 
 539:Core/core_cm0.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
 540:Core/core_cm0.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
 541:Core/core_cm0.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
 542:Core/core_cm0.h **** 
 543:Core/core_cm0.h **** 
 544:Core/core_cm0.h **** /*@} */
 545:Core/core_cm0.h **** 
 546:Core/core_cm0.h **** 
 547:Core/core_cm0.h **** 
 548:Core/core_cm0.h **** /*******************************************************************************
 549:Core/core_cm0.h ****  *                Hardware Abstraction Layer
 550:Core/core_cm0.h ****   Core Function Interface contains:
 551:Core/core_cm0.h ****   - Core NVIC Functions
 552:Core/core_cm0.h ****   - Core SysTick Functions
 553:Core/core_cm0.h ****   - Core Register Access Functions
 554:Core/core_cm0.h ****  ******************************************************************************/
 555:Core/core_cm0.h **** /**
 556:Core/core_cm0.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 557:Core/core_cm0.h **** */
 558:Core/core_cm0.h **** 
 559:Core/core_cm0.h **** 
 560:Core/core_cm0.h **** 
 561:Core/core_cm0.h **** /* ##########################   NVIC functions  #################################### */
 562:Core/core_cm0.h **** /**
ARM GAS  /tmp/cc3WhKxr.s 			page 13


 563:Core/core_cm0.h ****   \ingroup  CMSIS_Core_FunctionInterface
 564:Core/core_cm0.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
 565:Core/core_cm0.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
 566:Core/core_cm0.h ****   @{
 567:Core/core_cm0.h ****  */
 568:Core/core_cm0.h **** 
 569:Core/core_cm0.h **** #ifdef CMSIS_NVIC_VIRTUAL
 570:Core/core_cm0.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
 571:Core/core_cm0.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
 572:Core/core_cm0.h ****   #endif
 573:Core/core_cm0.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 574:Core/core_cm0.h **** #else
 575:Core/core_cm0.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
 576:Core/core_cm0.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
 577:Core/core_cm0.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
 578:Core/core_cm0.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
 579:Core/core_cm0.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
 580:Core/core_cm0.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
 581:Core/core_cm0.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
 582:Core/core_cm0.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 583:Core/core_cm0.h **** /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
 584:Core/core_cm0.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
 585:Core/core_cm0.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
 586:Core/core_cm0.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
 587:Core/core_cm0.h **** #endif /* CMSIS_NVIC_VIRTUAL */
 588:Core/core_cm0.h **** 
 589:Core/core_cm0.h **** #ifdef CMSIS_VECTAB_VIRTUAL
 590:Core/core_cm0.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 591:Core/core_cm0.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
 592:Core/core_cm0.h ****   #endif
 593:Core/core_cm0.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 594:Core/core_cm0.h **** #else
 595:Core/core_cm0.h ****   #define NVIC_SetVector              __NVIC_SetVector
 596:Core/core_cm0.h ****   #define NVIC_GetVector              __NVIC_GetVector
 597:Core/core_cm0.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 598:Core/core_cm0.h **** 
 599:Core/core_cm0.h **** #define NVIC_USER_IRQ_OFFSET          16
 600:Core/core_cm0.h **** 
 601:Core/core_cm0.h **** 
 602:Core/core_cm0.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
 603:Core/core_cm0.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
 604:Core/core_cm0.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
 605:Core/core_cm0.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
 606:Core/core_cm0.h **** 
 607:Core/core_cm0.h **** 
 608:Core/core_cm0.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 609:Core/core_cm0.h **** /* The following MACROS handle generation of the register offset and byte masks */
 610:Core/core_cm0.h **** #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 611:Core/core_cm0.h **** #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 612:Core/core_cm0.h **** #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 613:Core/core_cm0.h **** 
 614:Core/core_cm0.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X)
 615:Core/core_cm0.h **** #define __NVIC_GetPriorityGrouping()  (0U)
 616:Core/core_cm0.h **** 
 617:Core/core_cm0.h **** /**
 618:Core/core_cm0.h ****   \brief   Enable Interrupt
 619:Core/core_cm0.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
ARM GAS  /tmp/cc3WhKxr.s 			page 14


 620:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 621:Core/core_cm0.h ****   \note    IRQn must not be negative.
 622:Core/core_cm0.h ****  */
 623:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 624:Core/core_cm0.h **** {
 625:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 626:Core/core_cm0.h ****   {
 627:Core/core_cm0.h ****     __COMPILER_BARRIER();
 628:Core/core_cm0.h ****     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 629:Core/core_cm0.h ****     __COMPILER_BARRIER();
 630:Core/core_cm0.h ****   }
 631:Core/core_cm0.h **** }
 632:Core/core_cm0.h **** 
 633:Core/core_cm0.h **** 
 634:Core/core_cm0.h **** /**
 635:Core/core_cm0.h ****   \brief   Get Interrupt Enable status
 636:Core/core_cm0.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
 637:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 638:Core/core_cm0.h ****   \return             0  Interrupt is not enabled.
 639:Core/core_cm0.h ****   \return             1  Interrupt is enabled.
 640:Core/core_cm0.h ****   \note    IRQn must not be negative.
 641:Core/core_cm0.h ****  */
 642:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 643:Core/core_cm0.h **** {
 644:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 645:Core/core_cm0.h ****   {
 646:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 647:Core/core_cm0.h ****   }
 648:Core/core_cm0.h ****   else
 649:Core/core_cm0.h ****   {
 650:Core/core_cm0.h ****     return(0U);
 651:Core/core_cm0.h ****   }
 652:Core/core_cm0.h **** }
 653:Core/core_cm0.h **** 
 654:Core/core_cm0.h **** 
 655:Core/core_cm0.h **** /**
 656:Core/core_cm0.h ****   \brief   Disable Interrupt
 657:Core/core_cm0.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
 658:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 659:Core/core_cm0.h ****   \note    IRQn must not be negative.
 660:Core/core_cm0.h ****  */
 661:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 662:Core/core_cm0.h **** {
 663:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 664:Core/core_cm0.h ****   {
 665:Core/core_cm0.h ****     NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 666:Core/core_cm0.h ****     __DSB();
 667:Core/core_cm0.h ****     __ISB();
 668:Core/core_cm0.h ****   }
 669:Core/core_cm0.h **** }
 670:Core/core_cm0.h **** 
 671:Core/core_cm0.h **** 
 672:Core/core_cm0.h **** /**
 673:Core/core_cm0.h ****   \brief   Get Pending Interrupt
 674:Core/core_cm0.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
 675:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 676:Core/core_cm0.h ****   \return             0  Interrupt status is not pending.
ARM GAS  /tmp/cc3WhKxr.s 			page 15


 677:Core/core_cm0.h ****   \return             1  Interrupt status is pending.
 678:Core/core_cm0.h ****   \note    IRQn must not be negative.
 679:Core/core_cm0.h ****  */
 680:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 681:Core/core_cm0.h **** {
 682:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 683:Core/core_cm0.h ****   {
 684:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 685:Core/core_cm0.h ****   }
 686:Core/core_cm0.h ****   else
 687:Core/core_cm0.h ****   {
 688:Core/core_cm0.h ****     return(0U);
 689:Core/core_cm0.h ****   }
 690:Core/core_cm0.h **** }
 691:Core/core_cm0.h **** 
 692:Core/core_cm0.h **** 
 693:Core/core_cm0.h **** /**
 694:Core/core_cm0.h ****   \brief   Set Pending Interrupt
 695:Core/core_cm0.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
 696:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 697:Core/core_cm0.h ****   \note    IRQn must not be negative.
 698:Core/core_cm0.h ****  */
 699:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 700:Core/core_cm0.h **** {
 701:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 702:Core/core_cm0.h ****   {
 703:Core/core_cm0.h ****     NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 704:Core/core_cm0.h ****   }
 705:Core/core_cm0.h **** }
 706:Core/core_cm0.h **** 
 707:Core/core_cm0.h **** 
 708:Core/core_cm0.h **** /**
 709:Core/core_cm0.h ****   \brief   Clear Pending Interrupt
 710:Core/core_cm0.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
 711:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 712:Core/core_cm0.h ****   \note    IRQn must not be negative.
 713:Core/core_cm0.h ****  */
 714:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 715:Core/core_cm0.h **** {
 716:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 717:Core/core_cm0.h ****   {
 718:Core/core_cm0.h ****     NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 719:Core/core_cm0.h ****   }
 720:Core/core_cm0.h **** }
 721:Core/core_cm0.h **** 
 722:Core/core_cm0.h **** 
 723:Core/core_cm0.h **** /**
 724:Core/core_cm0.h ****   \brief   Set Interrupt Priority
 725:Core/core_cm0.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
 726:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 727:Core/core_cm0.h ****            or negative to specify a processor exception.
 728:Core/core_cm0.h ****   \param [in]      IRQn  Interrupt number.
 729:Core/core_cm0.h ****   \param [in]  priority  Priority to set.
 730:Core/core_cm0.h ****   \note    The priority cannot be set for every processor exception.
 731:Core/core_cm0.h ****  */
 732:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 733:Core/core_cm0.h **** {
ARM GAS  /tmp/cc3WhKxr.s 			page 16


 734:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 735:Core/core_cm0.h ****   {
 736:Core/core_cm0.h ****     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))
 737:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 738:Core/core_cm0.h ****   }
 739:Core/core_cm0.h ****   else
 740:Core/core_cm0.h ****   {
 741:Core/core_cm0.h ****     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
 742:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 743:Core/core_cm0.h ****   }
 744:Core/core_cm0.h **** }
 745:Core/core_cm0.h **** 
 746:Core/core_cm0.h **** 
 747:Core/core_cm0.h **** /**
 748:Core/core_cm0.h ****   \brief   Get Interrupt Priority
 749:Core/core_cm0.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
 750:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 751:Core/core_cm0.h ****            or negative to specify a processor exception.
 752:Core/core_cm0.h ****   \param [in]   IRQn  Interrupt number.
 753:Core/core_cm0.h ****   \return             Interrupt Priority.
 754:Core/core_cm0.h ****                       Value is aligned automatically to the implemented priority bits of the microc
 755:Core/core_cm0.h ****  */
 756:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 757:Core/core_cm0.h **** {
 758:Core/core_cm0.h **** 
 759:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 760:Core/core_cm0.h ****   {
 761:Core/core_cm0.h ****     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 762:Core/core_cm0.h ****   }
 763:Core/core_cm0.h ****   else
 764:Core/core_cm0.h ****   {
 765:Core/core_cm0.h ****     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 766:Core/core_cm0.h ****   }
 767:Core/core_cm0.h **** }
 768:Core/core_cm0.h **** 
 769:Core/core_cm0.h **** 
 770:Core/core_cm0.h **** /**
 771:Core/core_cm0.h ****   \brief   Encode Priority
 772:Core/core_cm0.h ****   \details Encodes the priority for an interrupt with the given priority group,
 773:Core/core_cm0.h ****            preemptive priority value, and subpriority value.
 774:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 775:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 776:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 777:Core/core_cm0.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
 778:Core/core_cm0.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
 779:Core/core_cm0.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
 780:Core/core_cm0.h ****  */
 781:Core/core_cm0.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
 782:Core/core_cm0.h **** {
 783:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 784:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 785:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 786:Core/core_cm0.h **** 
 787:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 788:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 789:Core/core_cm0.h **** 
 790:Core/core_cm0.h ****   return (
ARM GAS  /tmp/cc3WhKxr.s 			page 17


 791:Core/core_cm0.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 792:Core/core_cm0.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 793:Core/core_cm0.h ****          );
 794:Core/core_cm0.h **** }
 795:Core/core_cm0.h **** 
 796:Core/core_cm0.h **** 
 797:Core/core_cm0.h **** /**
 798:Core/core_cm0.h ****   \brief   Decode Priority
 799:Core/core_cm0.h ****   \details Decodes an interrupt priority value with a given priority group to
 800:Core/core_cm0.h ****            preemptive priority value and subpriority value.
 801:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 802:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
 803:Core/core_cm0.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
 804:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 805:Core/core_cm0.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
 806:Core/core_cm0.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
 807:Core/core_cm0.h ****  */
 808:Core/core_cm0.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
 809:Core/core_cm0.h **** {
 810:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 811:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 812:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 813:Core/core_cm0.h **** 
 814:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 815:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 816:Core/core_cm0.h **** 
 817:Core/core_cm0.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
 818:Core/core_cm0.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 819:Core/core_cm0.h **** }
 820:Core/core_cm0.h **** 
 821:Core/core_cm0.h **** 
 822:Core/core_cm0.h **** 
 823:Core/core_cm0.h **** /**
 824:Core/core_cm0.h ****   \brief   Set Interrupt Vector
 825:Core/core_cm0.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
 826:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 827:Core/core_cm0.h ****            or negative to specify a processor exception.
 828:Core/core_cm0.h ****            Address 0 must be mapped to SRAM.
 829:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number
 830:Core/core_cm0.h ****   \param [in]   vector    Address of interrupt handler function
 831:Core/core_cm0.h ****  */
 832:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 833:Core/core_cm0.h **** {
 834:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 835:Core/core_cm0.h ****   *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to ac
 836:Core/core_cm0.h ****   /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
 837:Core/core_cm0.h **** }
 838:Core/core_cm0.h **** 
 839:Core/core_cm0.h **** 
 840:Core/core_cm0.h **** /**
 841:Core/core_cm0.h ****   \brief   Get Interrupt Vector
 842:Core/core_cm0.h ****   \details Reads an interrupt vector from interrupt vector table.
 843:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 844:Core/core_cm0.h ****            or negative to specify a processor exception.
 845:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number.
 846:Core/core_cm0.h ****   \return                 Address of interrupt handler function
 847:Core/core_cm0.h ****  */
ARM GAS  /tmp/cc3WhKxr.s 			page 18


 848:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 849:Core/core_cm0.h **** {
 850:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 851:Core/core_cm0.h ****   return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to ac
 852:Core/core_cm0.h **** }
 853:Core/core_cm0.h **** 
 854:Core/core_cm0.h **** 
 855:Core/core_cm0.h **** /**
 856:Core/core_cm0.h ****   \brief   System Reset
 857:Core/core_cm0.h ****   \details Initiates a system reset request to reset the MCU.
 858:Core/core_cm0.h ****  */
 859:Core/core_cm0.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
  67              		.loc 2 859 34 view .LVU7
  68              	.LBB13:
 860:Core/core_cm0.h **** {
 861:Core/core_cm0.h ****   __DSB();                                                          /* Ensure all outstanding memor
  69              		.loc 2 861 3 view .LVU8
  70              	.LBB14:
  71              	.LBI14:
  72              		.file 3 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cc3WhKxr.s 			page 19


  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
ARM GAS  /tmp/cc3WhKxr.s 			page 20


  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
ARM GAS  /tmp/cc3WhKxr.s 			page 21


 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
ARM GAS  /tmp/cc3WhKxr.s 			page 22


 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
ARM GAS  /tmp/cc3WhKxr.s 			page 23


 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
  73              		.loc 3 269 27 view .LVU9
  74              	.LBB15:
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
  75              		.loc 3 271 3 view .LVU10
  76              		.syntax divided
  77              	@ 271 "Core/cmsis_gcc.h" 1
  78 0008 BFF34F8F 		dsb 0xF
  79              	@ 0 "" 2
  80              		.thumb
  81              		.syntax unified
  82              	.LBE15:
  83              	.LBE14:
 862:Core/core_cm0.h ****                                                                        buffered write are completed
 863:Core/core_cm0.h ****   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  84              		.loc 2 863 3 view .LVU11
  85              		.loc 2 863 15 is_stmt 0 view .LVU12
  86 000c 034B     		ldr	r3, .L5
  87 000e 044A     		ldr	r2, .L5+4
  88 0010 DA60     		str	r2, [r3, #12]
 864:Core/core_cm0.h ****                  SCB_AIRCR_SYSRESETREQ_Msk);
 865:Core/core_cm0.h ****   __DSB();                                                          /* Ensure completion of memory 
  89              		.loc 2 865 3 is_stmt 1 view .LVU13
  90              	.LBB16:
  91              	.LBI16:
 269:Core/cmsis_gcc.h **** {
  92              		.loc 3 269 27 view .LVU14
  93              	.LBB17:
  94              		.loc 3 271 3 view .LVU15
  95              		.syntax divided
  96              	@ 271 "Core/cmsis_gcc.h" 1
  97 0012 BFF34F8F 		dsb 0xF
  98              	@ 0 "" 2
  99              		.thumb
 100              		.syntax unified
 101              	.L4:
 102              	.LBE17:
 103              	.LBE16:
 866:Core/core_cm0.h **** 
 867:Core/core_cm0.h ****   for(;;)                                                           /* wait until reset */
 104              		.loc 2 867 3 view .LVU16
 868:Core/core_cm0.h ****   {
 869:Core/core_cm0.h ****     __NOP();
 105              		.loc 2 869 5 discriminator 1 view .LVU17
 106              		.syntax divided
 107              	@ 869 "Core/core_cm0.h" 1
 108 0016 C046     		nop
 109              	@ 0 "" 2
 867:Core/core_cm0.h ****   {
 110              		.loc 2 867 3 view .LVU18
 111              		.thumb
 112              		.syntax unified
 113 0018 FDE7     		b	.L4
ARM GAS  /tmp/cc3WhKxr.s 			page 24


 114              	.L6:
 115 001a C046     		.align	2
 116              	.L5:
 117 001c 00ED00E0 		.word	-536810240
 118 0020 0400FA05 		.word	100270084
 119              	.LBE13:
 120              	.LBE12:
 121              		.cfi_endproc
 122              	.LFE46:
 124              		.section	.text.SVC_Handler,"ax",%progbits
 125              		.align	1
 126              		.p2align 2,,3
 127              		.global	SVC_Handler
 128              		.syntax unified
 129              		.code	16
 130              		.thumb_func
 132              	SVC_Handler:
 133              	.LFB51:
 134              		.cfi_startproc
  59:Hardware/lcm32f06x_it.c **** }
  60:Hardware/lcm32f06x_it.c **** 
  61:Hardware/lcm32f06x_it.c **** /**
  62:Hardware/lcm32f06x_it.c ****  * @name   SVC_Handler
  63:Hardware/lcm32f06x_it.c ****  * @brief  EN: This function handles SVCall exception.
  64:Hardware/lcm32f06x_it.c ****  *         CN: 此函数用于处理SVCall异常。
  65:Hardware/lcm32f06x_it.c ****  * @param  None
  66:Hardware/lcm32f06x_it.c ****  * @retval None
  67:Hardware/lcm32f06x_it.c ****  */
  68:Hardware/lcm32f06x_it.c **** void SVC_Handler(void)
 135              		.loc 1 68 6 view -0
 136              		@ args = 0, pretend = 0, frame = 0
 137              		@ frame_needed = 0, uses_anonymous_args = 0
 138              		@ link register save eliminated.
 139              		@ sp needed
 140 0000 7047     		bx	lr
 141              		.cfi_endproc
 142              	.LFE51:
 144 0002 C046     		.section	.text.PendSV_Handler,"ax",%progbits
 145              		.align	1
 146              		.p2align 2,,3
 147              		.global	PendSV_Handler
 148              		.syntax unified
 149              		.code	16
 150              		.thumb_func
 152              	PendSV_Handler:
 153              	.LFB53:
 154              		.cfi_startproc
  69:Hardware/lcm32f06x_it.c **** {
  70:Hardware/lcm32f06x_it.c **** }
  71:Hardware/lcm32f06x_it.c **** 
  72:Hardware/lcm32f06x_it.c **** /**
  73:Hardware/lcm32f06x_it.c ****  * @name   PendSV_Handler
  74:Hardware/lcm32f06x_it.c ****  * @brief  EN: This function handles PendSVC exception.
  75:Hardware/lcm32f06x_it.c ****  *         CN: 此函数用于处理PendSVC异常。
  76:Hardware/lcm32f06x_it.c ****  * @param  None
  77:Hardware/lcm32f06x_it.c ****  * @retval None
  78:Hardware/lcm32f06x_it.c ****  */
ARM GAS  /tmp/cc3WhKxr.s 			page 25


  79:Hardware/lcm32f06x_it.c **** void PendSV_Handler(void)
 155              		.loc 1 79 6 view -0
 156              		@ args = 0, pretend = 0, frame = 0
 157              		@ frame_needed = 0, uses_anonymous_args = 0
 158              		@ link register save eliminated.
 159              		@ sp needed
 160 0000 7047     		bx	lr
 161              		.cfi_endproc
 162              	.LFE53:
 164 0002 C046     		.section	.text.SysTick_Handler,"ax",%progbits
 165              		.align	1
 166              		.p2align 2,,3
 167              		.global	SysTick_Handler
 168              		.syntax unified
 169              		.code	16
 170              		.thumb_func
 172              	SysTick_Handler:
 173              	.LFB49:
  80:Hardware/lcm32f06x_it.c **** {
  81:Hardware/lcm32f06x_it.c **** }
  82:Hardware/lcm32f06x_it.c **** 
  83:Hardware/lcm32f06x_it.c **** /**
  84:Hardware/lcm32f06x_it.c ****  * @name   SysTick_Handler
  85:Hardware/lcm32f06x_it.c ****  * @brief  EN: This function handles SysTick Handler.
  86:Hardware/lcm32f06x_it.c ****  *         CN: 此函数处理SysTick处理程序。
  87:Hardware/lcm32f06x_it.c ****  * @param  None
  88:Hardware/lcm32f06x_it.c ****  * @retval None
  89:Hardware/lcm32f06x_it.c ****  */
  90:Hardware/lcm32f06x_it.c **** void SysTick_Handler(void)
  91:Hardware/lcm32f06x_it.c **** {
 174              		.loc 1 91 1 view -0
 175              		.cfi_startproc
 176              		@ args = 0, pretend = 0, frame = 0
 177              		@ frame_needed = 0, uses_anonymous_args = 0
  92:Hardware/lcm32f06x_it.c ****   task_on_timer(&g_task_handle, 1);
 178              		.loc 1 92 3 view .LVU22
  91:Hardware/lcm32f06x_it.c ****   task_on_timer(&g_task_handle, 1);
 179              		.loc 1 91 1 is_stmt 0 view .LVU23
 180 0000 10B5     		push	{r4, lr}
 181              	.LCFI1:
 182              		.cfi_def_cfa_offset 8
 183              		.cfi_offset 4, -8
 184              		.cfi_offset 14, -4
 185              		.loc 1 92 3 view .LVU24
 186 0002 0121     		movs	r1, #1
  93:Hardware/lcm32f06x_it.c **** }
 187              		.loc 1 93 1 view .LVU25
 188              		@ sp needed
  92:Hardware/lcm32f06x_it.c ****   task_on_timer(&g_task_handle, 1);
 189              		.loc 1 92 3 view .LVU26
 190 0004 0148     		ldr	r0, .L10
 191 0006 FFF7FEFF 		bl	task_on_timer
 192              	.LVL1:
 193              		.loc 1 93 1 view .LVU27
 194 000a 10BD     		pop	{r4, pc}
 195              	.L11:
 196              		.align	2
ARM GAS  /tmp/cc3WhKxr.s 			page 26


 197              	.L10:
 198 000c 00000000 		.word	g_task_handle
 199              		.cfi_endproc
 200              	.LFE49:
 202              		.text
 203              	.Letext0:
 204              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 205              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 206              		.file 6 "Component/task/task_define.h"
 207              		.file 7 "Component/task/task.h"
 208              		.file 8 "Library/inc/lcm32f06x_rcc.h"
 209              		.file 9 "User/global.h"
 210              		.file 10 "Library/inc/lcm32f06x.h"
ARM GAS  /tmp/cc3WhKxr.s 			page 27


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_it.c
     /tmp/cc3WhKxr.s:17     .text.NMI_Handler:00000000 $t
     /tmp/cc3WhKxr.s:24     .text.NMI_Handler:00000000 NMI_Handler
     /tmp/cc3WhKxr.s:38     .text.HardFault_Handler:00000000 $t
     /tmp/cc3WhKxr.s:45     .text.HardFault_Handler:00000000 HardFault_Handler
     /tmp/cc3WhKxr.s:117    .text.HardFault_Handler:0000001c $d
     /tmp/cc3WhKxr.s:125    .text.SVC_Handler:00000000 $t
     /tmp/cc3WhKxr.s:132    .text.SVC_Handler:00000000 SVC_Handler
     /tmp/cc3WhKxr.s:145    .text.PendSV_Handler:00000000 $t
     /tmp/cc3WhKxr.s:152    .text.PendSV_Handler:00000000 PendSV_Handler
     /tmp/cc3WhKxr.s:165    .text.SysTick_Handler:00000000 $t
     /tmp/cc3WhKxr.s:172    .text.SysTick_Handler:00000000 SysTick_Handler
     /tmp/cc3WhKxr.s:198    .text.SysTick_Handler:0000000c $d

UNDEFINED SYMBOLS
delay10us
task_on_timer
g_task_handle
