ARM GAS  /tmp/cclh89PE.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_adc.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Library/src/lcm32f06x_adc.c"
  16              		.section	.text.ADC_DeInit,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	ADC_DeInit
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	ADC_DeInit:
  25              	.LVL0:
  26              	.LFB45:
   1:Library/src/lcm32f06x_adc.c **** /**
   2:Library/src/lcm32f06x_adc.c ****   ******************************************************************************
   3:Library/src/lcm32f06x_adc.c ****   * @file    lcm32f06x_adc.c
   4:Library/src/lcm32f06x_adc.c ****   * @author  System R&D Team
   5:Library/src/lcm32f06x_adc.c ****   * @version V2.0.2
   6:Library/src/lcm32f06x_adc.c ****   * @date    10-April-2025
   7:Library/src/lcm32f06x_adc.c ****   * @brief   This file provides all the adc firmware functions.
   8:Library/src/lcm32f06x_adc.c ****   ******************************************************************************
   9:Library/src/lcm32f06x_adc.c ****   * @attention
  10:Library/src/lcm32f06x_adc.c ****   *
  11:Library/src/lcm32f06x_adc.c ****   * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  12:Library/src/lcm32f06x_adc.c ****   * All rights reserved.
  13:Library/src/lcm32f06x_adc.c ****   *
  14:Library/src/lcm32f06x_adc.c ****   * This software is licensed under terms that can be found in the LICENSE file
  15:Library/src/lcm32f06x_adc.c ****   * in the root directory of this software component.
  16:Library/src/lcm32f06x_adc.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  17:Library/src/lcm32f06x_adc.c ****   *
  18:Library/src/lcm32f06x_adc.c ****   ******************************************************************************
  19:Library/src/lcm32f06x_adc.c ****   */
  20:Library/src/lcm32f06x_adc.c **** 
  21:Library/src/lcm32f06x_adc.c **** /* Includes ------------------------------------------------------------------*/
  22:Library/src/lcm32f06x_adc.c **** #include "lcm32f06x_adc.h"
  23:Library/src/lcm32f06x_adc.c **** 
  24:Library/src/lcm32f06x_adc.c **** /**
  25:Library/src/lcm32f06x_adc.c ****   * @name   ADC_DeInit
  26:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Deinitializes ADC peripheral registers to their default reset values.
  27:Library/src/lcm32f06x_adc.c ****   *         CN: ??ADC??¦¶???????????????????????
  28:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
  29:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
  30:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
  31:Library/src/lcm32f06x_adc.c ****   * @retval None
  32:Library/src/lcm32f06x_adc.c ****   */
ARM GAS  /tmp/cclh89PE.s 			page 2


  33:Library/src/lcm32f06x_adc.c **** void ADC_DeInit(ADC_TypeDef *ADCx)
  34:Library/src/lcm32f06x_adc.c **** {
  27              		.loc 1 34 1 view -0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 0
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  35:Library/src/lcm32f06x_adc.c ****   if (ADCx == ADC)
  31              		.loc 1 35 3 view .LVU1
  32              		.loc 1 35 6 is_stmt 0 view .LVU2
  33 0000 074B     		ldr	r3, .L5
  34:Library/src/lcm32f06x_adc.c ****   if (ADCx == ADC)
  34              		.loc 1 34 1 view .LVU3
  35 0002 10B5     		push	{r4, lr}
  36              	.LCFI0:
  37              		.cfi_def_cfa_offset 8
  38              		.cfi_offset 4, -8
  39              		.cfi_offset 14, -4
  40              		.loc 1 35 6 view .LVU4
  41 0004 9842     		cmp	r0, r3
  42 0006 00D0     		beq	.L4
  43              	.LVL1:
  44              	.L1:
  36:Library/src/lcm32f06x_adc.c ****   {
  37:Library/src/lcm32f06x_adc.c ****     /* Release ADC1 from reset state */
  38:Library/src/lcm32f06x_adc.c ****     RCC_APB0PeriphResetCmd(RCC_APB0Periph_ADC, ENABLE);
  39:Library/src/lcm32f06x_adc.c ****     /* Enable ADC1 reset state */
  40:Library/src/lcm32f06x_adc.c ****     RCC_APB0PeriphResetCmd(RCC_APB0Periph_ADC, DISABLE);
  41:Library/src/lcm32f06x_adc.c ****   }
  42:Library/src/lcm32f06x_adc.c **** }
  45              		.loc 1 42 1 view .LVU5
  46              		@ sp needed
  47 0008 10BD     		pop	{r4, pc}
  48              	.LVL2:
  49              	.L4:
  38:Library/src/lcm32f06x_adc.c ****     /* Enable ADC1 reset state */
  50              		.loc 1 38 5 is_stmt 1 view .LVU6
  51 000a 8020     		movs	r0, #128
  52              	.LVL3:
  38:Library/src/lcm32f06x_adc.c ****     /* Enable ADC1 reset state */
  53              		.loc 1 38 5 is_stmt 0 view .LVU7
  54 000c 0121     		movs	r1, #1
  55 000e 8000     		lsls	r0, r0, #2
  56 0010 FFF7FEFF 		bl	RCC_APB0PeriphResetCmd
  57              	.LVL4:
  40:Library/src/lcm32f06x_adc.c ****   }
  58              		.loc 1 40 5 is_stmt 1 view .LVU8
  59 0014 8020     		movs	r0, #128
  60 0016 0021     		movs	r1, #0
  61 0018 8000     		lsls	r0, r0, #2
  62 001a FFF7FEFF 		bl	RCC_APB0PeriphResetCmd
  63              	.LVL5:
  64              		.loc 1 42 1 is_stmt 0 view .LVU9
  65 001e F3E7     		b	.L1
  66              	.L6:
  67              		.align	2
  68              	.L5:
  69 0020 00A00140 		.word	1073848320
ARM GAS  /tmp/cclh89PE.s 			page 3


  70              		.cfi_endproc
  71              	.LFE45:
  73              		.section	.text.ADC_Cmd,"ax",%progbits
  74              		.align	1
  75              		.p2align 2,,3
  76              		.global	ADC_Cmd
  77              		.syntax unified
  78              		.code	16
  79              		.thumb_func
  81              	ADC_Cmd:
  82              	.LVL6:
  83              	.LFB46:
  43:Library/src/lcm32f06x_adc.c **** 
  44:Library/src/lcm32f06x_adc.c **** /**
  45:Library/src/lcm32f06x_adc.c ****   * @name   ADC_Cmd
  46:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Enables or disables the specified ADC peripheral.
  47:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC??¦¶?õô??
  48:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
  49:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
  50:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
  51:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
  52:Library/src/lcm32f06x_adc.c ****   *         EN: New state of the ADC peripheral.
  53:Library/src/lcm32f06x_adc.c ****   *         CN: ADC??¦¶?õô????????
  54:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
  55:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
  56:Library/src/lcm32f06x_adc.c ****   * @retval None
  57:Library/src/lcm32f06x_adc.c ****   */
  58:Library/src/lcm32f06x_adc.c **** void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState State)
  59:Library/src/lcm32f06x_adc.c **** {
  84              		.loc 1 59 1 is_stmt 1 view -0
  85              		.cfi_startproc
  86              		@ args = 0, pretend = 0, frame = 0
  87              		@ frame_needed = 0, uses_anonymous_args = 0
  88              		@ link register save eliminated.
  60:Library/src/lcm32f06x_adc.c ****   if (State != DISABLE)
  89              		.loc 1 60 3 view .LVU11
  90              		.loc 1 60 6 is_stmt 0 view .LVU12
  91 0000 0029     		cmp	r1, #0
  92 0002 1CD0     		beq	.L8
  61:Library/src/lcm32f06x_adc.c ****   {
  62:Library/src/lcm32f06x_adc.c ****     /* Set the ADEN bit to Enable the ADC peripheral */
  63:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_ADC = 0;
  93              		.loc 1 63 5 is_stmt 1 view .LVU13
  94              		.loc 1 63 24 is_stmt 0 view .LVU14
  95 0004 838C     		ldrh	r3, [r0, #36]
  64:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_REF = 0;
  96              		.loc 1 64 24 view .LVU15
  97 0006 244A     		ldr	r2, .L18
  63:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_REF = 0;
  98              		.loc 1 63 24 view .LVU16
  99 0008 5B04     		lsls	r3, r3, #17
 100 000a 5B0C     		lsrs	r3, r3, #17
 101 000c 8384     		strh	r3, [r0, #36]
 102              		.loc 1 64 5 is_stmt 1 view .LVU17
 103              		.loc 1 64 24 is_stmt 0 view .LVU18
 104 000e 838C     		ldrh	r3, [r0, #36]
 105 0010 1340     		ands	r3, r2
ARM GAS  /tmp/cclh89PE.s 			page 4


 106 0012 8384     		strh	r3, [r0, #36]
  65:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHA = 0;
 107              		.loc 1 65 5 is_stmt 1 view .LVU19
 108              		.loc 1 65 24 is_stmt 0 view .LVU20
 109 0014 838C     		ldrh	r3, [r0, #36]
 110 0016 214A     		ldr	r2, .L18+4
 111 0018 1340     		ands	r3, r2
 112 001a 8384     		strh	r3, [r0, #36]
  66:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHB = 0;
 113              		.loc 1 66 5 is_stmt 1 view .LVU21
 114              		.loc 1 66 24 is_stmt 0 view .LVU22
 115 001c 838C     		ldrh	r3, [r0, #36]
 116 001e 204A     		ldr	r2, .L18+8
 117 0020 1340     		ands	r3, r2
  67:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.EN = 1;
 118              		.loc 1 67 19 view .LVU23
 119 0022 0122     		movs	r2, #1
  66:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHB = 0;
 120              		.loc 1 66 24 view .LVU24
 121 0024 8384     		strh	r3, [r0, #36]
 122              		.loc 1 67 5 is_stmt 1 view .LVU25
 123              		.loc 1 67 19 is_stmt 0 view .LVU26
 124 0026 4369     		ldr	r3, [r0, #20]
 125 0028 1343     		orrs	r3, r2
 126 002a 4361     		str	r3, [r0, #20]
 127              	.L10:
  68:Library/src/lcm32f06x_adc.c ****     do
 128              		.loc 1 68 5 is_stmt 1 view .LVU27
  69:Library/src/lcm32f06x_adc.c ****     {
  70:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 129              		.loc 1 70 7 view .LVU28
 130              		.syntax divided
 131              	@ 70 "Library/src/lcm32f06x_adc.c" 1
 132 002c C046     		nop
 133              	@ 0 "" 2
 134              		.loc 1 70 16 view .LVU29
 135              	@ 70 "Library/src/lcm32f06x_adc.c" 1
 136 002e C046     		nop
 137              	@ 0 "" 2
 138              		.loc 1 70 25 view .LVU30
 139              	@ 70 "Library/src/lcm32f06x_adc.c" 1
 140 0030 C046     		nop
 141              	@ 0 "" 2
 142              		.loc 1 70 34 view .LVU31
 143              	@ 70 "Library/src/lcm32f06x_adc.c" 1
 144 0032 C046     		nop
 145              	@ 0 "" 2
 146              		.loc 1 70 43 view .LVU32
 147              	@ 70 "Library/src/lcm32f06x_adc.c" 1
 148 0034 C046     		nop
 149              	@ 0 "" 2
  71:Library/src/lcm32f06x_adc.c ****     } while (ADCx->SR_b.READY == 0);
 150              		.loc 1 71 31 discriminator 1 view .LVU33
 151              		.loc 1 71 24 is_stmt 0 discriminator 1 view .LVU34
 152              		.thumb
 153              		.syntax unified
 154 0036 0368     		ldr	r3, [r0]
ARM GAS  /tmp/cclh89PE.s 			page 5


 155              		.loc 1 71 31 discriminator 1 view .LVU35
 156 0038 DB07     		lsls	r3, r3, #31
 157 003a F7D5     		bpl	.L10
 158              	.L7:
  72:Library/src/lcm32f06x_adc.c ****   }
  73:Library/src/lcm32f06x_adc.c ****   else
  74:Library/src/lcm32f06x_adc.c ****   {
  75:Library/src/lcm32f06x_adc.c ****     /* Set the ADDIS to Disable the ADC peripheral */
  76:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.STOP = 1;
  77:Library/src/lcm32f06x_adc.c ****     do
  78:Library/src/lcm32f06x_adc.c ****     {
  79:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
  80:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
  81:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.DIS = 1;
  82:Library/src/lcm32f06x_adc.c ****     do
  83:Library/src/lcm32f06x_adc.c ****     {
  84:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
  85:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
  86:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_ADC = 1;
  87:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_REF = 1;
  88:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHA = 1;
  89:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHB = 1;
  90:Library/src/lcm32f06x_adc.c ****   }
  91:Library/src/lcm32f06x_adc.c **** }
 159              		.loc 1 91 1 view .LVU36
 160              		@ sp needed
 161 003c 7047     		bx	lr
 162              	.L8:
  76:Library/src/lcm32f06x_adc.c ****     do
 163              		.loc 1 76 5 is_stmt 1 view .LVU37
  76:Library/src/lcm32f06x_adc.c ****     do
 164              		.loc 1 76 21 is_stmt 0 view .LVU38
 165 003e 0822     		movs	r2, #8
 166 0040 4369     		ldr	r3, [r0, #20]
 167 0042 1343     		orrs	r3, r2
 168 0044 4361     		str	r3, [r0, #20]
 169              	.L11:
  77:Library/src/lcm32f06x_adc.c ****     {
 170              		.loc 1 77 5 is_stmt 1 view .LVU39
  79:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 171              		.loc 1 79 7 view .LVU40
 172              		.syntax divided
 173              	@ 79 "Library/src/lcm32f06x_adc.c" 1
 174 0046 C046     		nop
 175              	@ 0 "" 2
  79:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 176              		.loc 1 79 16 view .LVU41
 177              	@ 79 "Library/src/lcm32f06x_adc.c" 1
 178 0048 C046     		nop
 179              	@ 0 "" 2
  79:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 180              		.loc 1 79 25 view .LVU42
 181              	@ 79 "Library/src/lcm32f06x_adc.c" 1
 182 004a C046     		nop
 183              	@ 0 "" 2
  79:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 184              		.loc 1 79 34 view .LVU43
ARM GAS  /tmp/cclh89PE.s 			page 6


 185              	@ 79 "Library/src/lcm32f06x_adc.c" 1
 186 004c C046     		nop
 187              	@ 0 "" 2
  79:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 188              		.loc 1 79 43 view .LVU44
 189              	@ 79 "Library/src/lcm32f06x_adc.c" 1
 190 004e C046     		nop
 191              	@ 0 "" 2
  80:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.DIS = 1;
 192              		.loc 1 80 14 discriminator 1 view .LVU45
  80:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.DIS = 1;
 193              		.loc 1 80 24 is_stmt 0 discriminator 1 view .LVU46
 194              		.thumb
 195              		.syntax unified
 196 0050 4369     		ldr	r3, [r0, #20]
  80:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.DIS = 1;
 197              		.loc 1 80 14 discriminator 1 view .LVU47
 198 0052 1B07     		lsls	r3, r3, #28
 199 0054 F7D4     		bmi	.L11
  81:Library/src/lcm32f06x_adc.c ****     do
 200              		.loc 1 81 5 is_stmt 1 view .LVU48
  81:Library/src/lcm32f06x_adc.c ****     do
 201              		.loc 1 81 20 is_stmt 0 view .LVU49
 202 0056 0222     		movs	r2, #2
 203 0058 4369     		ldr	r3, [r0, #20]
 204 005a 1343     		orrs	r3, r2
 205 005c 4361     		str	r3, [r0, #20]
 206              	.L12:
  82:Library/src/lcm32f06x_adc.c ****     {
 207              		.loc 1 82 5 is_stmt 1 view .LVU50
  84:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
 208              		.loc 1 84 7 view .LVU51
 209              		.syntax divided
 210              	@ 84 "Library/src/lcm32f06x_adc.c" 1
 211 005e C046     		nop
 212              	@ 0 "" 2
  84:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
 213              		.loc 1 84 16 view .LVU52
 214              	@ 84 "Library/src/lcm32f06x_adc.c" 1
 215 0060 C046     		nop
 216              	@ 0 "" 2
  84:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
 217              		.loc 1 84 25 view .LVU53
 218              	@ 84 "Library/src/lcm32f06x_adc.c" 1
 219 0062 C046     		nop
 220              	@ 0 "" 2
  84:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
 221              		.loc 1 84 34 view .LVU54
 222              	@ 84 "Library/src/lcm32f06x_adc.c" 1
 223 0064 C046     		nop
 224              	@ 0 "" 2
  84:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.EN);
 225              		.loc 1 84 43 view .LVU55
 226              	@ 84 "Library/src/lcm32f06x_adc.c" 1
 227 0066 C046     		nop
 228              	@ 0 "" 2
  85:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_ADC = 1;
ARM GAS  /tmp/cclh89PE.s 			page 7


 229              		.loc 1 85 14 discriminator 1 view .LVU56
  85:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_ADC = 1;
 230              		.loc 1 85 24 is_stmt 0 discriminator 1 view .LVU57
 231              		.thumb
 232              		.syntax unified
 233 0068 4369     		ldr	r3, [r0, #20]
  85:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_ADC = 1;
 234              		.loc 1 85 14 discriminator 1 view .LVU58
 235 006a DB07     		lsls	r3, r3, #31
 236 006c F7D4     		bmi	.L12
  86:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_REF = 1;
 237              		.loc 1 86 5 is_stmt 1 view .LVU59
  86:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_REF = 1;
 238              		.loc 1 86 24 is_stmt 0 view .LVU60
 239 006e 828C     		ldrh	r2, [r0, #36]
 240 0070 0C4B     		ldr	r3, .L18+12
 241 0072 1343     		orrs	r3, r2
 242 0074 8384     		strh	r3, [r0, #36]
  87:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHA = 1;
 243              		.loc 1 87 5 is_stmt 1 view .LVU61
  87:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHA = 1;
 244              		.loc 1 87 24 is_stmt 0 view .LVU62
 245 0076 8023     		movs	r3, #128
 246 0078 828C     		ldrh	r2, [r0, #36]
 247 007a DB01     		lsls	r3, r3, #7
 248 007c 1343     		orrs	r3, r2
 249 007e 8384     		strh	r3, [r0, #36]
  88:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHB = 1;
 250              		.loc 1 88 5 is_stmt 1 view .LVU63
  88:Library/src/lcm32f06x_adc.c ****     ADCx->ANA_b.PD_SHB = 1;
 251              		.loc 1 88 24 is_stmt 0 view .LVU64
 252 0080 8023     		movs	r3, #128
 253 0082 828C     		ldrh	r2, [r0, #36]
 254 0084 5B01     		lsls	r3, r3, #5
 255 0086 1343     		orrs	r3, r2
 256 0088 8384     		strh	r3, [r0, #36]
  89:Library/src/lcm32f06x_adc.c ****   }
 257              		.loc 1 89 5 is_stmt 1 view .LVU65
  89:Library/src/lcm32f06x_adc.c ****   }
 258              		.loc 1 89 24 is_stmt 0 view .LVU66
 259 008a 8023     		movs	r3, #128
 260 008c 828C     		ldrh	r2, [r0, #36]
 261 008e 9B01     		lsls	r3, r3, #6
 262 0090 1343     		orrs	r3, r2
 263 0092 8384     		strh	r3, [r0, #36]
 264              		.loc 1 91 1 view .LVU67
 265 0094 D2E7     		b	.L7
 266              	.L19:
 267 0096 C046     		.align	2
 268              	.L18:
 269 0098 FFBFFFFF 		.word	-16385
 270 009c FFEFFFFF 		.word	-4097
 271 00a0 FFDFFFFF 		.word	-8193
 272 00a4 0080FFFF 		.word	-32768
 273              		.cfi_endproc
 274              	.LFE46:
 276              		.section	.text.ADC_StructInit,"ax",%progbits
ARM GAS  /tmp/cclh89PE.s 			page 8


 277              		.align	1
 278              		.p2align 2,,3
 279              		.global	ADC_StructInit
 280              		.syntax unified
 281              		.code	16
 282              		.thumb_func
 284              	ADC_StructInit:
 285              	.LVL7:
 286              	.LFB47:
  92:Library/src/lcm32f06x_adc.c **** 
  93:Library/src/lcm32f06x_adc.c **** /**
  94:Library/src/lcm32f06x_adc.c ****   * @name   ADC_StructInit
  95:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Fills each ADC_InitStruct member with its default value.
  96:Library/src/lcm32f06x_adc.c ****   *         CN: ????????????ADC_InitStruct?????
  97:Library/src/lcm32f06x_adc.c ****   * @param  ADC_InitStruct: 
  98:Library/src/lcm32f06x_adc.c ****   *         EN: pointer to an ADC_InitTypeDef structure which will be initialized.
  99:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????ADC_InitTypeDef???????
 100:Library/src/lcm32f06x_adc.c ****   * @retval None
 101:Library/src/lcm32f06x_adc.c ****   */
 102:Library/src/lcm32f06x_adc.c **** void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
 103:Library/src/lcm32f06x_adc.c **** {
 287              		.loc 1 103 1 is_stmt 1 view -0
 288              		.cfi_startproc
 289              		@ args = 0, pretend = 0, frame = 0
 290              		@ frame_needed = 0, uses_anonymous_args = 0
 291              		@ link register save eliminated.
 104:Library/src/lcm32f06x_adc.c ****   /* Reset ADC init structure parameters values */
 105:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ClkMode = ADC_ClockMode_SynClkDiv1;
 292              		.loc 1 105 3 view .LVU69
 293              		.loc 1 105 31 is_stmt 0 view .LVU70
 294 0000 0023     		movs	r3, #0
 106:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ReferenceVoltage = ADC_ReferenceVoltage_3V2;
 107:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_VCCChanelMapping = ADC_VCCChanel_DISABLE;
 108:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempChanelMapping = ADC_TempChanel_DISABLE;
 109:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_WorkMode = ADC_WorkMode_Normal;
 110:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_OverFlowMode = ADC_OverFlow_New;
 111:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_LowPowerMode = DISABLE;
 112:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 113:Library/src/lcm32f06x_adc.c ****   
 114:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_SampleTime = 7;       // ????¦¶0-7;AD ?????????????? ????? 010?????????=(x+1)
 115:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_AdjustTime = 7;       // ????¦¶0-7;AD ???????????????? ????? 010?????????=(x+
 116:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertTime = 0;      // ????¦¶0-15;????????
 117:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertPulseTime = 0; // ????¦¶0-1;?????????????? ????? 0?????????=(x+3)*CLK
 118:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempPulseTime = 0;    // ????¦¶0-15;?????????????
 119:Library/src/lcm32f06x_adc.c **** }
 295              		.loc 1 119 1 view .LVU71
 296              		@ sp needed
 114:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_AdjustTime = 7;       // ????¦¶0-7;AD ???????????????? ????? 010?????????=(x+
 297              		.loc 1 114 34 view .LVU72
 298 0002 0722     		movs	r2, #7
 105:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ReferenceVoltage = ADC_ReferenceVoltage_3V2;
 299              		.loc 1 105 31 view .LVU73
 300 0004 0360     		str	r3, [r0]
 106:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ReferenceVoltage = ADC_ReferenceVoltage_3V2;
 301              		.loc 1 106 3 is_stmt 1 view .LVU74
 106:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ReferenceVoltage = ADC_ReferenceVoltage_3V2;
 302              		.loc 1 106 40 is_stmt 0 view .LVU75
ARM GAS  /tmp/cclh89PE.s 			page 9


 303 0006 4360     		str	r3, [r0, #4]
 107:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempChanelMapping = ADC_TempChanel_DISABLE;
 304              		.loc 1 107 3 is_stmt 1 view .LVU76
 107:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempChanelMapping = ADC_TempChanel_DISABLE;
 305              		.loc 1 107 40 is_stmt 0 view .LVU77
 306 0008 8360     		str	r3, [r0, #8]
 108:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_WorkMode = ADC_WorkMode_Normal;
 307              		.loc 1 108 3 is_stmt 1 view .LVU78
 108:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_WorkMode = ADC_WorkMode_Normal;
 308              		.loc 1 108 41 is_stmt 0 view .LVU79
 309 000a C360     		str	r3, [r0, #12]
 109:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_OverFlowMode = ADC_OverFlow_New;
 310              		.loc 1 109 3 is_stmt 1 view .LVU80
 109:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_OverFlowMode = ADC_OverFlow_New;
 311              		.loc 1 109 32 is_stmt 0 view .LVU81
 312 000c 0361     		str	r3, [r0, #16]
 110:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_LowPowerMode = DISABLE;
 313              		.loc 1 110 3 is_stmt 1 view .LVU82
 110:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_LowPowerMode = DISABLE;
 314              		.loc 1 110 36 is_stmt 0 view .LVU83
 315 000e 4361     		str	r3, [r0, #20]
 111:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 316              		.loc 1 111 3 is_stmt 1 view .LVU84
 111:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
 317              		.loc 1 111 36 is_stmt 0 view .LVU85
 318 0010 0376     		strb	r3, [r0, #24]
 112:Library/src/lcm32f06x_adc.c ****   
 319              		.loc 1 112 3 is_stmt 1 view .LVU86
 112:Library/src/lcm32f06x_adc.c ****   
 320              		.loc 1 112 33 is_stmt 0 view .LVU87
 321 0012 C361     		str	r3, [r0, #28]
 114:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_AdjustTime = 7;       // ????¦¶0-7;AD ???????????????? ????? 010?????????=(x+
 322              		.loc 1 114 3 is_stmt 1 view .LVU88
 114:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_AdjustTime = 7;       // ????¦¶0-7;AD ???????????????? ????? 010?????????=(x+
 323              		.loc 1 114 34 is_stmt 0 view .LVU89
 324 0014 C262     		str	r2, [r0, #44]
 115:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertTime = 0;      // ????¦¶0-15;????????
 325              		.loc 1 115 3 is_stmt 1 view .LVU90
 115:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertTime = 0;      // ????¦¶0-15;????????
 326              		.loc 1 115 34 is_stmt 0 view .LVU91
 327 0016 0263     		str	r2, [r0, #48]
 116:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertPulseTime = 0; // ????¦¶0-1;?????????????? ????? 0?????????=(x+3)*CLK
 328              		.loc 1 116 3 is_stmt 1 view .LVU92
 116:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_ConvertPulseTime = 0; // ????¦¶0-1;?????????????? ????? 0?????????=(x+3)*CLK
 329              		.loc 1 116 35 is_stmt 0 view .LVU93
 330 0018 4362     		str	r3, [r0, #36]
 117:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempPulseTime = 0;    // ????¦¶0-15;?????????????
 331              		.loc 1 117 3 is_stmt 1 view .LVU94
 117:Library/src/lcm32f06x_adc.c ****   ADC_InitStruct->ADC_TempPulseTime = 0;    // ????¦¶0-15;?????????????
 332              		.loc 1 117 40 is_stmt 0 view .LVU95
 333 001a 8362     		str	r3, [r0, #40]
 118:Library/src/lcm32f06x_adc.c **** }
 334              		.loc 1 118 3 is_stmt 1 view .LVU96
 118:Library/src/lcm32f06x_adc.c **** }
 335              		.loc 1 118 37 is_stmt 0 view .LVU97
 336 001c 0362     		str	r3, [r0, #32]
 337              		.loc 1 119 1 view .LVU98
ARM GAS  /tmp/cclh89PE.s 			page 10


 338 001e 7047     		bx	lr
 339              		.cfi_endproc
 340              	.LFE47:
 342              		.section	.text.ADC_Init,"ax",%progbits
 343              		.align	1
 344              		.p2align 2,,3
 345              		.global	ADC_Init
 346              		.syntax unified
 347              		.code	16
 348              		.thumb_func
 350              	ADC_Init:
 351              	.LVL8:
 352              	.LFB48:
 120:Library/src/lcm32f06x_adc.c **** 
 121:Library/src/lcm32f06x_adc.c **** /**
 122:Library/src/lcm32f06x_adc.c ****   * @name   ADC_Init
 123:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Initializes the ADCx peripheral according to the specified parameters in the ADC_In
 124:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????????ADCx??¦¶?õô??ADC_InitStruct?§³?
 125:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 126:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 127:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 128:Library/src/lcm32f06x_adc.c ****   * @param  ADC_InitStruct: 
 129:Library/src/lcm32f06x_adc.c ****   *         EN: Pointer to an ADC_InitTypeDef structure that contains the configuration information
 130:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC_InitTypeDef?????????????????ADC??¦¶?õô???????????
 131:Library/src/lcm32f06x_adc.c ****   * @retval None
 132:Library/src/lcm32f06x_adc.c ****   */
 133:Library/src/lcm32f06x_adc.c **** void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
 134:Library/src/lcm32f06x_adc.c **** {
 353              		.loc 1 134 1 is_stmt 1 view -0
 354              		.cfi_startproc
 355              		@ args = 0, pretend = 0, frame = 0
 356              		@ frame_needed = 0, uses_anonymous_args = 0
 135:Library/src/lcm32f06x_adc.c ****   uint32_t tmpreg0 = 0;
 357              		.loc 1 135 3 view .LVU100
 136:Library/src/lcm32f06x_adc.c ****   uint32_t tmpreg1 = 0;
 358              		.loc 1 136 3 view .LVU101
 137:Library/src/lcm32f06x_adc.c ****   uint32_t AD_TRIM_temp = 0;
 359              		.loc 1 137 3 view .LVU102
 138:Library/src/lcm32f06x_adc.c ****   uint32_t ADCG;
 360              		.loc 1 138 3 view .LVU103
 139:Library/src/lcm32f06x_adc.c ****   uint32_t ADCV;
 361              		.loc 1 139 3 view .LVU104
 140:Library/src/lcm32f06x_adc.c ****   uint32_t AD_SELECT_DATA = 0;
 362              		.loc 1 140 3 view .LVU105
 141:Library/src/lcm32f06x_adc.c ****   tmpreg0 = ADCx->CFGR;
 363              		.loc 1 141 3 view .LVU106
 142:Library/src/lcm32f06x_adc.c ****   tmpreg1 = ADCx->SMPR;
 143:Library/src/lcm32f06x_adc.c **** 
 144:Library/src/lcm32f06x_adc.c ****   tmpreg0 &= 0x00000000;
 145:Library/src/lcm32f06x_adc.c ****   tmpreg1 &= 0x00000000;
 146:Library/src/lcm32f06x_adc.c ****   if(ADC_InitStruct->ADC_WorkMode == ADC_WorkMode_Stable)
 364              		.loc 1 146 5 is_stmt 0 view .LVU107
 365 0000 8022     		movs	r2, #128
 141:Library/src/lcm32f06x_adc.c ****   tmpreg0 = ADCx->CFGR;
 366              		.loc 1 141 11 view .LVU108
 367 0002 8369     		ldr	r3, [r0, #24]
 368              	.LVL9:
ARM GAS  /tmp/cclh89PE.s 			page 11


 142:Library/src/lcm32f06x_adc.c ****   tmpreg1 = ADCx->SMPR;
 369              		.loc 1 142 3 is_stmt 1 view .LVU109
 142:Library/src/lcm32f06x_adc.c ****   tmpreg1 = ADCx->SMPR;
 370              		.loc 1 142 11 is_stmt 0 view .LVU110
 371 0004 C369     		ldr	r3, [r0, #28]
 372              	.LVL10:
 144:Library/src/lcm32f06x_adc.c ****   tmpreg1 &= 0x00000000;
 373              		.loc 1 144 3 is_stmt 1 view .LVU111
 145:Library/src/lcm32f06x_adc.c ****   if(ADC_InitStruct->ADC_WorkMode == ADC_WorkMode_Stable)
 374              		.loc 1 145 3 view .LVU112
 375              		.loc 1 146 3 view .LVU113
 376              		.loc 1 146 20 is_stmt 0 view .LVU114
 377 0006 0B69     		ldr	r3, [r1, #16]
 134:Library/src/lcm32f06x_adc.c ****   uint32_t tmpreg0 = 0;
 378              		.loc 1 134 1 view .LVU115
 379 0008 F0B5     		push	{r4, r5, r6, r7, lr}
 380              	.LCFI1:
 381              		.cfi_def_cfa_offset 20
 382              		.cfi_offset 4, -20
 383              		.cfi_offset 5, -16
 384              		.cfi_offset 6, -12
 385              		.cfi_offset 7, -8
 386              		.cfi_offset 14, -4
 387              		.loc 1 146 5 view .LVU116
 388 000a 1203     		lsls	r2, r2, #12
 147:Library/src/lcm32f06x_adc.c ****   {
 148:Library/src/lcm32f06x_adc.c ****     if (ADC_InitStruct->ADC_ConvertTime >= 0xF)
 389              		.loc 1 148 23 view .LVU117
 390 000c 4E6A     		ldr	r6, [r1, #36]
 146:Library/src/lcm32f06x_adc.c ****   {
 391              		.loc 1 146 5 view .LVU118
 392 000e 9342     		cmp	r3, r2
 393 0010 35D0     		beq	.L22
 394              	.L38:
 149:Library/src/lcm32f06x_adc.c ****       ADC_InitStruct->ADC_ConvertTime = 0xF;
 150:Library/src/lcm32f06x_adc.c ****     else
 151:Library/src/lcm32f06x_adc.c ****       ADC_InitStruct->ADC_ConvertTime += 1;
 152:Library/src/lcm32f06x_adc.c ****   }
 153:Library/src/lcm32f06x_adc.c ****   tmpreg0 |= (uint32_t)(ADC_InitStruct->ADC_ClkMode | ADC_InitStruct->ADC_ReferenceVoltage | \
 154:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 155:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_WorkMode | ADC_InitStruct->ADC_OverFlowMode | \
 156:Library/src/lcm32f06x_adc.c ****                         (uint32_t)((ADC_InitStruct->ADC_LowPowerMode) << 16) | ADC_InitStruct->ADC_
 157:Library/src/lcm32f06x_adc.c **** 
 158:Library/src/lcm32f06x_adc.c **** 
 159:Library/src/lcm32f06x_adc.c ****   tmpreg1 |= (uint32_t)((ADC_InitStruct->ADC_AdjustTime) | ((ADC_InitStruct->ADC_TempPulseTime) << 
 160:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 395              		.loc 1 160 108 view .LVU119
 396 0012 3603     		lsls	r6, r6, #12
 397              	.L23:
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 398              		.loc 1 153 3 is_stmt 1 view .LVU120
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 399              		.loc 1 153 14 is_stmt 0 view .LVU121
 400 0014 0A68     		ldr	r2, [r1]
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 401              		.loc 1 153 69 view .LVU122
 402 0016 4D68     		ldr	r5, [r1, #4]
ARM GAS  /tmp/cclh89PE.s 			page 12


 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 403              		.loc 1 153 14 view .LVU123
 404 0018 1343     		orrs	r3, r2
 405 001a 8A68     		ldr	r2, [r1, #8]
 406 001c 2B43     		orrs	r3, r5
 407 001e 1343     		orrs	r3, r2
 408 0020 CA68     		ldr	r2, [r1, #12]
 156:Library/src/lcm32f06x_adc.c **** 
 409              		.loc 1 156 51 view .LVU124
 410 0022 0C7E     		ldrb	r4, [r1, #24]
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 411              		.loc 1 153 14 view .LVU125
 412 0024 1343     		orrs	r3, r2
 413 0026 4A69     		ldr	r2, [r1, #20]
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 414              		.loc 1 159 140 view .LVU126
 415 0028 CF6A     		ldr	r7, [r1, #44]
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 416              		.loc 1 153 14 view .LVU127
 417 002a 1343     		orrs	r3, r2
 418 002c CA69     		ldr	r2, [r1, #28]
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 419              		.loc 1 159 140 view .LVU128
 420 002e 3F01     		lsls	r7, r7, #4
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 421              		.loc 1 153 14 view .LVU129
 422 0030 1343     		orrs	r3, r2
 156:Library/src/lcm32f06x_adc.c **** 
 423              		.loc 1 156 25 view .LVU130
 424 0032 2204     		lsls	r2, r4, #16
 153:Library/src/lcm32f06x_adc.c ****                         ADC_InitStruct->ADC_VCCChanelMapping | ADC_InitStruct->ADC_TempChanelMappin
 425              		.loc 1 153 14 view .LVU131
 426 0034 1343     		orrs	r3, r2
 427              	.LVL11:
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 428              		.loc 1 159 3 is_stmt 1 view .LVU132
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 429              		.loc 1 159 97 is_stmt 0 view .LVU133
 430 0036 0A6A     		ldr	r2, [r1, #32]
 431 0038 1205     		lsls	r2, r2, #20
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 432              		.loc 1 159 104 view .LVU134
 433 003a 3A43     		orrs	r2, r7
 434 003c 0F6B     		ldr	r7, [r1, #48]
 435              		.loc 1 160 65 view .LVU135
 436 003e 896A     		ldr	r1, [r1, #40]
 437              	.LVL12:
 161:Library/src/lcm32f06x_adc.c **** 
 162:Library/src/lcm32f06x_adc.c ****   ADCx->CFGR = tmpreg0;
 438              		.loc 1 162 14 view .LVU136
 439 0040 8361     		str	r3, [r0, #24]
 163:Library/src/lcm32f06x_adc.c ****   ADCx->SMPR = tmpreg1;
 164:Library/src/lcm32f06x_adc.c ****   AD_SELECT_DATA = ADC_InitStruct->ADC_ReferenceVoltage;
 165:Library/src/lcm32f06x_adc.c **** 
 166:Library/src/lcm32f06x_adc.c ****   if (AD_SELECT_DATA==ADC_ReferenceVoltage_4V9)// VREF=4V9
 440              		.loc 1 166 6 view .LVU137
 441 0042 8023     		movs	r3, #128
ARM GAS  /tmp/cclh89PE.s 			page 13


 442              	.LVL13:
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 443              		.loc 1 159 104 view .LVU138
 444 0044 3A43     		orrs	r2, r7
 160:Library/src/lcm32f06x_adc.c **** 
 445              		.loc 1 160 65 view .LVU139
 446 0046 0902     		lsls	r1, r1, #8
 159:Library/src/lcm32f06x_adc.c ****                         ((ADC_InitStruct->ADC_ConvertPulseTime) << 8) | ((ADC_InitStruct->ADC_Conve
 447              		.loc 1 159 146 view .LVU140
 448 0048 0A43     		orrs	r2, r1
 160:Library/src/lcm32f06x_adc.c **** 
 449              		.loc 1 160 71 view .LVU141
 450 004a 3243     		orrs	r2, r6
 451              	.LVL14:
 162:Library/src/lcm32f06x_adc.c ****   ADCx->SMPR = tmpreg1;
 452              		.loc 1 162 3 is_stmt 1 view .LVU142
 163:Library/src/lcm32f06x_adc.c ****   AD_SELECT_DATA = ADC_InitStruct->ADC_ReferenceVoltage;
 453              		.loc 1 163 3 view .LVU143
 163:Library/src/lcm32f06x_adc.c ****   AD_SELECT_DATA = ADC_InitStruct->ADC_ReferenceVoltage;
 454              		.loc 1 163 14 is_stmt 0 view .LVU144
 455 004c C261     		str	r2, [r0, #28]
 456              	.LVL15:
 164:Library/src/lcm32f06x_adc.c **** 
 457              		.loc 1 164 3 is_stmt 1 view .LVU145
 458              		.loc 1 166 3 view .LVU146
 459              		.loc 1 166 6 is_stmt 0 view .LVU147
 460 004e 9B02     		lsls	r3, r3, #10
 461 0050 9D42     		cmp	r5, r3
 462 0052 22D0     		beq	.L40
 167:Library/src/lcm32f06x_adc.c ****   {
 168:Library/src/lcm32f06x_adc.c ****     if (ADC_InitStruct->ADC_LowPowerMode == ENABLE)
 169:Library/src/lcm32f06x_adc.c ****     {
 170:Library/src/lcm32f06x_adc.c ****       AD_TRIM_temp = (*(volatile uint32_t *)(0x1FFFF7A8));
 171:Library/src/lcm32f06x_adc.c ****     }
 172:Library/src/lcm32f06x_adc.c ****     else
 173:Library/src/lcm32f06x_adc.c ****     {
 174:Library/src/lcm32f06x_adc.c ****       AD_TRIM_temp = (*(volatile uint32_t *)(0x1FFFF7A0));
 175:Library/src/lcm32f06x_adc.c ****     }
 176:Library/src/lcm32f06x_adc.c **** 
 177:Library/src/lcm32f06x_adc.c ****     if (AD_TRIM_temp == 0xffffffff)
 178:Library/src/lcm32f06x_adc.c ****     {
 179:Library/src/lcm32f06x_adc.c ****       ADCx->TRIM = 0x009700A3;
 180:Library/src/lcm32f06x_adc.c ****     }
 181:Library/src/lcm32f06x_adc.c ****     else
 182:Library/src/lcm32f06x_adc.c ****     {
 183:Library/src/lcm32f06x_adc.c ****         ADCx->TRIM = AD_TRIM_temp;
 184:Library/src/lcm32f06x_adc.c ****     }
 185:Library/src/lcm32f06x_adc.c ****   }
 186:Library/src/lcm32f06x_adc.c ****   else //VREF=3.2 / VDD
 187:Library/src/lcm32f06x_adc.c ****   {
 188:Library/src/lcm32f06x_adc.c ****     if (ADC_InitStruct->ADC_LowPowerMode == ENABLE)
 463              		.loc 1 188 5 is_stmt 1 view .LVU148
 464              		.loc 1 188 8 is_stmt 0 view .LVU149
 465 0054 012C     		cmp	r4, #1
 466 0056 19D0     		beq	.L41
 189:Library/src/lcm32f06x_adc.c ****     {
 190:Library/src/lcm32f06x_adc.c ****         AD_TRIM_temp = (*(volatile uint32_t *)(0x1FFFF7A4));
ARM GAS  /tmp/cclh89PE.s 			page 14


 191:Library/src/lcm32f06x_adc.c ****     }
 192:Library/src/lcm32f06x_adc.c ****     else
 193:Library/src/lcm32f06x_adc.c ****     {
 194:Library/src/lcm32f06x_adc.c ****         AD_TRIM_temp = (*(volatile uint32_t *)(0x1FFFF70C));     
 467              		.loc 1 194 9 is_stmt 1 view .LVU150
 468              		.loc 1 194 22 is_stmt 0 view .LVU151
 469 0058 174B     		ldr	r3, .L43
 470 005a 1B68     		ldr	r3, [r3]
 471              	.LVL16:
 195:Library/src/lcm32f06x_adc.c ****     }
 196:Library/src/lcm32f06x_adc.c **** 
 197:Library/src/lcm32f06x_adc.c ****     if (AD_TRIM_temp == 0xffffffff)
 472              		.loc 1 197 5 is_stmt 1 view .LVU152
 473              		.loc 1 197 8 is_stmt 0 view .LVU153
 474 005c 5A1C     		adds	r2, r3, #1
 475 005e 19D0     		beq	.L31
 476              	.LVL17:
 198:Library/src/lcm32f06x_adc.c ****     {
 199:Library/src/lcm32f06x_adc.c ****       ADCx->TRIM = 0x009700A3;
 200:Library/src/lcm32f06x_adc.c ****     }
 201:Library/src/lcm32f06x_adc.c ****     else
 202:Library/src/lcm32f06x_adc.c ****     {
 203:Library/src/lcm32f06x_adc.c ****       if (ADC_InitStruct->ADC_LowPowerMode == ENABLE)
 477              		.loc 1 203 7 is_stmt 1 view .LVU154
 204:Library/src/lcm32f06x_adc.c ****       {
 205:Library/src/lcm32f06x_adc.c ****         ADCx->TRIM = AD_TRIM_temp;
 206:Library/src/lcm32f06x_adc.c ****       }
 207:Library/src/lcm32f06x_adc.c ****       else
 208:Library/src/lcm32f06x_adc.c ****       {
 209:Library/src/lcm32f06x_adc.c ****         ADCG=((AD_TRIM_temp^0x005c0000)>>16)&0x000000ff;
 478              		.loc 1 209 9 view .LVU155
 210:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 479              		.loc 1 210 9 view .LVU156
 211:Library/src/lcm32f06x_adc.c ****         ADCx->TRIM =ADCG+ADCV;
 480              		.loc 1 211 9 view .LVU157
 209:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 481              		.loc 1 209 40 is_stmt 0 view .LVU158
 482 0060 5C22     		movs	r2, #92
 483 0062 190C     		lsrs	r1, r3, #16
 484 0064 5140     		eors	r1, r2
 209:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 485              		.loc 1 209 13 view .LVU159
 486 0066 A332     		adds	r2, r2, #163
 487 0068 0A40     		ands	r2, r1
 210:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 488              		.loc 1 210 41 view .LVU160
 489 006a D021     		movs	r1, #208
 490 006c 1B04     		lsls	r3, r3, #16
 491              	.LVL18:
 210:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 492              		.loc 1 210 41 view .LVU161
 493 006e C903     		lsls	r1, r1, #15
 494 0070 4B40     		eors	r3, r1
 210:Library/src/lcm32f06x_adc.c ****         ADCV=(( AD_TRIM_temp^0x00000068)<<16)&0x00ff0000;
 495              		.loc 1 210 13 view .LVU162
 496 0072 FF21     		movs	r1, #255
 497 0074 0904     		lsls	r1, r1, #16
ARM GAS  /tmp/cclh89PE.s 			page 15


 498 0076 0B40     		ands	r3, r1
 499              		.loc 1 211 25 view .LVU163
 500 0078 1343     		orrs	r3, r2
 501              	.LVL19:
 502              	.L39:
 503              		.loc 1 211 20 view .LVU164
 504 007a 0362     		str	r3, [r0, #32]
 505              	.LVL20:
 506              	.L21:
 212:Library/src/lcm32f06x_adc.c ****       }
 213:Library/src/lcm32f06x_adc.c ****     }
 214:Library/src/lcm32f06x_adc.c ****   }
 215:Library/src/lcm32f06x_adc.c **** }
 507              		.loc 1 215 1 view .LVU165
 508              		@ sp needed
 509              	.LVL21:
 510              		.loc 1 215 1 view .LVU166
 511 007c F0BD     		pop	{r4, r5, r6, r7, pc}
 512              	.LVL22:
 513              	.L22:
 148:Library/src/lcm32f06x_adc.c ****       ADC_InitStruct->ADC_ConvertTime = 0xF;
 514              		.loc 1 148 5 is_stmt 1 view .LVU167
 148:Library/src/lcm32f06x_adc.c ****       ADC_InitStruct->ADC_ConvertTime = 0xF;
 515              		.loc 1 148 8 is_stmt 0 view .LVU168
 516 007e 0E2E     		cmp	r6, #14
 517 0080 14D9     		bls	.L24
 149:Library/src/lcm32f06x_adc.c ****     else
 518              		.loc 1 149 7 is_stmt 1 view .LVU169
 149:Library/src/lcm32f06x_adc.c ****     else
 519              		.loc 1 149 39 is_stmt 0 view .LVU170
 520 0082 0F22     		movs	r2, #15
 521 0084 F026     		movs	r6, #240
 522 0086 4A62     		str	r2, [r1, #36]
 523 0088 3602     		lsls	r6, r6, #8
 524 008a C3E7     		b	.L23
 525              	.LVL23:
 526              	.L41:
 190:Library/src/lcm32f06x_adc.c ****     }
 527              		.loc 1 190 9 is_stmt 1 view .LVU171
 190:Library/src/lcm32f06x_adc.c ****     }
 528              		.loc 1 190 22 is_stmt 0 view .LVU172
 529 008c 0B4B     		ldr	r3, .L43+4
 530 008e 1B68     		ldr	r3, [r3]
 531              	.LVL24:
 197:Library/src/lcm32f06x_adc.c ****     {
 532              		.loc 1 197 5 is_stmt 1 view .LVU173
 197:Library/src/lcm32f06x_adc.c ****     {
 533              		.loc 1 197 8 is_stmt 0 view .LVU174
 534 0090 5A1C     		adds	r2, r3, #1
 535 0092 F2D1     		bne	.L39
 536              	.LVL25:
 537              	.L31:
 199:Library/src/lcm32f06x_adc.c ****     }
 538              		.loc 1 199 7 is_stmt 1 view .LVU175
 199:Library/src/lcm32f06x_adc.c ****     }
 539              		.loc 1 199 18 is_stmt 0 view .LVU176
 540 0094 0A4B     		ldr	r3, .L43+8
ARM GAS  /tmp/cclh89PE.s 			page 16


 541              	.LVL26:
 199:Library/src/lcm32f06x_adc.c ****     }
 542              		.loc 1 199 18 view .LVU177
 543 0096 0362     		str	r3, [r0, #32]
 544              	.LVL27:
 199:Library/src/lcm32f06x_adc.c ****     }
 545              		.loc 1 199 18 view .LVU178
 546 0098 F0E7     		b	.L21
 547              	.LVL28:
 548              	.L40:
 168:Library/src/lcm32f06x_adc.c ****     {
 549              		.loc 1 168 5 is_stmt 1 view .LVU179
 168:Library/src/lcm32f06x_adc.c ****     {
 550              		.loc 1 168 8 is_stmt 0 view .LVU180
 551 009a 012C     		cmp	r4, #1
 552 009c 09D0     		beq	.L42
 174:Library/src/lcm32f06x_adc.c ****     }
 553              		.loc 1 174 7 is_stmt 1 view .LVU181
 174:Library/src/lcm32f06x_adc.c ****     }
 554              		.loc 1 174 20 is_stmt 0 view .LVU182
 555 009e 094B     		ldr	r3, .L43+12
 556 00a0 1B68     		ldr	r3, [r3]
 557              	.LVL29:
 558              	.L27:
 177:Library/src/lcm32f06x_adc.c ****     {
 559              		.loc 1 177 5 is_stmt 1 view .LVU183
 177:Library/src/lcm32f06x_adc.c ****     {
 560              		.loc 1 177 8 is_stmt 0 view .LVU184
 561 00a2 5A1C     		adds	r2, r3, #1
 562 00a4 E9D1     		bne	.L39
 563              	.LVL30:
 199:Library/src/lcm32f06x_adc.c ****     }
 564              		.loc 1 199 7 is_stmt 1 view .LVU185
 199:Library/src/lcm32f06x_adc.c ****     }
 565              		.loc 1 199 18 is_stmt 0 view .LVU186
 566 00a6 064B     		ldr	r3, .L43+8
 567              	.LVL31:
 199:Library/src/lcm32f06x_adc.c ****     }
 568              		.loc 1 199 18 view .LVU187
 569 00a8 0362     		str	r3, [r0, #32]
 570              	.LVL32:
 199:Library/src/lcm32f06x_adc.c ****     }
 571              		.loc 1 199 18 view .LVU188
 572 00aa E7E7     		b	.L21
 573              	.LVL33:
 574              	.L24:
 151:Library/src/lcm32f06x_adc.c ****   }
 575              		.loc 1 151 7 is_stmt 1 view .LVU189
 151:Library/src/lcm32f06x_adc.c ****   }
 576              		.loc 1 151 39 is_stmt 0 view .LVU190
 577 00ac 0136     		adds	r6, r6, #1
 578 00ae 4E62     		str	r6, [r1, #36]
 579 00b0 AFE7     		b	.L38
 580              	.LVL34:
 581              	.L42:
 170:Library/src/lcm32f06x_adc.c ****     }
 582              		.loc 1 170 7 is_stmt 1 view .LVU191
ARM GAS  /tmp/cclh89PE.s 			page 17


 170:Library/src/lcm32f06x_adc.c ****     }
 583              		.loc 1 170 20 is_stmt 0 view .LVU192
 584 00b2 054B     		ldr	r3, .L43+16
 585 00b4 1B68     		ldr	r3, [r3]
 586              	.LVL35:
 170:Library/src/lcm32f06x_adc.c ****     }
 587              		.loc 1 170 20 view .LVU193
 588 00b6 F4E7     		b	.L27
 589              	.L44:
 590              		.align	2
 591              	.L43:
 592 00b8 0CF7FF1F 		.word	536868620
 593 00bc A4F7FF1F 		.word	536868772
 594 00c0 A3009700 		.word	9896099
 595 00c4 A0F7FF1F 		.word	536868768
 596 00c8 A8F7FF1F 		.word	536868776
 597              		.cfi_endproc
 598              	.LFE48:
 600              		.section	.text.ADC_ExternTrigger_Config,"ax",%progbits
 601              		.align	1
 602              		.p2align 2,,3
 603              		.global	ADC_ExternTrigger_Config
 604              		.syntax unified
 605              		.code	16
 606              		.thumb_func
 608              	ADC_ExternTrigger_Config:
 609              	.LVL36:
 610              	.LFB49:
 216:Library/src/lcm32f06x_adc.c **** 
 217:Library/src/lcm32f06x_adc.c **** /**
 218:Library/src/lcm32f06x_adc.c ****   * @name   ADC_ExternTrigger_Config
 219:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Configure the delay time for external triggering of X.
 220:Library/src/lcm32f06x_adc.c ****   *         CN: ??????????X????????
 221:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 222:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 223:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 224:Library/src/lcm32f06x_adc.c ****   * @param  ExternTigger: 
 225:Library/src/lcm32f06x_adc.c ****   *         EN: Select an external trigger x.
 226:Library/src/lcm32f06x_adc.c ****   *         CN: ????????? x??
 227:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ExternTrigeer0
 228:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ExternTrigeer1
 229:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ExternTrigeer2
 230:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ExternTrigeer3
 231:Library/src/lcm32f06x_adc.c ****   * @param  Delay: 
 232:Library/src/lcm32f06x_adc.c ****   *         EN: Delay time.
 233:Library/src/lcm32f06x_adc.c ****   *         CN: ??????
 234:Library/src/lcm32f06x_adc.c ****   * @retval None
 235:Library/src/lcm32f06x_adc.c ****   */
 236:Library/src/lcm32f06x_adc.c **** void ADC_ExternTrigger_Config (ADC_TypeDef *ADCx, uint8_t ExternTigger, uint8_t Delay)
 237:Library/src/lcm32f06x_adc.c **** {
 611              		.loc 1 237 1 is_stmt 1 view -0
 612              		.cfi_startproc
 613              		@ args = 0, pretend = 0, frame = 0
 614              		@ frame_needed = 0, uses_anonymous_args = 0
 615              		@ link register save eliminated.
 238:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_EXTERNT_TRIGGER(ExternTigger));
 616              		.loc 1 238 3 view .LVU195
ARM GAS  /tmp/cclh89PE.s 			page 18


 239:Library/src/lcm32f06x_adc.c ****   uint32_t Temp = 0;
 617              		.loc 1 239 3 view .LVU196
 240:Library/src/lcm32f06x_adc.c ****   if(ExternTigger == ADC_ExternTrigeer0)
 618              		.loc 1 240 3 view .LVU197
 619              		.loc 1 240 5 is_stmt 0 view .LVU198
 620 0000 0029     		cmp	r1, #0
 621 0002 05D1     		bne	.L46
 241:Library/src/lcm32f06x_adc.c ****   {
 242:Library/src/lcm32f06x_adc.c ****     Temp = ADCx->EXTCFGR0 & (~ADC_EXTCFGR0_DLY0_Msk);
 622              		.loc 1 242 5 is_stmt 1 view .LVU199
 623              		.loc 1 242 16 is_stmt 0 view .LVU200
 624 0004 036E     		ldr	r3, [r0, #96]
 625              		.loc 1 242 10 view .LVU201
 626 0006 FF31     		adds	r1, r1, #255
 627              	.LVL37:
 628              		.loc 1 242 10 view .LVU202
 629 0008 8B43     		bics	r3, r1
 630              	.LVL38:
 243:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY0_Pos;
 631              		.loc 1 243 5 is_stmt 1 view .LVU203
 632              		.loc 1 243 10 is_stmt 0 view .LVU204
 633 000a 1343     		orrs	r3, r2
 634              	.LVL39:
 635              	.L47:
 244:Library/src/lcm32f06x_adc.c ****   }
 245:Library/src/lcm32f06x_adc.c ****   else if (ExternTigger == ADC_ExternTrigeer1)
 246:Library/src/lcm32f06x_adc.c ****   {
 247:Library/src/lcm32f06x_adc.c ****     Temp = ADCx->EXTCFGR0 & (~ADC_EXTCFGR0_DLY1_Msk);
 248:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY1_Pos;
 249:Library/src/lcm32f06x_adc.c ****   }
 250:Library/src/lcm32f06x_adc.c ****   else if (ExternTigger == ADC_ExternTrigeer2)
 251:Library/src/lcm32f06x_adc.c ****   {
 252:Library/src/lcm32f06x_adc.c ****     Temp = ADCx->EXTCFGR0 & (~ADC_EXTCFGR0_DLY2_Msk);
 253:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY2_Pos;
 254:Library/src/lcm32f06x_adc.c ****   }
 255:Library/src/lcm32f06x_adc.c ****   else if (ExternTigger == ADC_ExternTrigeer3)
 256:Library/src/lcm32f06x_adc.c ****   {
 257:Library/src/lcm32f06x_adc.c ****     Temp = ADCx->EXTCFGR0 & (~ADC_EXTCFGR0_DLY3_Msk);
 258:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY3_Pos;
 259:Library/src/lcm32f06x_adc.c ****   }
 260:Library/src/lcm32f06x_adc.c ****   ADCx->EXTCFGR0 = Temp;
 636              		.loc 1 260 3 is_stmt 1 view .LVU205
 637              		.loc 1 260 18 is_stmt 0 view .LVU206
 638 000c 0366     		str	r3, [r0, #96]
 261:Library/src/lcm32f06x_adc.c **** }
 639              		.loc 1 261 1 view .LVU207
 640              		@ sp needed
 641 000e 7047     		bx	lr
 642              	.LVL40:
 643              	.L46:
 245:Library/src/lcm32f06x_adc.c ****   {
 644              		.loc 1 245 8 is_stmt 1 view .LVU208
 245:Library/src/lcm32f06x_adc.c ****   {
 645              		.loc 1 245 11 is_stmt 0 view .LVU209
 646 0010 0129     		cmp	r1, #1
 647 0012 0AD0     		beq	.L51
 250:Library/src/lcm32f06x_adc.c ****   {
ARM GAS  /tmp/cclh89PE.s 			page 19


 648              		.loc 1 250 8 is_stmt 1 view .LVU210
 250:Library/src/lcm32f06x_adc.c ****   {
 649              		.loc 1 250 11 is_stmt 0 view .LVU211
 650 0014 0229     		cmp	r1, #2
 651 0016 0ED0     		beq	.L52
 255:Library/src/lcm32f06x_adc.c ****   {
 652              		.loc 1 255 8 is_stmt 1 view .LVU212
 239:Library/src/lcm32f06x_adc.c ****   if(ExternTigger == ADC_ExternTrigeer0)
 653              		.loc 1 239 12 is_stmt 0 view .LVU213
 654 0018 0023     		movs	r3, #0
 255:Library/src/lcm32f06x_adc.c ****   {
 655              		.loc 1 255 11 view .LVU214
 656 001a 0329     		cmp	r1, #3
 657 001c F6D1     		bne	.L47
 257:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY3_Pos;
 658              		.loc 1 257 5 is_stmt 1 view .LVU215
 257:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY3_Pos;
 659              		.loc 1 257 16 is_stmt 0 view .LVU216
 660 001e 016E     		ldr	r1, [r0, #96]
 661              	.LVL41:
 258:Library/src/lcm32f06x_adc.c ****   }
 662              		.loc 1 258 19 view .LVU217
 663 0020 1306     		lsls	r3, r2, #24
 257:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY3_Pos;
 664              		.loc 1 257 10 view .LVU218
 665 0022 0902     		lsls	r1, r1, #8
 666 0024 090A     		lsrs	r1, r1, #8
 667              	.LVL42:
 258:Library/src/lcm32f06x_adc.c ****   }
 668              		.loc 1 258 5 is_stmt 1 view .LVU219
 258:Library/src/lcm32f06x_adc.c ****   }
 669              		.loc 1 258 10 is_stmt 0 view .LVU220
 670 0026 0B43     		orrs	r3, r1
 671 0028 F0E7     		b	.L47
 672              	.LVL43:
 673              	.L51:
 247:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY1_Pos;
 674              		.loc 1 247 5 is_stmt 1 view .LVU221
 247:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY1_Pos;
 675              		.loc 1 247 10 is_stmt 0 view .LVU222
 676 002a 064B     		ldr	r3, .L53
 247:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY1_Pos;
 677              		.loc 1 247 16 view .LVU223
 678 002c 016E     		ldr	r1, [r0, #96]
 679              	.LVL44:
 247:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY1_Pos;
 680              		.loc 1 247 10 view .LVU224
 681 002e 1940     		ands	r1, r3
 682              	.LVL45:
 248:Library/src/lcm32f06x_adc.c ****   }
 683              		.loc 1 248 5 is_stmt 1 view .LVU225
 248:Library/src/lcm32f06x_adc.c ****   }
 684              		.loc 1 248 19 is_stmt 0 view .LVU226
 685 0030 1302     		lsls	r3, r2, #8
 248:Library/src/lcm32f06x_adc.c ****   }
 686              		.loc 1 248 10 view .LVU227
 687 0032 0B43     		orrs	r3, r1
ARM GAS  /tmp/cclh89PE.s 			page 20


 688              	.LVL46:
 248:Library/src/lcm32f06x_adc.c ****   }
 689              		.loc 1 248 10 view .LVU228
 690 0034 EAE7     		b	.L47
 691              	.LVL47:
 692              	.L52:
 252:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY2_Pos;
 693              		.loc 1 252 5 is_stmt 1 view .LVU229
 252:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY2_Pos;
 694              		.loc 1 252 10 is_stmt 0 view .LVU230
 695 0036 044B     		ldr	r3, .L53+4
 252:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY2_Pos;
 696              		.loc 1 252 16 view .LVU231
 697 0038 016E     		ldr	r1, [r0, #96]
 698              	.LVL48:
 252:Library/src/lcm32f06x_adc.c ****     Temp |= Delay << ADC_EXTCFGR0_DLY2_Pos;
 699              		.loc 1 252 10 view .LVU232
 700 003a 1940     		ands	r1, r3
 701              	.LVL49:
 253:Library/src/lcm32f06x_adc.c ****   }
 702              		.loc 1 253 5 is_stmt 1 view .LVU233
 253:Library/src/lcm32f06x_adc.c ****   }
 703              		.loc 1 253 19 is_stmt 0 view .LVU234
 704 003c 1304     		lsls	r3, r2, #16
 253:Library/src/lcm32f06x_adc.c ****   }
 705              		.loc 1 253 10 view .LVU235
 706 003e 0B43     		orrs	r3, r1
 707              	.LVL50:
 253:Library/src/lcm32f06x_adc.c ****   }
 708              		.loc 1 253 10 view .LVU236
 709 0040 E4E7     		b	.L47
 710              	.L54:
 711 0042 C046     		.align	2
 712              	.L53:
 713 0044 FF00FFFF 		.word	-65281
 714 0048 FFFF00FF 		.word	-16711681
 715              		.cfi_endproc
 716              	.LFE49:
 718              		.section	.text.ADC_StopOfConversion,"ax",%progbits
 719              		.align	1
 720              		.p2align 2,,3
 721              		.global	ADC_StopOfConversion
 722              		.syntax unified
 723              		.code	16
 724              		.thumb_func
 726              	ADC_StopOfConversion:
 727              	.LVL51:
 728              	.LFB50:
 262:Library/src/lcm32f06x_adc.c **** 
 263:Library/src/lcm32f06x_adc.c **** /**
 264:Library/src/lcm32f06x_adc.c ****   * @name   ADC_StopOfConversion
 265:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC stops current conversion.
 266:Library/src/lcm32f06x_adc.c ****   *         CN: ADC??????????
 267:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 268:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 269:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 270:Library/src/lcm32f06x_adc.c ****   * @retval None
ARM GAS  /tmp/cclh89PE.s 			page 21


 271:Library/src/lcm32f06x_adc.c ****   */
 272:Library/src/lcm32f06x_adc.c **** 
 273:Library/src/lcm32f06x_adc.c **** void ADC_StopOfConversion(ADC_TypeDef *ADCx)
 274:Library/src/lcm32f06x_adc.c **** {
 729              		.loc 1 274 1 is_stmt 1 view -0
 730              		.cfi_startproc
 731              		@ args = 0, pretend = 0, frame = 0
 732              		@ frame_needed = 0, uses_anonymous_args = 0
 733              		@ link register save eliminated.
 275:Library/src/lcm32f06x_adc.c ****   if (ADCx->CR & ADC_CR_START_Msk)
 734              		.loc 1 275 3 view .LVU238
 735              		.loc 1 275 11 is_stmt 0 view .LVU239
 736 0000 4369     		ldr	r3, [r0, #20]
 737              		.loc 1 275 6 view .LVU240
 738 0002 5B07     		lsls	r3, r3, #29
 739 0004 01D5     		bpl	.L56
 276:Library/src/lcm32f06x_adc.c ****   {
 277:Library/src/lcm32f06x_adc.c ****     ADCx->CR = (uint32_t)ADC_CR_STOP_Msk;
 740              		.loc 1 277 5 is_stmt 1 view .LVU241
 741              		.loc 1 277 14 is_stmt 0 view .LVU242
 742 0006 0823     		movs	r3, #8
 743 0008 4361     		str	r3, [r0, #20]
 744              	.L56:
 278:Library/src/lcm32f06x_adc.c ****   }
 279:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_STOP_Msk)  /* ????????????stop */
 745              		.loc 1 279 10 is_stmt 1 view .LVU243
 746              		.loc 1 279 14 is_stmt 0 view .LVU244
 747 000a 4369     		ldr	r3, [r0, #20]
 748              		.loc 1 279 10 view .LVU245
 749 000c 1B07     		lsls	r3, r3, #28
 750 000e 08D5     		bpl	.L55
 751              		.loc 1 279 19 view .LVU246
 752 0010 0822     		movs	r2, #8
 753              	.L58:
 280:Library/src/lcm32f06x_adc.c ****   {
 281:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 754              		.loc 1 281 7 is_stmt 1 view .LVU247
 755              		.syntax divided
 756              	@ 281 "Library/src/lcm32f06x_adc.c" 1
 757 0012 C046     		nop
 758              	@ 0 "" 2
 759              		.loc 1 281 16 view .LVU248
 760              	@ 281 "Library/src/lcm32f06x_adc.c" 1
 761 0014 C046     		nop
 762              	@ 0 "" 2
 763              		.loc 1 281 25 view .LVU249
 764              	@ 281 "Library/src/lcm32f06x_adc.c" 1
 765 0016 C046     		nop
 766              	@ 0 "" 2
 767              		.loc 1 281 34 view .LVU250
 768              	@ 281 "Library/src/lcm32f06x_adc.c" 1
 769 0018 C046     		nop
 770              	@ 0 "" 2
 771              		.loc 1 281 43 view .LVU251
 772              	@ 281 "Library/src/lcm32f06x_adc.c" 1
 773 001a C046     		nop
 774              	@ 0 "" 2
ARM GAS  /tmp/cclh89PE.s 			page 22


 279:Library/src/lcm32f06x_adc.c ****   {
 775              		.loc 1 279 10 view .LVU252
 279:Library/src/lcm32f06x_adc.c ****   {
 776              		.loc 1 279 14 is_stmt 0 view .LVU253
 777              		.thumb
 778              		.syntax unified
 779 001c 4369     		ldr	r3, [r0, #20]
 279:Library/src/lcm32f06x_adc.c ****   {
 780              		.loc 1 279 10 view .LVU254
 781 001e 1A42     		tst	r2, r3
 782 0020 F7D1     		bne	.L58
 783              	.L55:
 282:Library/src/lcm32f06x_adc.c ****   };
 283:Library/src/lcm32f06x_adc.c **** }
 784              		.loc 1 283 1 view .LVU255
 785              		@ sp needed
 786 0022 7047     		bx	lr
 787              		.cfi_endproc
 788              	.LFE50:
 790              		.section	.text.ADC_StartOfConversion,"ax",%progbits
 791              		.align	1
 792              		.p2align 2,,3
 793              		.global	ADC_StartOfConversion
 794              		.syntax unified
 795              		.code	16
 796              		.thumb_func
 798              	ADC_StartOfConversion:
 799              	.LVL52:
 800              	.LFB51:
 284:Library/src/lcm32f06x_adc.c **** 
 285:Library/src/lcm32f06x_adc.c **** /**
 286:Library/src/lcm32f06x_adc.c ****   * @name   ADC_StartOfConversion
 287:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC begins conversion.
 288:Library/src/lcm32f06x_adc.c ****   *         CN: ADC????????
 289:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 290:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 291:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 292:Library/src/lcm32f06x_adc.c ****   * @retval None
 293:Library/src/lcm32f06x_adc.c ****   */
 294:Library/src/lcm32f06x_adc.c **** void ADC_StartOfConversion(ADC_TypeDef *ADCx)
 295:Library/src/lcm32f06x_adc.c **** {
 801              		.loc 1 295 1 is_stmt 1 view -0
 802              		.cfi_startproc
 803              		@ args = 0, pretend = 0, frame = 0
 804              		@ frame_needed = 0, uses_anonymous_args = 0
 296:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->SR & ADC_SR_READY_Msk))
 805              		.loc 1 296 3 view .LVU257
 806              		.loc 1 296 10 view .LVU258
 807              		.loc 1 296 16 is_stmt 0 view .LVU259
 808 0000 0368     		ldr	r3, [r0]
 295:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->SR & ADC_SR_READY_Msk))
 809              		.loc 1 295 1 view .LVU260
 810 0002 70B5     		push	{r4, r5, r6, lr}
 811              	.LCFI2:
 812              		.cfi_def_cfa_offset 16
 813              		.cfi_offset 4, -16
 814              		.cfi_offset 5, -12
ARM GAS  /tmp/cclh89PE.s 			page 23


 815              		.cfi_offset 6, -8
 816              		.cfi_offset 14, -4
 295:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->SR & ADC_SR_READY_Msk))
 817              		.loc 1 295 1 view .LVU261
 818 0004 0400     		movs	r4, r0
 819              		.loc 1 296 10 view .LVU262
 820 0006 DB07     		lsls	r3, r3, #31
 821 0008 08D4     		bmi	.L69
 822              		.loc 1 296 21 view .LVU263
 823 000a 0122     		movs	r2, #1
 824              	.L70:
 297:Library/src/lcm32f06x_adc.c ****   {
 298:Library/src/lcm32f06x_adc.c ****     __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 825              		.loc 1 298 5 is_stmt 1 view .LVU264
 826              		.syntax divided
 827              	@ 298 "Library/src/lcm32f06x_adc.c" 1
 828 000c C046     		nop
 829              	@ 0 "" 2
 830              		.loc 1 298 14 view .LVU265
 831              	@ 298 "Library/src/lcm32f06x_adc.c" 1
 832 000e C046     		nop
 833              	@ 0 "" 2
 834              		.loc 1 298 23 view .LVU266
 835              	@ 298 "Library/src/lcm32f06x_adc.c" 1
 836 0010 C046     		nop
 837              	@ 0 "" 2
 838              		.loc 1 298 32 view .LVU267
 839              	@ 298 "Library/src/lcm32f06x_adc.c" 1
 840 0012 C046     		nop
 841              	@ 0 "" 2
 842              		.loc 1 298 41 view .LVU268
 843              	@ 298 "Library/src/lcm32f06x_adc.c" 1
 844 0014 C046     		nop
 845              	@ 0 "" 2
 296:Library/src/lcm32f06x_adc.c ****   {
 846              		.loc 1 296 10 view .LVU269
 296:Library/src/lcm32f06x_adc.c ****   {
 847              		.loc 1 296 16 is_stmt 0 view .LVU270
 848              		.thumb
 849              		.syntax unified
 850 0016 2368     		ldr	r3, [r4]
 296:Library/src/lcm32f06x_adc.c ****   {
 851              		.loc 1 296 10 view .LVU271
 852 0018 1A42     		tst	r2, r3
 853 001a F7D0     		beq	.L70
 854              	.L69:
 299:Library/src/lcm32f06x_adc.c ****   };
 855              		.loc 1 299 4 is_stmt 1 view .LVU272
 300:Library/src/lcm32f06x_adc.c ****   ADCx->CR = (uint32_t)ADC_CR_START_Msk; // ADSTART
 856              		.loc 1 300 3 view .LVU273
 857              		.loc 1 300 12 is_stmt 0 view .LVU274
 858 001c 0425     		movs	r5, #4
 301:Library/src/lcm32f06x_adc.c ****   delay10us(1);
 859              		.loc 1 301 3 view .LVU275
 860 001e 0120     		movs	r0, #1
 861              	.LVL53:
 300:Library/src/lcm32f06x_adc.c ****   ADCx->CR = (uint32_t)ADC_CR_START_Msk; // ADSTART
ARM GAS  /tmp/cclh89PE.s 			page 24


 862              		.loc 1 300 12 view .LVU276
 863 0020 6561     		str	r5, [r4, #20]
 864              		.loc 1 301 3 is_stmt 1 view .LVU277
 865 0022 FFF7FEFF 		bl	delay10us
 866              	.LVL54:
 302:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->CR & ADC_CR_START_Msk))
 867              		.loc 1 302 3 view .LVU278
 868              		.loc 1 302 10 view .LVU279
 869              		.loc 1 302 16 is_stmt 0 view .LVU280
 870 0026 6369     		ldr	r3, [r4, #20]
 871              		.loc 1 302 10 view .LVU281
 872 0028 1D42     		tst	r5, r3
 873 002a 08D1     		bne	.L68
 874              		.loc 1 302 21 view .LVU282
 875 002c 0422     		movs	r2, #4
 876              	.L72:
 303:Library/src/lcm32f06x_adc.c ****   {
 304:Library/src/lcm32f06x_adc.c ****     __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 877              		.loc 1 304 5 is_stmt 1 view .LVU283
 878              		.syntax divided
 879              	@ 304 "Library/src/lcm32f06x_adc.c" 1
 880 002e C046     		nop
 881              	@ 0 "" 2
 882              		.loc 1 304 14 view .LVU284
 883              	@ 304 "Library/src/lcm32f06x_adc.c" 1
 884 0030 C046     		nop
 885              	@ 0 "" 2
 886              		.loc 1 304 23 view .LVU285
 887              	@ 304 "Library/src/lcm32f06x_adc.c" 1
 888 0032 C046     		nop
 889              	@ 0 "" 2
 890              		.loc 1 304 32 view .LVU286
 891              	@ 304 "Library/src/lcm32f06x_adc.c" 1
 892 0034 C046     		nop
 893              	@ 0 "" 2
 894              		.loc 1 304 41 view .LVU287
 895              	@ 304 "Library/src/lcm32f06x_adc.c" 1
 896 0036 C046     		nop
 897              	@ 0 "" 2
 302:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->CR & ADC_CR_START_Msk))
 898              		.loc 1 302 10 view .LVU288
 302:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->CR & ADC_CR_START_Msk))
 899              		.loc 1 302 16 is_stmt 0 view .LVU289
 900              		.thumb
 901              		.syntax unified
 902 0038 6369     		ldr	r3, [r4, #20]
 302:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->CR & ADC_CR_START_Msk))
 903              		.loc 1 302 10 view .LVU290
 904 003a 1A42     		tst	r2, r3
 905 003c F7D0     		beq	.L72
 906              	.L68:
 305:Library/src/lcm32f06x_adc.c ****   }
 306:Library/src/lcm32f06x_adc.c **** }
 907              		.loc 1 306 1 view .LVU291
 908              		@ sp needed
 909              	.LVL55:
 910              		.loc 1 306 1 view .LVU292
ARM GAS  /tmp/cclh89PE.s 			page 25


 911 003e 70BD     		pop	{r4, r5, r6, pc}
 912              		.cfi_endproc
 913              	.LFE51:
 915              		.section	.text.ADC_CloseAdc,"ax",%progbits
 916              		.align	1
 917              		.p2align 2,,3
 918              		.global	ADC_CloseAdc
 919              		.syntax unified
 920              		.code	16
 921              		.thumb_func
 923              	ADC_CloseAdc:
 924              	.LVL56:
 925              	.LFB52:
 307:Library/src/lcm32f06x_adc.c **** 
 308:Library/src/lcm32f06x_adc.c **** /**
 309:Library/src/lcm32f06x_adc.c ****   * @name   ADC_CloseAdc
 310:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Stop or shut down the ADC module.
 311:Library/src/lcm32f06x_adc.c ****   *         CN: ?????? ADC??î•
 312:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 313:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 314:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 315:Library/src/lcm32f06x_adc.c ****   * @retval None
 316:Library/src/lcm32f06x_adc.c ****   */
 317:Library/src/lcm32f06x_adc.c **** void ADC_CloseAdc(ADC_TypeDef *ADCx)
 318:Library/src/lcm32f06x_adc.c **** {
 926              		.loc 1 318 1 is_stmt 1 view -0
 927              		.cfi_startproc
 928              		@ args = 0, pretend = 0, frame = 0
 929              		@ frame_needed = 0, uses_anonymous_args = 0
 930              		@ link register save eliminated.
 319:Library/src/lcm32f06x_adc.c ****   if (ADCx->CR & ADC_CR_START_Msk)
 931              		.loc 1 319 3 view .LVU294
 932              		.loc 1 319 11 is_stmt 0 view .LVU295
 933 0000 4369     		ldr	r3, [r0, #20]
 934              		.loc 1 319 6 view .LVU296
 935 0002 5B07     		lsls	r3, r3, #29
 936 0004 01D5     		bpl	.L79
 320:Library/src/lcm32f06x_adc.c ****   {
 321:Library/src/lcm32f06x_adc.c ****     ADCx->CR = ADC_CR_STOP_Msk;
 937              		.loc 1 321 5 is_stmt 1 view .LVU297
 938              		.loc 1 321 14 is_stmt 0 view .LVU298
 939 0006 0823     		movs	r3, #8
 940 0008 4361     		str	r3, [r0, #20]
 941              	.L79:
 322:Library/src/lcm32f06x_adc.c ****   }
 323:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_STOP_Msk)
 942              		.loc 1 323 10 is_stmt 1 view .LVU299
 943              		.loc 1 323 14 is_stmt 0 view .LVU300
 944 000a 4369     		ldr	r3, [r0, #20]
 945              		.loc 1 323 10 view .LVU301
 946 000c 1B07     		lsls	r3, r3, #28
 947 000e 08D5     		bpl	.L80
 948              		.loc 1 323 19 view .LVU302
 949 0010 0822     		movs	r2, #8
 950              	.L81:
 324:Library/src/lcm32f06x_adc.c ****   {
 325:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
ARM GAS  /tmp/cclh89PE.s 			page 26


 951              		.loc 1 325 7 is_stmt 1 view .LVU303
 952              		.syntax divided
 953              	@ 325 "Library/src/lcm32f06x_adc.c" 1
 954 0012 C046     		nop
 955              	@ 0 "" 2
 956              		.loc 1 325 16 view .LVU304
 957              	@ 325 "Library/src/lcm32f06x_adc.c" 1
 958 0014 C046     		nop
 959              	@ 0 "" 2
 960              		.loc 1 325 25 view .LVU305
 961              	@ 325 "Library/src/lcm32f06x_adc.c" 1
 962 0016 C046     		nop
 963              	@ 0 "" 2
 964              		.loc 1 325 34 view .LVU306
 965              	@ 325 "Library/src/lcm32f06x_adc.c" 1
 966 0018 C046     		nop
 967              	@ 0 "" 2
 968              		.loc 1 325 43 view .LVU307
 969              	@ 325 "Library/src/lcm32f06x_adc.c" 1
 970 001a C046     		nop
 971              	@ 0 "" 2
 323:Library/src/lcm32f06x_adc.c ****   {
 972              		.loc 1 323 10 view .LVU308
 323:Library/src/lcm32f06x_adc.c ****   {
 973              		.loc 1 323 14 is_stmt 0 view .LVU309
 974              		.thumb
 975              		.syntax unified
 976 001c 4369     		ldr	r3, [r0, #20]
 323:Library/src/lcm32f06x_adc.c ****   {
 977              		.loc 1 323 10 view .LVU310
 978 001e 1A42     		tst	r2, r3
 979 0020 F7D1     		bne	.L81
 980              	.L80:
 326:Library/src/lcm32f06x_adc.c ****   };
 981              		.loc 1 326 4 is_stmt 1 view .LVU311
 327:Library/src/lcm32f06x_adc.c ****   ADCx->CR = ADC_CR_DIS_Msk;
 982              		.loc 1 327 3 view .LVU312
 983              		.loc 1 327 12 is_stmt 0 view .LVU313
 984 0022 0223     		movs	r3, #2
 985 0024 4361     		str	r3, [r0, #20]
 328:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_EN_Msk)
 986              		.loc 1 328 3 is_stmt 1 view .LVU314
 987              		.loc 1 328 10 view .LVU315
 988              		.loc 1 328 14 is_stmt 0 view .LVU316
 989 0026 4369     		ldr	r3, [r0, #20]
 990              		.loc 1 328 10 view .LVU317
 991 0028 DB07     		lsls	r3, r3, #31
 992 002a 08D5     		bpl	.L78
 993              		.loc 1 328 19 view .LVU318
 994 002c 0122     		movs	r2, #1
 995              	.L83:
 329:Library/src/lcm32f06x_adc.c ****   {
 330:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 996              		.loc 1 330 7 is_stmt 1 view .LVU319
 997              		.syntax divided
 998              	@ 330 "Library/src/lcm32f06x_adc.c" 1
 999 002e C046     		nop
ARM GAS  /tmp/cclh89PE.s 			page 27


 1000              	@ 0 "" 2
 1001              		.loc 1 330 16 view .LVU320
 1002              	@ 330 "Library/src/lcm32f06x_adc.c" 1
 1003 0030 C046     		nop
 1004              	@ 0 "" 2
 1005              		.loc 1 330 25 view .LVU321
 1006              	@ 330 "Library/src/lcm32f06x_adc.c" 1
 1007 0032 C046     		nop
 1008              	@ 0 "" 2
 1009              		.loc 1 330 34 view .LVU322
 1010              	@ 330 "Library/src/lcm32f06x_adc.c" 1
 1011 0034 C046     		nop
 1012              	@ 0 "" 2
 1013              		.loc 1 330 43 view .LVU323
 1014              	@ 330 "Library/src/lcm32f06x_adc.c" 1
 1015 0036 C046     		nop
 1016              	@ 0 "" 2
 328:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_EN_Msk)
 1017              		.loc 1 328 10 view .LVU324
 328:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_EN_Msk)
 1018              		.loc 1 328 14 is_stmt 0 view .LVU325
 1019              		.thumb
 1020              		.syntax unified
 1021 0038 4369     		ldr	r3, [r0, #20]
 328:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_EN_Msk)
 1022              		.loc 1 328 10 view .LVU326
 1023 003a 1A42     		tst	r2, r3
 1024 003c F7D1     		bne	.L83
 1025              	.L78:
 331:Library/src/lcm32f06x_adc.c ****   };
 332:Library/src/lcm32f06x_adc.c **** }
 1026              		.loc 1 332 1 view .LVU327
 1027              		@ sp needed
 1028 003e 7047     		bx	lr
 1029              		.cfi_endproc
 1030              	.LFE52:
 1032              		.section	.text.ADC_GetConversionValue,"ax",%progbits
 1033              		.align	1
 1034              		.p2align 2,,3
 1035              		.global	ADC_GetConversionValue
 1036              		.syntax unified
 1037              		.code	16
 1038              		.thumb_func
 1040              	ADC_GetConversionValue:
 1041              	.LVL57:
 1042              	.LFB53:
 333:Library/src/lcm32f06x_adc.c **** 
 334:Library/src/lcm32f06x_adc.c **** /**
 335:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetConversionValue
 336:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Obtain ADC SOC conversion value.
 337:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC SOC??????
 338:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 339:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 340:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 341:Library/src/lcm32f06x_adc.c ****   * @param  SOCx:
 342:Library/src/lcm32f06x_adc.c ****   *         EN: where x can be from 0 to 15 to select the SOC channel
 343:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?????? 0 ?? 15 ????? SOC ?????
ARM GAS  /tmp/cclh89PE.s 			page 28


 344:Library/src/lcm32f06x_adc.c ****   * @retval uint16_t
 345:Library/src/lcm32f06x_adc.c ****   */
 346:Library/src/lcm32f06x_adc.c **** uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx ,uint32_t SOCx)
 347:Library/src/lcm32f06x_adc.c **** {
 1043              		.loc 1 347 1 is_stmt 1 view -0
 1044              		.cfi_startproc
 1045              		@ args = 0, pretend = 0, frame = 0
 1046              		@ frame_needed = 0, uses_anonymous_args = 0
 1047              		@ link register save eliminated.
 348:Library/src/lcm32f06x_adc.c **** 
 349:Library/src/lcm32f06x_adc.c ****   while (!(ADCx->SOCISR & (1 << SOCx)))
 1048              		.loc 1 349 3 view .LVU329
 1049              		.loc 1 349 10 view .LVU330
 1050              		.loc 1 349 30 is_stmt 0 view .LVU331
 1051 0000 0122     		movs	r2, #1
 1052 0002 8A40     		lsls	r2, r2, r1
 1053              		.loc 1 349 16 view .LVU332
 1054 0004 C368     		ldr	r3, [r0, #12]
 1055              		.loc 1 349 10 view .LVU333
 1056 0006 1A42     		tst	r2, r3
 1057 0008 07D1     		bne	.L99
 1058              	.L100:
 350:Library/src/lcm32f06x_adc.c ****   {
 351:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 1059              		.loc 1 351 7 is_stmt 1 view .LVU334
 1060              		.syntax divided
 1061              	@ 351 "Library/src/lcm32f06x_adc.c" 1
 1062 000a C046     		nop
 1063              	@ 0 "" 2
 1064              		.loc 1 351 16 view .LVU335
 1065              	@ 351 "Library/src/lcm32f06x_adc.c" 1
 1066 000c C046     		nop
 1067              	@ 0 "" 2
 1068              		.loc 1 351 25 view .LVU336
 1069              	@ 351 "Library/src/lcm32f06x_adc.c" 1
 1070 000e C046     		nop
 1071              	@ 0 "" 2
 1072              		.loc 1 351 34 view .LVU337
 1073              	@ 351 "Library/src/lcm32f06x_adc.c" 1
 1074 0010 C046     		nop
 1075              	@ 0 "" 2
 1076              		.loc 1 351 43 view .LVU338
 1077              	@ 351 "Library/src/lcm32f06x_adc.c" 1
 1078 0012 C046     		nop
 1079              	@ 0 "" 2
 349:Library/src/lcm32f06x_adc.c ****   {
 1080              		.loc 1 349 10 view .LVU339
 349:Library/src/lcm32f06x_adc.c ****   {
 1081              		.loc 1 349 16 is_stmt 0 view .LVU340
 1082              		.thumb
 1083              		.syntax unified
 1084 0014 C368     		ldr	r3, [r0, #12]
 349:Library/src/lcm32f06x_adc.c ****   {
 1085              		.loc 1 349 10 view .LVU341
 1086 0016 1A42     		tst	r2, r3
 1087 0018 F7D0     		beq	.L100
 1088              	.L99:
ARM GAS  /tmp/cclh89PE.s 			page 29


 352:Library/src/lcm32f06x_adc.c ****   };
 1089              		.loc 1 352 4 is_stmt 1 view .LVU342
 353:Library/src/lcm32f06x_adc.c ****   return (uint16_t)(DR(SOCx));
 1090              		.loc 1 353 3 view .LVU343
 354:Library/src/lcm32f06x_adc.c **** }
 1091              		.loc 1 354 1 is_stmt 0 view .LVU344
 1092              		@ sp needed
 353:Library/src/lcm32f06x_adc.c ****   return (uint16_t)(DR(SOCx));
 1093              		.loc 1 353 21 view .LVU345
 1094 001a 034B     		ldr	r3, .L103
 1095 001c 8900     		lsls	r1, r1, #2
 1096              	.LVL58:
 353:Library/src/lcm32f06x_adc.c ****   return (uint16_t)(DR(SOCx));
 1097              		.loc 1 353 21 view .LVU346
 1098 001e 9C46     		mov	ip, r3
 1099 0020 6144     		add	r1, r1, ip
 353:Library/src/lcm32f06x_adc.c ****   return (uint16_t)(DR(SOCx));
 1100              		.loc 1 353 10 discriminator 1 view .LVU347
 1101 0022 0888     		ldrh	r0, [r1]
 1102              	.LVL59:
 1103              		.loc 1 354 1 view .LVU348
 1104 0024 7047     		bx	lr
 1105              	.L104:
 1106 0026 C046     		.align	2
 1107              	.L103:
 1108 0028 C0A00140 		.word	1073848512
 1109              		.cfi_endproc
 1110              	.LFE53:
 1112              		.section	.text.ADC_GetDMAValue,"ax",%progbits
 1113              		.align	1
 1114              		.p2align 2,,3
 1115              		.global	ADC_GetDMAValue
 1116              		.syntax unified
 1117              		.code	16
 1118              		.thumb_func
 1120              	ADC_GetDMAValue:
 1121              	.LVL60:
 1122              	.LFB54:
 355:Library/src/lcm32f06x_adc.c **** 
 356:Library/src/lcm32f06x_adc.c **** /**
 357:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetDMAValue
 358:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Obtain ADC DMA conversion value.
 359:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC DMA ??????
 360:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 361:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 362:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 363:Library/src/lcm32f06x_adc.c ****   * @retval uint16_t
 364:Library/src/lcm32f06x_adc.c ****   */
 365:Library/src/lcm32f06x_adc.c **** uint16_t ADC_GetDMAValue(ADC_TypeDef *ADCx )
 366:Library/src/lcm32f06x_adc.c **** {
 1123              		.loc 1 366 1 is_stmt 1 view -0
 1124              		.cfi_startproc
 1125              		@ args = 0, pretend = 0, frame = 0
 1126              		@ frame_needed = 0, uses_anonymous_args = 0
 1127              		@ link register save eliminated.
 367:Library/src/lcm32f06x_adc.c ****   return (uint16_t)ADCx->DADDR;
 1128              		.loc 1 367 3 view .LVU350
ARM GAS  /tmp/cclh89PE.s 			page 30


 1129              		.loc 1 367 24 is_stmt 0 view .LVU351
 1130 0000 C06A     		ldr	r0, [r0, #44]
 1131              	.LVL61:
 368:Library/src/lcm32f06x_adc.c **** }
 1132              		.loc 1 368 1 view .LVU352
 1133              		@ sp needed
 367:Library/src/lcm32f06x_adc.c ****   return (uint16_t)ADCx->DADDR;
 1134              		.loc 1 367 10 discriminator 1 view .LVU353
 1135 0002 80B2     		uxth	r0, r0
 1136              		.loc 1 368 1 view .LVU354
 1137 0004 7047     		bx	lr
 1138              		.cfi_endproc
 1139              	.LFE54:
 1141 0006 C046     		.section	.text.ADC_SOC_Config_New,"ax",%progbits
 1142              		.align	1
 1143              		.p2align 2,,3
 1144              		.global	ADC_SOC_Config_New
 1145              		.syntax unified
 1146              		.code	16
 1147              		.thumb_func
 1149              	ADC_SOC_Config_New:
 1150              	.LVL62:
 1151              	.LFB55:
 369:Library/src/lcm32f06x_adc.c **** 
 370:Library/src/lcm32f06x_adc.c **** /**
 371:Library/src/lcm32f06x_adc.c ****   * @name   ADC_SOC_Config
 372:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC SOC configuration.
 373:Library/src/lcm32f06x_adc.c ****   *         CN: ADC SOC???¨¢?
 374:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 375:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 376:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 377:Library/src/lcm32f06x_adc.c ****   * @param  SOCx:
 378:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to 15 to select the SOCx.
 379:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ?? 15 ????? ADC ???ÒÂ
 380:Library/src/lcm32f06x_adc.c ****   * @param  TriggerSource:
 381:Library/src/lcm32f06x_adc.c ****   *         EN: Specify trigger source selection.
 382:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????
 383:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect0
 384:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect1
 385:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect2
 386:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect3
 387:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelectNone
 388:Library/src/lcm32f06x_adc.c ****   * @param  ADCIN:
 389:Library/src/lcm32f06x_adc.c ****   *         EN: Specify external ADIN selection.
 390:Library/src/lcm32f06x_adc.c ****   *         CN: ?????ADIN???
 391:Library/src/lcm32f06x_adc.c ****   * @param  SOC_SAMP:
 392:Library/src/lcm32f06x_adc.c ****   *         EN: Specify sampling mode.
 393:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????
 394:Library/src/lcm32f06x_adc.c ****   *             @arg SOC_SAMP_SINGLE
 395:Library/src/lcm32f06x_adc.c ****   *             @arg SOC_SAMP_DOUBLE
 396:Library/src/lcm32f06x_adc.c ****   * @retval uint16_t
 397:Library/src/lcm32f06x_adc.c ****   */
 398:Library/src/lcm32f06x_adc.c **** void ADC_SOC_Config_New(ADC_TypeDef *ADCx, uint32_t SOCx, uint32_t TriggerSource, uint32_t ADCIN, u
 399:Library/src/lcm32f06x_adc.c **** {
 1152              		.loc 1 399 1 is_stmt 1 view -0
 1153              		.cfi_startproc
 1154              		@ args = 4, pretend = 0, frame = 0
ARM GAS  /tmp/cclh89PE.s 			page 31


 1155              		@ frame_needed = 0, uses_anonymous_args = 0
 1156              		@ link register save eliminated.
 400:Library/src/lcm32f06x_adc.c ****   if (SOCx <= SOC15) {
 1157              		.loc 1 400 3 view .LVU356
 1158              		.loc 1 400 6 is_stmt 0 view .LVU357
 1159 0000 0F29     		cmp	r1, #15
 1160 0002 06D8     		bhi	.L106
 401:Library/src/lcm32f06x_adc.c ****     ADCSOC(ADCx, SOCx) = (TriggerSource | ADCIN | SOC_SAMP);
 1161              		.loc 1 401 5 is_stmt 1 view .LVU358
 1162              		.loc 1 401 24 is_stmt 0 view .LVU359
 1163 0004 8900     		lsls	r1, r1, #2
 1164              	.LVL63:
 1165              		.loc 1 401 24 view .LVU360
 1166 0006 4018     		adds	r0, r0, r1
 1167              	.LVL64:
 1168              		.loc 1 401 49 view .LVU361
 1169 0008 0099     		ldr	r1, [sp]
 1170              		.loc 1 401 24 view .LVU362
 1171 000a 8030     		adds	r0, r0, #128
 1172              		.loc 1 401 49 view .LVU363
 1173 000c 0B43     		orrs	r3, r1
 1174              	.LVL65:
 1175              		.loc 1 401 49 view .LVU364
 1176 000e 1343     		orrs	r3, r2
 1177              		.loc 1 401 24 view .LVU365
 1178 0010 0360     		str	r3, [r0]
 1179              	.L106:
 402:Library/src/lcm32f06x_adc.c ****   }
 403:Library/src/lcm32f06x_adc.c **** }
 1180              		.loc 1 403 1 view .LVU366
 1181              		@ sp needed
 1182 0012 7047     		bx	lr
 1183              		.cfi_endproc
 1184              	.LFE55:
 1186              		.section	.text.ADC_SOC_Config,"ax",%progbits
 1187              		.align	1
 1188              		.p2align 2,,3
 1189              		.global	ADC_SOC_Config
 1190              		.syntax unified
 1191              		.code	16
 1192              		.thumb_func
 1194              	ADC_SOC_Config:
 1195              	.LVL66:
 1196              	.LFB56:
 404:Library/src/lcm32f06x_adc.c **** void ADC_SOC_Config(ADC_TypeDef *ADCx, uint32_t SOCx, uint32_t TriggerSource ,uint32_t ADCIN, uint3
 405:Library/src/lcm32f06x_adc.c **** {
 1197              		.loc 1 405 1 is_stmt 1 view -0
 1198              		.cfi_startproc
 1199              		@ args = 4, pretend = 0, frame = 0
 1200              		@ frame_needed = 0, uses_anonymous_args = 0
 406:Library/src/lcm32f06x_adc.c ****   if(SOCx == SOC0)
 1201              		.loc 1 406 3 view .LVU368
 405:Library/src/lcm32f06x_adc.c ****   if(SOCx == SOC0)
 1202              		.loc 1 405 1 is_stmt 0 view .LVU369
 1203 0000 10B5     		push	{r4, lr}
 1204              	.LCFI3:
 1205              		.cfi_def_cfa_offset 8
ARM GAS  /tmp/cclh89PE.s 			page 32


 1206              		.cfi_offset 4, -8
 1207              		.cfi_offset 14, -4
 1208 0002 0F29     		cmp	r1, #15
 1209 0004 08D8     		bhi	.L108
 1210 0006 324C     		ldr	r4, .L127
 1211 0008 8900     		lsls	r1, r1, #2
 1212              	.LVL67:
 405:Library/src/lcm32f06x_adc.c ****   if(SOCx == SOC0)
 1213              		.loc 1 405 1 view .LVU370
 1214 000a 6158     		ldr	r1, [r4, r1]
 1215 000c 8F46     		mov	pc, r1
 1216              		.section	.rodata.ADC_SOC_Config,"a",%progbits
 1217              		.align	2
 1218              	.L111:
 1219 0000 26000000 		.word	.L126
 1220 0004 32000000 		.word	.L125
 1221 0008 3E000000 		.word	.L124
 1222 000c 4A000000 		.word	.L123
 1223 0010 56000000 		.word	.L122
 1224 0014 62000000 		.word	.L121
 1225 0018 6E000000 		.word	.L120
 1226 001c 7A000000 		.word	.L119
 1227 0020 86000000 		.word	.L118
 1228 0024 92000000 		.word	.L117
 1229 0028 9E000000 		.word	.L116
 1230 002c AA000000 		.word	.L115
 1231 0030 B6000000 		.word	.L114
 1232 0034 C2000000 		.word	.L113
 1233 0038 1A000000 		.word	.L112
 1234 003c 0E000000 		.word	.L110
 1235              		.section	.text.ADC_SOC_Config
 1236              	.L110:
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 408:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC1)
 409:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC1 = (TriggerSource|ADCIN|SOC_SAMP);
 410:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 411:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC2 = (TriggerSource|ADCIN|SOC_SAMP);
 412:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 413:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC3 = (TriggerSource|ADCIN|SOC_SAMP);
 414:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 415:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC4 = (TriggerSource|ADCIN|SOC_SAMP);
 416:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 417:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC5 = (TriggerSource|ADCIN|SOC_SAMP);
 418:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 419:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC6 = (TriggerSource|ADCIN|SOC_SAMP);
 420:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 421:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC7 = (TriggerSource|ADCIN|SOC_SAMP);
 422:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 423:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC8 = (TriggerSource|ADCIN|SOC_SAMP);
 424:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 425:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC9 = (TriggerSource|ADCIN|SOC_SAMP);
 426:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 427:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC10 = (TriggerSource|ADCIN|SOC_SAMP);
 428:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 429:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC11 = (TriggerSource|ADCIN|SOC_SAMP);
 430:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 431:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC12 = (TriggerSource|ADCIN|SOC_SAMP);
ARM GAS  /tmp/cclh89PE.s 			page 33


 432:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 433:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC13 = (TriggerSource|ADCIN|SOC_SAMP);
 434:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 435:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC14 = (TriggerSource|ADCIN|SOC_SAMP);
 436:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 437:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC15 = (TriggerSource|ADCIN|SOC_SAMP);
 1237              		.loc 1 437 5 is_stmt 1 view .LVU371
 1238              		.loc 1 437 42 is_stmt 0 view .LVU372
 1239 000e 0299     		ldr	r1, [sp, #8]
 1240 0010 0B43     		orrs	r3, r1
 1241              	.LVL68:
 1242              		.loc 1 437 42 view .LVU373
 1243 0012 1343     		orrs	r3, r2
 1244              		.loc 1 437 20 view .LVU374
 1245 0014 BC22     		movs	r2, #188
 1246              	.LVL69:
 1247              		.loc 1 437 20 view .LVU375
 1248 0016 8350     		str	r3, [r0, r2]
 1249              	.LVL70:
 1250              	.L108:
 438:Library/src/lcm32f06x_adc.c **** }
 1251              		.loc 1 438 1 view .LVU376
 1252              		@ sp needed
 1253 0018 10BD     		pop	{r4, pc}
 1254              	.LVL71:
 1255              	.L112:
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1256              		.loc 1 435 5 is_stmt 1 view .LVU377
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1257              		.loc 1 435 42 is_stmt 0 view .LVU378
 1258 001a 0299     		ldr	r1, [sp, #8]
 1259 001c 0B43     		orrs	r3, r1
 1260              	.LVL72:
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1261              		.loc 1 435 42 view .LVU379
 1262 001e 1343     		orrs	r3, r2
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1263              		.loc 1 435 20 view .LVU380
 1264 0020 B822     		movs	r2, #184
 1265              	.LVL73:
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1266              		.loc 1 435 20 view .LVU381
 1267 0022 8350     		str	r3, [r0, r2]
 1268              	.LVL74:
 435:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC15)
 1269              		.loc 1 435 20 view .LVU382
 1270 0024 F8E7     		b	.L108
 1271              	.LVL75:
 1272              	.L126:
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 1273              		.loc 1 407 5 is_stmt 1 view .LVU383
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 1274              		.loc 1 407 41 is_stmt 0 view .LVU384
 1275 0026 0299     		ldr	r1, [sp, #8]
 1276 0028 0B43     		orrs	r3, r1
 1277              	.LVL76:
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
ARM GAS  /tmp/cclh89PE.s 			page 34


 1278              		.loc 1 407 41 view .LVU385
 1279 002a 1343     		orrs	r3, r2
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 1280              		.loc 1 407 19 view .LVU386
 1281 002c 8022     		movs	r2, #128
 1282              	.LVL77:
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 1283              		.loc 1 407 19 view .LVU387
 1284 002e 8350     		str	r3, [r0, r2]
 1285              	.LVL78:
 407:Library/src/lcm32f06x_adc.c ****     ADCx->ADCSOC0 = (TriggerSource|ADCIN|SOC_SAMP);
 1286              		.loc 1 407 19 view .LVU388
 1287 0030 F2E7     		b	.L108
 1288              	.LVL79:
 1289              	.L125:
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1290              		.loc 1 409 5 is_stmt 1 view .LVU389
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1291              		.loc 1 409 41 is_stmt 0 view .LVU390
 1292 0032 0299     		ldr	r1, [sp, #8]
 1293 0034 0B43     		orrs	r3, r1
 1294              	.LVL80:
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1295              		.loc 1 409 41 view .LVU391
 1296 0036 1343     		orrs	r3, r2
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1297              		.loc 1 409 19 view .LVU392
 1298 0038 8422     		movs	r2, #132
 1299              	.LVL81:
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1300              		.loc 1 409 19 view .LVU393
 1301 003a 8350     		str	r3, [r0, r2]
 1302              	.LVL82:
 409:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC2)
 1303              		.loc 1 409 19 view .LVU394
 1304 003c ECE7     		b	.L108
 1305              	.LVL83:
 1306              	.L124:
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 1307              		.loc 1 411 5 is_stmt 1 view .LVU395
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 1308              		.loc 1 411 41 is_stmt 0 view .LVU396
 1309 003e 0299     		ldr	r1, [sp, #8]
 1310 0040 0B43     		orrs	r3, r1
 1311              	.LVL84:
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 1312              		.loc 1 411 41 view .LVU397
 1313 0042 1343     		orrs	r3, r2
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 1314              		.loc 1 411 19 view .LVU398
 1315 0044 8822     		movs	r2, #136
 1316              	.LVL85:
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
 1317              		.loc 1 411 19 view .LVU399
 1318 0046 8350     		str	r3, [r0, r2]
 1319              	.LVL86:
 411:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC3)
ARM GAS  /tmp/cclh89PE.s 			page 35


 1320              		.loc 1 411 19 view .LVU400
 1321 0048 E6E7     		b	.L108
 1322              	.LVL87:
 1323              	.L123:
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1324              		.loc 1 413 5 is_stmt 1 view .LVU401
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1325              		.loc 1 413 41 is_stmt 0 view .LVU402
 1326 004a 0299     		ldr	r1, [sp, #8]
 1327 004c 0B43     		orrs	r3, r1
 1328              	.LVL88:
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1329              		.loc 1 413 41 view .LVU403
 1330 004e 1343     		orrs	r3, r2
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1331              		.loc 1 413 19 view .LVU404
 1332 0050 8C22     		movs	r2, #140
 1333              	.LVL89:
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1334              		.loc 1 413 19 view .LVU405
 1335 0052 8350     		str	r3, [r0, r2]
 1336              	.LVL90:
 413:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC4)
 1337              		.loc 1 413 19 view .LVU406
 1338 0054 E0E7     		b	.L108
 1339              	.LVL91:
 1340              	.L122:
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1341              		.loc 1 415 5 is_stmt 1 view .LVU407
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1342              		.loc 1 415 41 is_stmt 0 view .LVU408
 1343 0056 0299     		ldr	r1, [sp, #8]
 1344 0058 0B43     		orrs	r3, r1
 1345              	.LVL92:
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1346              		.loc 1 415 41 view .LVU409
 1347 005a 1343     		orrs	r3, r2
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1348              		.loc 1 415 19 view .LVU410
 1349 005c 9022     		movs	r2, #144
 1350              	.LVL93:
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1351              		.loc 1 415 19 view .LVU411
 1352 005e 8350     		str	r3, [r0, r2]
 1353              	.LVL94:
 415:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC5)
 1354              		.loc 1 415 19 view .LVU412
 1355 0060 DAE7     		b	.L108
 1356              	.LVL95:
 1357              	.L121:
 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1358              		.loc 1 417 5 is_stmt 1 view .LVU413
 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1359              		.loc 1 417 41 is_stmt 0 view .LVU414
 1360 0062 0299     		ldr	r1, [sp, #8]
 1361 0064 0B43     		orrs	r3, r1
 1362              	.LVL96:
ARM GAS  /tmp/cclh89PE.s 			page 36


 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1363              		.loc 1 417 41 view .LVU415
 1364 0066 1343     		orrs	r3, r2
 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1365              		.loc 1 417 19 view .LVU416
 1366 0068 9422     		movs	r2, #148
 1367              	.LVL97:
 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1368              		.loc 1 417 19 view .LVU417
 1369 006a 8350     		str	r3, [r0, r2]
 1370              	.LVL98:
 417:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC6)
 1371              		.loc 1 417 19 view .LVU418
 1372 006c D4E7     		b	.L108
 1373              	.LVL99:
 1374              	.L120:
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1375              		.loc 1 419 5 is_stmt 1 view .LVU419
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1376              		.loc 1 419 41 is_stmt 0 view .LVU420
 1377 006e 0299     		ldr	r1, [sp, #8]
 1378 0070 0B43     		orrs	r3, r1
 1379              	.LVL100:
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1380              		.loc 1 419 41 view .LVU421
 1381 0072 1343     		orrs	r3, r2
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1382              		.loc 1 419 19 view .LVU422
 1383 0074 9822     		movs	r2, #152
 1384              	.LVL101:
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1385              		.loc 1 419 19 view .LVU423
 1386 0076 8350     		str	r3, [r0, r2]
 1387              	.LVL102:
 419:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC7)
 1388              		.loc 1 419 19 view .LVU424
 1389 0078 CEE7     		b	.L108
 1390              	.LVL103:
 1391              	.L119:
 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1392              		.loc 1 421 5 is_stmt 1 view .LVU425
 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1393              		.loc 1 421 41 is_stmt 0 view .LVU426
 1394 007a 0299     		ldr	r1, [sp, #8]
 1395 007c 0B43     		orrs	r3, r1
 1396              	.LVL104:
 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1397              		.loc 1 421 41 view .LVU427
 1398 007e 1343     		orrs	r3, r2
 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1399              		.loc 1 421 19 view .LVU428
 1400 0080 9C22     		movs	r2, #156
 1401              	.LVL105:
 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1402              		.loc 1 421 19 view .LVU429
 1403 0082 8350     		str	r3, [r0, r2]
 1404              	.LVL106:
ARM GAS  /tmp/cclh89PE.s 			page 37


 421:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC8)
 1405              		.loc 1 421 19 view .LVU430
 1406 0084 C8E7     		b	.L108
 1407              	.LVL107:
 1408              	.L118:
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1409              		.loc 1 423 5 is_stmt 1 view .LVU431
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1410              		.loc 1 423 41 is_stmt 0 view .LVU432
 1411 0086 0299     		ldr	r1, [sp, #8]
 1412 0088 0B43     		orrs	r3, r1
 1413              	.LVL108:
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1414              		.loc 1 423 41 view .LVU433
 1415 008a 1343     		orrs	r3, r2
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1416              		.loc 1 423 19 view .LVU434
 1417 008c A022     		movs	r2, #160
 1418              	.LVL109:
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1419              		.loc 1 423 19 view .LVU435
 1420 008e 8350     		str	r3, [r0, r2]
 1421              	.LVL110:
 423:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC9)
 1422              		.loc 1 423 19 view .LVU436
 1423 0090 C2E7     		b	.L108
 1424              	.LVL111:
 1425              	.L117:
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1426              		.loc 1 425 5 is_stmt 1 view .LVU437
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1427              		.loc 1 425 41 is_stmt 0 view .LVU438
 1428 0092 0299     		ldr	r1, [sp, #8]
 1429 0094 0B43     		orrs	r3, r1
 1430              	.LVL112:
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1431              		.loc 1 425 41 view .LVU439
 1432 0096 1343     		orrs	r3, r2
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1433              		.loc 1 425 19 view .LVU440
 1434 0098 A422     		movs	r2, #164
 1435              	.LVL113:
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1436              		.loc 1 425 19 view .LVU441
 1437 009a 8350     		str	r3, [r0, r2]
 1438              	.LVL114:
 425:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC10)
 1439              		.loc 1 425 19 view .LVU442
 1440 009c BCE7     		b	.L108
 1441              	.LVL115:
 1442              	.L116:
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1443              		.loc 1 427 5 is_stmt 1 view .LVU443
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1444              		.loc 1 427 42 is_stmt 0 view .LVU444
 1445 009e 0299     		ldr	r1, [sp, #8]
 1446 00a0 0B43     		orrs	r3, r1
ARM GAS  /tmp/cclh89PE.s 			page 38


 1447              	.LVL116:
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1448              		.loc 1 427 42 view .LVU445
 1449 00a2 1343     		orrs	r3, r2
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1450              		.loc 1 427 20 view .LVU446
 1451 00a4 A822     		movs	r2, #168
 1452              	.LVL117:
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1453              		.loc 1 427 20 view .LVU447
 1454 00a6 8350     		str	r3, [r0, r2]
 1455              	.LVL118:
 427:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC11)
 1456              		.loc 1 427 20 view .LVU448
 1457 00a8 B6E7     		b	.L108
 1458              	.LVL119:
 1459              	.L115:
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1460              		.loc 1 429 5 is_stmt 1 view .LVU449
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1461              		.loc 1 429 42 is_stmt 0 view .LVU450
 1462 00aa 0299     		ldr	r1, [sp, #8]
 1463 00ac 0B43     		orrs	r3, r1
 1464              	.LVL120:
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1465              		.loc 1 429 42 view .LVU451
 1466 00ae 1343     		orrs	r3, r2
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1467              		.loc 1 429 20 view .LVU452
 1468 00b0 AC22     		movs	r2, #172
 1469              	.LVL121:
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1470              		.loc 1 429 20 view .LVU453
 1471 00b2 8350     		str	r3, [r0, r2]
 1472              	.LVL122:
 429:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC12)
 1473              		.loc 1 429 20 view .LVU454
 1474 00b4 B0E7     		b	.L108
 1475              	.LVL123:
 1476              	.L114:
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1477              		.loc 1 431 5 is_stmt 1 view .LVU455
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1478              		.loc 1 431 42 is_stmt 0 view .LVU456
 1479 00b6 0299     		ldr	r1, [sp, #8]
 1480 00b8 0B43     		orrs	r3, r1
 1481              	.LVL124:
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1482              		.loc 1 431 42 view .LVU457
 1483 00ba 1343     		orrs	r3, r2
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1484              		.loc 1 431 20 view .LVU458
 1485 00bc B022     		movs	r2, #176
 1486              	.LVL125:
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1487              		.loc 1 431 20 view .LVU459
 1488 00be 8350     		str	r3, [r0, r2]
ARM GAS  /tmp/cclh89PE.s 			page 39


 1489              	.LVL126:
 431:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC13)
 1490              		.loc 1 431 20 view .LVU460
 1491 00c0 AAE7     		b	.L108
 1492              	.LVL127:
 1493              	.L113:
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1494              		.loc 1 433 5 is_stmt 1 view .LVU461
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1495              		.loc 1 433 42 is_stmt 0 view .LVU462
 1496 00c2 0299     		ldr	r1, [sp, #8]
 1497 00c4 0B43     		orrs	r3, r1
 1498              	.LVL128:
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1499              		.loc 1 433 42 view .LVU463
 1500 00c6 1343     		orrs	r3, r2
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1501              		.loc 1 433 20 view .LVU464
 1502 00c8 B422     		movs	r2, #180
 1503              	.LVL129:
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1504              		.loc 1 433 20 view .LVU465
 1505 00ca 8350     		str	r3, [r0, r2]
 1506              	.LVL130:
 433:Library/src/lcm32f06x_adc.c ****   else if(SOCx == SOC14)
 1507              		.loc 1 433 20 view .LVU466
 1508 00cc A4E7     		b	.L108
 1509              	.L128:
 1510 00ce C046     		.align	2
 1511              	.L127:
 1512 00d0 00000000 		.word	.L111
 1513              		.cfi_endproc
 1514              	.LFE56:
 1516              		.section	.text.TrigSelect_Config,"ax",%progbits
 1517              		.align	1
 1518              		.p2align 2,,3
 1519              		.global	TrigSelect_Config
 1520              		.syntax unified
 1521              		.code	16
 1522              		.thumb_func
 1524              	TrigSelect_Config:
 1525              	.LVL131:
 1526              	.LFB57:
 439:Library/src/lcm32f06x_adc.c **** 
 440:Library/src/lcm32f06x_adc.c **** /**
 441:Library/src/lcm32f06x_adc.c ****   * @name   TrigSelect_Config
 442:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC SOC trigger source configuration.
 443:Library/src/lcm32f06x_adc.c ****   *         CN: ADC SOC????????¨¢?
 444:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 445:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 446:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 447:Library/src/lcm32f06x_adc.c ****   * @param  TriggerSelect:
 448:Library/src/lcm32f06x_adc.c ****   *         EN: Select hardware trigger source.
 449:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????
 450:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect0
 451:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect1
 452:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect2
ARM GAS  /tmp/cclh89PE.s 			page 40


 453:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect3
 454:Library/src/lcm32f06x_adc.c ****   * @param  AdcExtsel:
 455:Library/src/lcm32f06x_adc.c ****   *         EN: Trigger source selection.
 456:Library/src/lcm32f06x_adc.c ****   *         CN: ????????
 457:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect0_TIM1_TRIG_OC1...
 458:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect1_TIM1_TRIG_OC2...
 459:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect2_TIM1_TRIG_OC3...
 460:Library/src/lcm32f06x_adc.c ****   *             @arg TriggerSelect3_TIM1_TRIG_OC4...
 461:Library/src/lcm32f06x_adc.c ****   * @param  Triggermode:
 462:Library/src/lcm32f06x_adc.c ****   *         EN: Trigger mode selection.
 463:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????
 464:Library/src/lcm32f06x_adc.c ****   *             @arg Triggermode_rising
 465:Library/src/lcm32f06x_adc.c ****   *             @arg Triggermode_falling
 466:Library/src/lcm32f06x_adc.c ****   *             @arg Triggermode_rising_falling
 467:Library/src/lcm32f06x_adc.c ****   *             @arg Triggermode_Dis
 468:Library/src/lcm32f06x_adc.c ****   * @retval None
 469:Library/src/lcm32f06x_adc.c ****   */
 470:Library/src/lcm32f06x_adc.c **** void TrigSelect_Config(ADC_TypeDef *ADCx, uint32_t TriggerSelect ,uint32_t AdcExtsel, uint32_t Trig
 471:Library/src/lcm32f06x_adc.c **** {
 1527              		.loc 1 471 1 is_stmt 1 view -0
 1528              		.cfi_startproc
 1529              		@ args = 0, pretend = 0, frame = 0
 1530              		@ frame_needed = 0, uses_anonymous_args = 0
 472:Library/src/lcm32f06x_adc.c ****   if (TriggerSelect == TriggerSelect0)
 1531              		.loc 1 472 3 view .LVU468
 471:Library/src/lcm32f06x_adc.c ****   if (TriggerSelect == TriggerSelect0)
 1532              		.loc 1 471 1 is_stmt 0 view .LVU469
 1533 0000 10B5     		push	{r4, lr}
 1534              	.LCFI4:
 1535              		.cfi_def_cfa_offset 8
 1536              		.cfi_offset 4, -8
 1537              		.cfi_offset 14, -4
 471:Library/src/lcm32f06x_adc.c ****   if (TriggerSelect == TriggerSelect0)
 1538              		.loc 1 471 1 view .LVU470
 1539 0002 1400     		movs	r4, r2
 1540              		.loc 1 472 6 view .LVU471
 1541 0004 0029     		cmp	r1, #0
 1542 0006 13D1     		bne	.L130
 473:Library/src/lcm32f06x_adc.c ****   {
 474:Library/src/lcm32f06x_adc.c ****     sysctrl_access();
 1543              		.loc 1 474 5 is_stmt 1 view .LVU472
 1544              	.LBB34:
 1545              	.LBI34:
 1546              		.file 2 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
ARM GAS  /tmp/cclh89PE.s 			page 41


  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
ARM GAS  /tmp/cclh89PE.s 			page 42


  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
ARM GAS  /tmp/cclh89PE.s 			page 43


 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cclh89PE.s 			page 44


 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cclh89PE.s 			page 45


 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 1547              		.loc 2 258 27 view .LVU473
 1548              	.LBB35:
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 1549              		.loc 2 260 3 view .LVU474
 1550              		.syntax divided
 1551              	@ 260 "Core/cmsis_gcc.h" 1
 1552 0008 BFF36F8F 		isb 0xF
 1553              	@ 0 "" 2
 1554              		.thumb
 1555              		.syntax unified
 1556              	.LBE35:
 1557              	.LBE34:
 1558              		.loc 1 474 5 discriminator 1 view .LVU475
 1559              	.LBB36:
 1560              	.LBI36:
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cclh89PE.s 			page 46


 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
ARM GAS  /tmp/cclh89PE.s 			page 47


 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
ARM GAS  /tmp/cclh89PE.s 			page 48


 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/cclh89PE.s 			page 49


 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
ARM GAS  /tmp/cclh89PE.s 			page 50


 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cclh89PE.s 			page 51


 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
ARM GAS  /tmp/cclh89PE.s 			page 52


 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cclh89PE.s 			page 53


 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
ARM GAS  /tmp/cclh89PE.s 			page 54


 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
ARM GAS  /tmp/cclh89PE.s 			page 55


 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
ARM GAS  /tmp/cclh89PE.s 			page 56


 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
ARM GAS  /tmp/cclh89PE.s 			page 57


 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 963:Core/cmsis_gcc.h **** }
 964:Core/cmsis_gcc.h **** 
 965:Core/cmsis_gcc.h **** 
 966:Core/cmsis_gcc.h **** /**
 967:Core/cmsis_gcc.h ****   \brief   Get Control Register
 968:Core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
ARM GAS  /tmp/cclh89PE.s 			page 58


 969:Core/cmsis_gcc.h ****   \return               Control Register value
 970:Core/cmsis_gcc.h ****  */
 971:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 972:Core/cmsis_gcc.h **** {
 973:Core/cmsis_gcc.h ****   uint32_t result;
 974:Core/cmsis_gcc.h **** 
 975:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 976:Core/cmsis_gcc.h ****   return(result);
 977:Core/cmsis_gcc.h **** }
 978:Core/cmsis_gcc.h **** 
 979:Core/cmsis_gcc.h **** 
 980:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 981:Core/cmsis_gcc.h **** /**
 982:Core/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 983:Core/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 984:Core/cmsis_gcc.h ****   \return               non-secure Control Register value
 985:Core/cmsis_gcc.h ****  */
 986:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 987:Core/cmsis_gcc.h **** {
 988:Core/cmsis_gcc.h ****   uint32_t result;
 989:Core/cmsis_gcc.h **** 
 990:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 991:Core/cmsis_gcc.h ****   return(result);
 992:Core/cmsis_gcc.h **** }
 993:Core/cmsis_gcc.h **** #endif
 994:Core/cmsis_gcc.h **** 
 995:Core/cmsis_gcc.h **** 
 996:Core/cmsis_gcc.h **** /**
 997:Core/cmsis_gcc.h ****   \brief   Set Control Register
 998:Core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 999:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1000:Core/cmsis_gcc.h ****  */
1001:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1002:Core/cmsis_gcc.h **** {
1003:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1004:Core/cmsis_gcc.h ****   __ISB();
1005:Core/cmsis_gcc.h **** }
1006:Core/cmsis_gcc.h **** 
1007:Core/cmsis_gcc.h **** 
1008:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1009:Core/cmsis_gcc.h **** /**
1010:Core/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
1011:Core/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
1012:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1013:Core/cmsis_gcc.h ****  */
1014:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1015:Core/cmsis_gcc.h **** {
1016:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1017:Core/cmsis_gcc.h ****   __ISB();
1018:Core/cmsis_gcc.h **** }
1019:Core/cmsis_gcc.h **** #endif
1020:Core/cmsis_gcc.h **** 
1021:Core/cmsis_gcc.h **** 
1022:Core/cmsis_gcc.h **** /**
1023:Core/cmsis_gcc.h ****   \brief   Get IPSR Register
1024:Core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
1025:Core/cmsis_gcc.h ****   \return               IPSR Register value
ARM GAS  /tmp/cclh89PE.s 			page 59


1026:Core/cmsis_gcc.h ****  */
1027:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1028:Core/cmsis_gcc.h **** {
1029:Core/cmsis_gcc.h ****   uint32_t result;
1030:Core/cmsis_gcc.h **** 
1031:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1032:Core/cmsis_gcc.h ****   return(result);
1033:Core/cmsis_gcc.h **** }
1034:Core/cmsis_gcc.h **** 
1035:Core/cmsis_gcc.h **** 
1036:Core/cmsis_gcc.h **** /**
1037:Core/cmsis_gcc.h ****   \brief   Get APSR Register
1038:Core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
1039:Core/cmsis_gcc.h ****   \return               APSR Register value
1040:Core/cmsis_gcc.h ****  */
1041:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1042:Core/cmsis_gcc.h **** {
1043:Core/cmsis_gcc.h ****   uint32_t result;
1044:Core/cmsis_gcc.h **** 
1045:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1046:Core/cmsis_gcc.h ****   return(result);
1047:Core/cmsis_gcc.h **** }
1048:Core/cmsis_gcc.h **** 
1049:Core/cmsis_gcc.h **** 
1050:Core/cmsis_gcc.h **** /**
1051:Core/cmsis_gcc.h ****   \brief   Get xPSR Register
1052:Core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
1053:Core/cmsis_gcc.h ****   \return               xPSR Register value
1054:Core/cmsis_gcc.h ****  */
1055:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1056:Core/cmsis_gcc.h **** {
1057:Core/cmsis_gcc.h ****   uint32_t result;
1058:Core/cmsis_gcc.h **** 
1059:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1060:Core/cmsis_gcc.h ****   return(result);
1061:Core/cmsis_gcc.h **** }
1062:Core/cmsis_gcc.h **** 
1063:Core/cmsis_gcc.h **** 
1064:Core/cmsis_gcc.h **** /**
1065:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
1066:Core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
1067:Core/cmsis_gcc.h ****   \return               PSP Register value
1068:Core/cmsis_gcc.h ****  */
1069:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1070:Core/cmsis_gcc.h **** {
1071:Core/cmsis_gcc.h ****   uint32_t result;
1072:Core/cmsis_gcc.h **** 
1073:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
1074:Core/cmsis_gcc.h ****   return(result);
1075:Core/cmsis_gcc.h **** }
1076:Core/cmsis_gcc.h **** 
1077:Core/cmsis_gcc.h **** 
1078:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1079:Core/cmsis_gcc.h **** /**
1080:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
1081:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
1082:Core/cmsis_gcc.h ****   \return               PSP Register value
ARM GAS  /tmp/cclh89PE.s 			page 60


1083:Core/cmsis_gcc.h ****  */
1084:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1085:Core/cmsis_gcc.h **** {
1086:Core/cmsis_gcc.h ****   uint32_t result;
1087:Core/cmsis_gcc.h **** 
1088:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
1089:Core/cmsis_gcc.h ****   return(result);
1090:Core/cmsis_gcc.h **** }
1091:Core/cmsis_gcc.h **** #endif
1092:Core/cmsis_gcc.h **** 
1093:Core/cmsis_gcc.h **** 
1094:Core/cmsis_gcc.h **** /**
1095:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
1096:Core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
1097:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1098:Core/cmsis_gcc.h ****  */
1099:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1100:Core/cmsis_gcc.h **** {
1101:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1102:Core/cmsis_gcc.h **** }
1103:Core/cmsis_gcc.h **** 
1104:Core/cmsis_gcc.h **** 
1105:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1106:Core/cmsis_gcc.h **** /**
1107:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
1108:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
1109:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1110:Core/cmsis_gcc.h ****  */
1111:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1112:Core/cmsis_gcc.h **** {
1113:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1114:Core/cmsis_gcc.h **** }
1115:Core/cmsis_gcc.h **** #endif
1116:Core/cmsis_gcc.h **** 
1117:Core/cmsis_gcc.h **** 
1118:Core/cmsis_gcc.h **** /**
1119:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
1120:Core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
1121:Core/cmsis_gcc.h ****   \return               MSP Register value
1122:Core/cmsis_gcc.h ****  */
1123:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1124:Core/cmsis_gcc.h **** {
1125:Core/cmsis_gcc.h ****   uint32_t result;
1126:Core/cmsis_gcc.h **** 
1127:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
1128:Core/cmsis_gcc.h ****   return(result);
1129:Core/cmsis_gcc.h **** }
1130:Core/cmsis_gcc.h **** 
1131:Core/cmsis_gcc.h **** 
1132:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1133:Core/cmsis_gcc.h **** /**
1134:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
1135:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
1136:Core/cmsis_gcc.h ****   \return               MSP Register value
1137:Core/cmsis_gcc.h ****  */
1138:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1139:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/cclh89PE.s 			page 61


1140:Core/cmsis_gcc.h ****   uint32_t result;
1141:Core/cmsis_gcc.h **** 
1142:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1143:Core/cmsis_gcc.h ****   return(result);
1144:Core/cmsis_gcc.h **** }
1145:Core/cmsis_gcc.h **** #endif
1146:Core/cmsis_gcc.h **** 
1147:Core/cmsis_gcc.h **** 
1148:Core/cmsis_gcc.h **** /**
1149:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
1150:Core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
1151:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1152:Core/cmsis_gcc.h ****  */
1153:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1154:Core/cmsis_gcc.h **** {
1155:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1156:Core/cmsis_gcc.h **** }
1157:Core/cmsis_gcc.h **** 
1158:Core/cmsis_gcc.h **** 
1159:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1160:Core/cmsis_gcc.h **** /**
1161:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
1162:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1163:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1164:Core/cmsis_gcc.h ****  */
1165:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1166:Core/cmsis_gcc.h **** {
1167:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1168:Core/cmsis_gcc.h **** }
1169:Core/cmsis_gcc.h **** #endif
1170:Core/cmsis_gcc.h **** 
1171:Core/cmsis_gcc.h **** 
1172:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1173:Core/cmsis_gcc.h **** /**
1174:Core/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
1175:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1176:Core/cmsis_gcc.h ****   \return               SP Register value
1177:Core/cmsis_gcc.h ****  */
1178:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1179:Core/cmsis_gcc.h **** {
1180:Core/cmsis_gcc.h ****   uint32_t result;
1181:Core/cmsis_gcc.h **** 
1182:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1183:Core/cmsis_gcc.h ****   return(result);
1184:Core/cmsis_gcc.h **** }
1185:Core/cmsis_gcc.h **** 
1186:Core/cmsis_gcc.h **** 
1187:Core/cmsis_gcc.h **** /**
1188:Core/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
1189:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1190:Core/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
1191:Core/cmsis_gcc.h ****  */
1192:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1193:Core/cmsis_gcc.h **** {
1194:Core/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1195:Core/cmsis_gcc.h **** }
1196:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cclh89PE.s 			page 62


1197:Core/cmsis_gcc.h **** 
1198:Core/cmsis_gcc.h **** 
1199:Core/cmsis_gcc.h **** /**
1200:Core/cmsis_gcc.h ****   \brief   Get Priority Mask
1201:Core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202:Core/cmsis_gcc.h ****   \return               Priority Mask value
1203:Core/cmsis_gcc.h ****  */
1204:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 1561              		.loc 2 1204 31 view .LVU476
 1562              	.LBB37:
1205:Core/cmsis_gcc.h **** {
1206:Core/cmsis_gcc.h ****   uint32_t result;
 1563              		.loc 2 1206 3 view .LVU477
1207:Core/cmsis_gcc.h **** 
1208:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
 1564              		.loc 2 1208 3 view .LVU478
 1565              		.syntax divided
 1566              	@ 1208 "Core/cmsis_gcc.h" 1
 1567 000c EFF31082 		MRS r2, primask
 1568              	@ 0 "" 2
 1569              	.LVL132:
1209:Core/cmsis_gcc.h ****   return(result);
 1570              		.loc 2 1209 3 view .LVU479
 1571              		.loc 2 1209 3 is_stmt 0 view .LVU480
 1572              		.thumb
 1573              		.syntax unified
 1574              	.LBE37:
 1575              	.LBE36:
 1576              		.loc 1 474 5 is_stmt 1 discriminator 2 view .LVU481
 1577              	.LBB38:
 1578              	.LBI38:
 960:Core/cmsis_gcc.h **** {
 1579              		.loc 2 960 27 view .LVU482
 1580              	.LBB39:
 962:Core/cmsis_gcc.h **** }
 1581              		.loc 2 962 3 view .LVU483
 1582              		.syntax divided
 1583              	@ 962 "Core/cmsis_gcc.h" 1
 1584 0010 72B6     		cpsid i
 1585              	@ 0 "" 2
 1586              		.thumb
 1587              		.syntax unified
 1588              	.LBE39:
 1589              	.LBE38:
 1590              		.loc 1 474 5 discriminator 3 view .LVU484
 1591 0012 294A     		ldr	r2, .L136
 1592 0014 2949     		ldr	r1, .L136+4
 1593              	.LVL133:
 475:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0xFFFF0000;
 1594              		.loc 1 475 12 is_stmt 0 view .LVU485
 1595 0016 2A48     		ldr	r0, .L136+8
 1596              	.LVL134:
 474:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0xFFFF0000;
 1597              		.loc 1 474 5 discriminator 3 view .LVU486
 1598 0018 1160     		str	r1, [r2]
 474:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0xFFFF0000;
 1599              		.loc 1 474 21 is_stmt 1 discriminator 3 view .LVU487
ARM GAS  /tmp/cclh89PE.s 			page 63


 1600              		.loc 1 475 5 view .LVU488
 1601              		.loc 1 475 12 is_stmt 0 view .LVU489
 1602 001a C16C     		ldr	r1, [r0, #76]
 476:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 1603              		.loc 1 476 65 view .LVU490
 1604 001c 1A02     		lsls	r2, r3, #8
 475:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0xFFFF0000;
 1605              		.loc 1 475 24 view .LVU491
 1606 001e 090C     		lsrs	r1, r1, #16
 1607 0020 0904     		lsls	r1, r1, #16
 1608 0022 C164     		str	r1, [r0, #76]
 1609              		.loc 1 476 5 is_stmt 1 view .LVU492
 1610              		.loc 1 476 12 is_stmt 0 view .LVU493
 1611 0024 C16C     		ldr	r1, [r0, #76]
 1612              		.loc 1 476 50 view .LVU494
 1613 0026 2243     		orrs	r2, r4
 1614              		.loc 1 476 24 view .LVU495
 1615 0028 0A43     		orrs	r2, r1
 1616 002a C264     		str	r2, [r0, #76]
 477:Library/src/lcm32f06x_adc.c ****     __dekey();
 1617              		.loc 1 477 5 is_stmt 1 view .LVU496
 1618              	.LBB40:
 1619              	.LBI40:
 949:Core/cmsis_gcc.h **** {
 1620              		.loc 2 949 27 view .LVU497
 1621              	.LBB41:
 951:Core/cmsis_gcc.h **** }
 1622              		.loc 2 951 3 view .LVU498
 1623              		.syntax divided
 1624              	@ 951 "Core/cmsis_gcc.h" 1
 1625 002c 62B6     		cpsie i
 1626              	@ 0 "" 2
 1627              		.thumb
 1628              		.syntax unified
 1629              	.LBE41:
 1630              	.LBE40:
 1631              		.loc 1 477 14 discriminator 1 view .LVU499
 1632              	.LVL135:
 1633              	.L129:
 478:Library/src/lcm32f06x_adc.c ****   }
 479:Library/src/lcm32f06x_adc.c ****   else if (TriggerSelect == TriggerSelect1)
 480:Library/src/lcm32f06x_adc.c ****   {
 481:Library/src/lcm32f06x_adc.c ****     sysctrl_access();
 482:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 483:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 484:Library/src/lcm32f06x_adc.c ****     __dekey();
 485:Library/src/lcm32f06x_adc.c ****   }
 486:Library/src/lcm32f06x_adc.c ****   else if (TriggerSelect == TriggerSelect2)
 487:Library/src/lcm32f06x_adc.c ****   {
 488:Library/src/lcm32f06x_adc.c ****     sysctrl_access();
 489:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 490:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 491:Library/src/lcm32f06x_adc.c ****     __dekey();
 492:Library/src/lcm32f06x_adc.c ****   }
 493:Library/src/lcm32f06x_adc.c ****   else if (TriggerSelect == TriggerSelect3)
 494:Library/src/lcm32f06x_adc.c ****   {
 495:Library/src/lcm32f06x_adc.c ****     sysctrl_access();
ARM GAS  /tmp/cclh89PE.s 			page 64


 496:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 497:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 498:Library/src/lcm32f06x_adc.c ****     __dekey();
 499:Library/src/lcm32f06x_adc.c ****   }
 500:Library/src/lcm32f06x_adc.c **** }
 1634              		.loc 1 500 1 is_stmt 0 view .LVU500
 1635              		@ sp needed
 1636 002e 10BD     		pop	{r4, pc}
 1637              	.LVL136:
 1638              	.L130:
 479:Library/src/lcm32f06x_adc.c ****   {
 1639              		.loc 1 479 8 is_stmt 1 view .LVU501
 479:Library/src/lcm32f06x_adc.c ****   {
 1640              		.loc 1 479 11 is_stmt 0 view .LVU502
 1641 0030 1029     		cmp	r1, #16
 1642 0032 18D0     		beq	.L134
 486:Library/src/lcm32f06x_adc.c ****   {
 1643              		.loc 1 486 8 is_stmt 1 view .LVU503
 486:Library/src/lcm32f06x_adc.c ****   {
 1644              		.loc 1 486 11 is_stmt 0 view .LVU504
 1645 0034 2029     		cmp	r1, #32
 1646 0036 2BD0     		beq	.L135
 493:Library/src/lcm32f06x_adc.c ****   {
 1647              		.loc 1 493 8 is_stmt 1 view .LVU505
 493:Library/src/lcm32f06x_adc.c ****   {
 1648              		.loc 1 493 11 is_stmt 0 view .LVU506
 1649 0038 3029     		cmp	r1, #48
 1650 003a F8D1     		bne	.L129
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1651              		.loc 1 495 5 is_stmt 1 view .LVU507
 1652              	.LBB42:
 1653              	.LBI42:
 258:Core/cmsis_gcc.h **** {
 1654              		.loc 2 258 27 view .LVU508
 1655              	.LBB43:
 260:Core/cmsis_gcc.h **** }
 1656              		.loc 2 260 3 view .LVU509
 1657              		.syntax divided
 1658              	@ 260 "Core/cmsis_gcc.h" 1
 1659 003c BFF36F8F 		isb 0xF
 1660              	@ 0 "" 2
 1661              		.thumb
 1662              		.syntax unified
 1663              	.LBE43:
 1664              	.LBE42:
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1665              		.loc 1 495 5 discriminator 1 view .LVU510
 1666              	.LBB44:
 1667              	.LBI44:
1204:Core/cmsis_gcc.h **** {
 1668              		.loc 2 1204 31 view .LVU511
 1669              	.LBB45:
1206:Core/cmsis_gcc.h **** 
 1670              		.loc 2 1206 3 view .LVU512
1208:Core/cmsis_gcc.h ****   return(result);
 1671              		.loc 2 1208 3 view .LVU513
 1672              		.syntax divided
ARM GAS  /tmp/cclh89PE.s 			page 65


 1673              	@ 1208 "Core/cmsis_gcc.h" 1
 1674 0040 EFF31082 		MRS r2, primask
 1675              	@ 0 "" 2
 1676              	.LVL137:
 1677              		.loc 2 1209 3 view .LVU514
 1678              		.loc 2 1209 3 is_stmt 0 view .LVU515
 1679              		.thumb
 1680              		.syntax unified
 1681              	.LBE45:
 1682              	.LBE44:
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1683              		.loc 1 495 5 is_stmt 1 discriminator 2 view .LVU516
 1684              	.LBB46:
 1685              	.LBI46:
 960:Core/cmsis_gcc.h **** {
 1686              		.loc 2 960 27 view .LVU517
 1687              	.LBB47:
 962:Core/cmsis_gcc.h **** }
 1688              		.loc 2 962 3 view .LVU518
 1689              		.syntax divided
 1690              	@ 962 "Core/cmsis_gcc.h" 1
 1691 0044 72B6     		cpsid i
 1692              	@ 0 "" 2
 1693              		.thumb
 1694              		.syntax unified
 1695              	.LBE47:
 1696              	.LBE46:
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1697              		.loc 1 495 5 discriminator 3 view .LVU519
 1698 0046 1C4A     		ldr	r2, .L136
 1699 0048 1C49     		ldr	r1, .L136+4
 1700              	.LVL138:
 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1701              		.loc 1 497 71 is_stmt 0 view .LVU520
 1702 004a 1B06     		lsls	r3, r3, #24
 1703              	.LVL139:
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1704              		.loc 1 495 5 discriminator 3 view .LVU521
 1705 004c 1160     		str	r1, [r2]
 495:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0x0000FFFF;
 1706              		.loc 1 495 21 is_stmt 1 discriminator 3 view .LVU522
 496:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1707              		.loc 1 496 5 view .LVU523
 496:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1708              		.loc 1 496 12 is_stmt 0 view .LVU524
 1709 004e 1C49     		ldr	r1, .L136+8
 1710 0050 0A6D     		ldr	r2, [r1, #80]
 496:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1711              		.loc 1 496 24 view .LVU525
 1712 0052 1204     		lsls	r2, r2, #16
 1713 0054 120C     		lsrs	r2, r2, #16
 1714 0056 0A65     		str	r2, [r1, #80]
 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1715              		.loc 1 497 5 is_stmt 1 view .LVU526
 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1716              		.loc 1 497 12 is_stmt 0 view .LVU527
 1717 0058 0A6D     		ldr	r2, [r1, #80]
ARM GAS  /tmp/cclh89PE.s 			page 66


 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1718              		.loc 1 497 24 view .LVU528
 1719 005a 1343     		orrs	r3, r2
 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1720              		.loc 1 497 27 view .LVU529
 1721 005c 2204     		lsls	r2, r4, #16
 497:Library/src/lcm32f06x_adc.c ****     __dekey();
 1722              		.loc 1 497 24 view .LVU530
 1723 005e 1A43     		orrs	r2, r3
 1724 0060 0A65     		str	r2, [r1, #80]
 498:Library/src/lcm32f06x_adc.c ****   }
 1725              		.loc 1 498 5 is_stmt 1 view .LVU531
 1726              	.LBB48:
 1727              	.LBI48:
 949:Core/cmsis_gcc.h **** {
 1728              		.loc 2 949 27 view .LVU532
 1729              	.LBB49:
 951:Core/cmsis_gcc.h **** }
 1730              		.loc 2 951 3 view .LVU533
 1731              		.syntax divided
 1732              	@ 951 "Core/cmsis_gcc.h" 1
 1733 0062 62B6     		cpsie i
 1734              	@ 0 "" 2
 1735              		.thumb
 1736              		.syntax unified
 1737              	.LBE49:
 1738              	.LBE48:
 498:Library/src/lcm32f06x_adc.c ****   }
 1739              		.loc 1 498 14 view .LVU534
 1740              		.loc 1 500 1 is_stmt 0 view .LVU535
 1741 0064 E3E7     		b	.L129
 1742              	.LVL140:
 1743              	.L134:
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1744              		.loc 1 481 5 is_stmt 1 view .LVU536
 1745              	.LBB50:
 1746              	.LBI50:
 258:Core/cmsis_gcc.h **** {
 1747              		.loc 2 258 27 view .LVU537
 1748              	.LBB51:
 260:Core/cmsis_gcc.h **** }
 1749              		.loc 2 260 3 view .LVU538
 1750              		.syntax divided
 1751              	@ 260 "Core/cmsis_gcc.h" 1
 1752 0066 BFF36F8F 		isb 0xF
 1753              	@ 0 "" 2
 1754              		.thumb
 1755              		.syntax unified
 1756              	.LBE51:
 1757              	.LBE50:
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1758              		.loc 1 481 5 discriminator 1 view .LVU539
 1759              	.LBB52:
 1760              	.LBI52:
1204:Core/cmsis_gcc.h **** {
 1761              		.loc 2 1204 31 view .LVU540
 1762              	.LBB53:
ARM GAS  /tmp/cclh89PE.s 			page 67


1206:Core/cmsis_gcc.h **** 
 1763              		.loc 2 1206 3 view .LVU541
1208:Core/cmsis_gcc.h ****   return(result);
 1764              		.loc 2 1208 3 view .LVU542
 1765              		.syntax divided
 1766              	@ 1208 "Core/cmsis_gcc.h" 1
 1767 006a EFF31082 		MRS r2, primask
 1768              	@ 0 "" 2
 1769              	.LVL141:
 1770              		.loc 2 1209 3 view .LVU543
 1771              		.loc 2 1209 3 is_stmt 0 view .LVU544
 1772              		.thumb
 1773              		.syntax unified
 1774              	.LBE53:
 1775              	.LBE52:
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1776              		.loc 1 481 5 is_stmt 1 discriminator 2 view .LVU545
 1777              	.LBB54:
 1778              	.LBI54:
 960:Core/cmsis_gcc.h **** {
 1779              		.loc 2 960 27 view .LVU546
 1780              	.LBB55:
 962:Core/cmsis_gcc.h **** }
 1781              		.loc 2 962 3 view .LVU547
 1782              		.syntax divided
 1783              	@ 962 "Core/cmsis_gcc.h" 1
 1784 006e 72B6     		cpsid i
 1785              	@ 0 "" 2
 1786              		.thumb
 1787              		.syntax unified
 1788              	.LBE55:
 1789              	.LBE54:
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1790              		.loc 1 481 5 discriminator 3 view .LVU548
 1791 0070 114A     		ldr	r2, .L136
 1792 0072 1249     		ldr	r1, .L136+4
 1793              	.LVL142:
 483:Library/src/lcm32f06x_adc.c ****     __dekey();
 1794              		.loc 1 483 71 is_stmt 0 view .LVU549
 1795 0074 1B06     		lsls	r3, r3, #24
 1796              	.LVL143:
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1797              		.loc 1 481 5 discriminator 3 view .LVU550
 1798 0076 1160     		str	r1, [r2]
 481:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 &= 0x0000FFFF;
 1799              		.loc 1 481 21 is_stmt 1 discriminator 3 view .LVU551
 482:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1800              		.loc 1 482 5 view .LVU552
 482:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1801              		.loc 1 482 12 is_stmt 0 view .LVU553
 1802 0078 1149     		ldr	r1, .L136+8
 483:Library/src/lcm32f06x_adc.c ****     __dekey();
 1803              		.loc 1 483 27 view .LVU554
 1804 007a 2404     		lsls	r4, r4, #16
 1805              	.LVL144:
 482:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1806              		.loc 1 482 12 view .LVU555
ARM GAS  /tmp/cclh89PE.s 			page 68


 1807 007c CA6C     		ldr	r2, [r1, #76]
 482:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG11 |= (uint32_t) (AdcExtsel << 16) | (Triggermode << 24);
 1808              		.loc 1 482 24 view .LVU556
 1809 007e 1204     		lsls	r2, r2, #16
 1810 0080 120C     		lsrs	r2, r2, #16
 1811 0082 CA64     		str	r2, [r1, #76]
 483:Library/src/lcm32f06x_adc.c ****     __dekey();
 1812              		.loc 1 483 5 is_stmt 1 view .LVU557
 483:Library/src/lcm32f06x_adc.c ****     __dekey();
 1813              		.loc 1 483 12 is_stmt 0 view .LVU558
 1814 0084 CA6C     		ldr	r2, [r1, #76]
 483:Library/src/lcm32f06x_adc.c ****     __dekey();
 1815              		.loc 1 483 24 view .LVU559
 1816 0086 1343     		orrs	r3, r2
 1817 0088 2343     		orrs	r3, r4
 1818 008a CB64     		str	r3, [r1, #76]
 484:Library/src/lcm32f06x_adc.c ****   }
 1819              		.loc 1 484 5 is_stmt 1 view .LVU560
 1820              	.LBB56:
 1821              	.LBI56:
 949:Core/cmsis_gcc.h **** {
 1822              		.loc 2 949 27 view .LVU561
 1823              	.LBB57:
 951:Core/cmsis_gcc.h **** }
 1824              		.loc 2 951 3 view .LVU562
 1825              		.syntax divided
 1826              	@ 951 "Core/cmsis_gcc.h" 1
 1827 008c 62B6     		cpsie i
 1828              	@ 0 "" 2
 1829              		.thumb
 1830              		.syntax unified
 1831              	.LBE57:
 1832              	.LBE56:
 484:Library/src/lcm32f06x_adc.c ****   }
 1833              		.loc 1 484 14 discriminator 1 view .LVU563
 1834              	.LBB59:
 1835              	.LBB58:
 952:Core/cmsis_gcc.h **** 
 1836              		.loc 2 952 1 is_stmt 0 view .LVU564
 1837 008e CEE7     		b	.L129
 1838              	.LVL145:
 1839              	.L135:
 952:Core/cmsis_gcc.h **** 
 1840              		.loc 2 952 1 view .LVU565
 1841              	.LBE58:
 1842              	.LBE59:
 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1843              		.loc 1 488 5 is_stmt 1 view .LVU566
 1844              	.LBB60:
 1845              	.LBI60:
 258:Core/cmsis_gcc.h **** {
 1846              		.loc 2 258 27 view .LVU567
 1847              	.LBB61:
 260:Core/cmsis_gcc.h **** }
 1848              		.loc 2 260 3 view .LVU568
 1849              		.syntax divided
 1850              	@ 260 "Core/cmsis_gcc.h" 1
ARM GAS  /tmp/cclh89PE.s 			page 69


 1851 0090 BFF36F8F 		isb 0xF
 1852              	@ 0 "" 2
 1853              		.thumb
 1854              		.syntax unified
 1855              	.LBE61:
 1856              	.LBE60:
 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1857              		.loc 1 488 5 discriminator 1 view .LVU569
 1858              	.LBB62:
 1859              	.LBI62:
1204:Core/cmsis_gcc.h **** {
 1860              		.loc 2 1204 31 view .LVU570
 1861              	.LBB63:
1206:Core/cmsis_gcc.h **** 
 1862              		.loc 2 1206 3 view .LVU571
1208:Core/cmsis_gcc.h ****   return(result);
 1863              		.loc 2 1208 3 view .LVU572
 1864              		.syntax divided
 1865              	@ 1208 "Core/cmsis_gcc.h" 1
 1866 0094 EFF31082 		MRS r2, primask
 1867              	@ 0 "" 2
 1868              	.LVL146:
 1869              		.loc 2 1209 3 view .LVU573
 1870              		.loc 2 1209 3 is_stmt 0 view .LVU574
 1871              		.thumb
 1872              		.syntax unified
 1873              	.LBE63:
 1874              	.LBE62:
 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1875              		.loc 1 488 5 is_stmt 1 discriminator 2 view .LVU575
 1876              	.LBB64:
 1877              	.LBI64:
 960:Core/cmsis_gcc.h **** {
 1878              		.loc 2 960 27 view .LVU576
 1879              	.LBB65:
 962:Core/cmsis_gcc.h **** }
 1880              		.loc 2 962 3 view .LVU577
 1881              		.syntax divided
 1882              	@ 962 "Core/cmsis_gcc.h" 1
 1883 0098 72B6     		cpsid i
 1884              	@ 0 "" 2
 1885              		.thumb
 1886              		.syntax unified
 1887              	.LBE65:
 1888              	.LBE64:
 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1889              		.loc 1 488 5 discriminator 3 view .LVU578
 1890 009a 074A     		ldr	r2, .L136
 1891 009c 0749     		ldr	r1, .L136+4
 1892              	.LVL147:
 490:Library/src/lcm32f06x_adc.c ****     __dekey();
 1893              		.loc 1 490 65 is_stmt 0 view .LVU579
 1894 009e 1B02     		lsls	r3, r3, #8
 1895              	.LVL148:
 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1896              		.loc 1 488 5 discriminator 3 view .LVU580
 1897 00a0 1160     		str	r1, [r2]
ARM GAS  /tmp/cclh89PE.s 			page 70


 488:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 &= 0xFFFF0000;
 1898              		.loc 1 488 21 is_stmt 1 discriminator 3 view .LVU581
 489:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 1899              		.loc 1 489 5 view .LVU582
 489:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 1900              		.loc 1 489 12 is_stmt 0 view .LVU583
 1901 00a2 0749     		ldr	r1, .L136+8
 490:Library/src/lcm32f06x_adc.c ****     __dekey();
 1902              		.loc 1 490 50 view .LVU584
 1903 00a4 2343     		orrs	r3, r4
 489:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 1904              		.loc 1 489 12 view .LVU585
 1905 00a6 0A6D     		ldr	r2, [r1, #80]
 489:Library/src/lcm32f06x_adc.c ****     SYSCTRL->EDU_CFG12 |= (uint32_t) (AdcExtsel) | (Triggermode << 8);
 1906              		.loc 1 489 24 view .LVU586
 1907 00a8 120C     		lsrs	r2, r2, #16
 1908 00aa 1204     		lsls	r2, r2, #16
 1909 00ac 0A65     		str	r2, [r1, #80]
 490:Library/src/lcm32f06x_adc.c ****     __dekey();
 1910              		.loc 1 490 5 is_stmt 1 view .LVU587
 490:Library/src/lcm32f06x_adc.c ****     __dekey();
 1911              		.loc 1 490 12 is_stmt 0 view .LVU588
 1912 00ae 0A6D     		ldr	r2, [r1, #80]
 490:Library/src/lcm32f06x_adc.c ****     __dekey();
 1913              		.loc 1 490 24 view .LVU589
 1914 00b0 1343     		orrs	r3, r2
 1915 00b2 0B65     		str	r3, [r1, #80]
 491:Library/src/lcm32f06x_adc.c ****   }
 1916              		.loc 1 491 5 is_stmt 1 view .LVU590
 1917              	.LBB66:
 1918              	.LBI66:
 949:Core/cmsis_gcc.h **** {
 1919              		.loc 2 949 27 view .LVU591
 1920              	.LBB67:
 951:Core/cmsis_gcc.h **** }
 1921              		.loc 2 951 3 view .LVU592
 1922              		.syntax divided
 1923              	@ 951 "Core/cmsis_gcc.h" 1
 1924 00b4 62B6     		cpsie i
 1925              	@ 0 "" 2
 1926              		.thumb
 1927              		.syntax unified
 1928              	.LBE67:
 1929              	.LBE66:
 491:Library/src/lcm32f06x_adc.c ****   }
 1930              		.loc 1 491 14 discriminator 1 view .LVU593
 1931              	.LBB69:
 1932              	.LBB68:
 952:Core/cmsis_gcc.h **** 
 1933              		.loc 2 952 1 is_stmt 0 view .LVU594
 1934 00b6 BAE7     		b	.L129
 1935              	.L137:
 1936              		.align	2
 1937              	.L136:
 1938 00b8 7C700048 		.word	1207988348
 1939 00bc 9A65FA05 		.word	100296090
 1940 00c0 00700048 		.word	1207988224
ARM GAS  /tmp/cclh89PE.s 			page 71


 1941              	.LBE68:
 1942              	.LBE69:
 1943              		.cfi_endproc
 1944              	.LFE57:
 1946              		.section	.text.ADC_DMA_Cmd,"ax",%progbits
 1947              		.align	1
 1948              		.p2align 2,,3
 1949              		.global	ADC_DMA_Cmd
 1950              		.syntax unified
 1951              		.code	16
 1952              		.thumb_func
 1954              	ADC_DMA_Cmd:
 1955              	.LVL149:
 1956              	.LFB58:
 501:Library/src/lcm32f06x_adc.c **** 
 502:Library/src/lcm32f06x_adc.c **** /**
 503:Library/src/lcm32f06x_adc.c ****   * @name   ADC_DMA_Cmd
 504:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Enable DMA data transmission corresponding to SOC.
 505:Library/src/lcm32f06x_adc.c ****   *         CN: SOC ????? DMA ???????????
 506:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 507:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 508:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 509:Library/src/lcm32f06x_adc.c ****   * @param  SOCx_DMA:
 510:Library/src/lcm32f06x_adc.c ****   *         EN: where x can be from 0 to 15 to select the SOC channel
 511:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?????? 0 ?? 15 ????? SOC DMA ?????
 512:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 513:Library/src/lcm32f06x_adc.c ****   *         EN: New state of SOC DMA transmission.
 514:Library/src/lcm32f06x_adc.c ****   *         CN: SOC DMA ???????????
 515:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 516:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 517:Library/src/lcm32f06x_adc.c ****   * @retval None
 518:Library/src/lcm32f06x_adc.c ****   */
 519:Library/src/lcm32f06x_adc.c **** void ADC_DMA_Cmd(ADC_TypeDef *ADCx,uint32_t SOCx_DMA,FunctionalState NewState)
 520:Library/src/lcm32f06x_adc.c **** {
 1957              		.loc 1 520 1 is_stmt 1 view -0
 1958              		.cfi_startproc
 1959              		@ args = 0, pretend = 0, frame = 0
 1960              		@ frame_needed = 0, uses_anonymous_args = 0
 1961              		@ link register save eliminated.
 521:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 1962              		.loc 1 521 3 view .LVU596
 522:Library/src/lcm32f06x_adc.c ****   {
 523:Library/src/lcm32f06x_adc.c ****     ADCx->DMACFG |= (SOCx_DMA << 16);
 1963              		.loc 1 523 9 is_stmt 0 view .LVU597
 1964 0000 836A     		ldr	r3, [r0, #40]
 1965              		.loc 1 523 31 view .LVU598
 1966 0002 0904     		lsls	r1, r1, #16
 1967              	.LVL150:
 521:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 1968              		.loc 1 521 6 view .LVU599
 1969 0004 002A     		cmp	r2, #0
 1970 0006 02D0     		beq	.L139
 1971              		.loc 1 523 5 is_stmt 1 view .LVU600
 1972              		.loc 1 523 18 is_stmt 0 view .LVU601
 1973 0008 0B43     		orrs	r3, r1
 1974 000a 8362     		str	r3, [r0, #40]
 1975              	.L138:
ARM GAS  /tmp/cclh89PE.s 			page 72


 524:Library/src/lcm32f06x_adc.c ****   }
 525:Library/src/lcm32f06x_adc.c ****   else
 526:Library/src/lcm32f06x_adc.c ****   {
 527:Library/src/lcm32f06x_adc.c ****     ADCx->DMACFG  &= ~(SOCx_DMA << 16);
 528:Library/src/lcm32f06x_adc.c ****   }
 529:Library/src/lcm32f06x_adc.c **** }
 1976              		.loc 1 529 1 view .LVU602
 1977              		@ sp needed
 1978 000c 7047     		bx	lr
 1979              	.L139:
 527:Library/src/lcm32f06x_adc.c ****   }
 1980              		.loc 1 527 5 is_stmt 1 view .LVU603
 527:Library/src/lcm32f06x_adc.c ****   }
 1981              		.loc 1 527 19 is_stmt 0 view .LVU604
 1982 000e 8B43     		bics	r3, r1
 1983 0010 8362     		str	r3, [r0, #40]
 1984              		.loc 1 529 1 view .LVU605
 1985 0012 FBE7     		b	.L138
 1986              		.cfi_endproc
 1987              	.LFE58:
 1989              		.section	.text.ADC_DMA_TransReq,"ax",%progbits
 1990              		.align	1
 1991              		.p2align 2,,3
 1992              		.global	ADC_DMA_TransReq
 1993              		.syntax unified
 1994              		.code	16
 1995              		.thumb_func
 1997              	ADC_DMA_TransReq:
 1998              	.LVL151:
 1999              	.LFB59:
 530:Library/src/lcm32f06x_adc.c **** 
 531:Library/src/lcm32f06x_adc.c **** /**
 532:Library/src/lcm32f06x_adc.c ****   * @name   ADC_DMA_TransReq
 533:Library/src/lcm32f06x_adc.c ****   * @brief  EN: DMA data transfer request corresponding to SOC.
 534:Library/src/lcm32f06x_adc.c ****   *         CN: SOC ????? DMA ???????????
 535:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 536:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 537:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 538:Library/src/lcm32f06x_adc.c ****   * @param  SOCx_DMA:
 539:Library/src/lcm32f06x_adc.c ****   *         EN: where x can be from 0 to 15 to select the SOC channel
 540:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?????? 0 ?? 15 ????? SOC DMA ?????
 541:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 542:Library/src/lcm32f06x_adc.c ****   *         EN: New state of SOC DMA transmission request.
 543:Library/src/lcm32f06x_adc.c ****   *         CN: SOC DMA ???????????????
 544:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 545:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 546:Library/src/lcm32f06x_adc.c ****   * @retval None
 547:Library/src/lcm32f06x_adc.c ****   */
 548:Library/src/lcm32f06x_adc.c **** void ADC_DMA_TransReq(ADC_TypeDef *ADCx, uint32_t SOCx_DMA, FunctionalState NewState)
 549:Library/src/lcm32f06x_adc.c **** {
 2000              		.loc 1 549 1 is_stmt 1 view -0
 2001              		.cfi_startproc
 2002              		@ args = 0, pretend = 0, frame = 0
 2003              		@ frame_needed = 0, uses_anonymous_args = 0
 2004              		@ link register save eliminated.
 550:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 2005              		.loc 1 550 3 view .LVU607
ARM GAS  /tmp/cclh89PE.s 			page 73


 551:Library/src/lcm32f06x_adc.c ****   {
 552:Library/src/lcm32f06x_adc.c ****     ADCx->DMACFG |= SOCx_DMA;
 2006              		.loc 1 552 9 is_stmt 0 view .LVU608
 2007 0000 836A     		ldr	r3, [r0, #40]
 550:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 2008              		.loc 1 550 6 view .LVU609
 2009 0002 002A     		cmp	r2, #0
 2010 0004 02D0     		beq	.L142
 2011              		.loc 1 552 5 is_stmt 1 view .LVU610
 2012              		.loc 1 552 18 is_stmt 0 view .LVU611
 2013 0006 0B43     		orrs	r3, r1
 2014 0008 8362     		str	r3, [r0, #40]
 2015              	.L141:
 553:Library/src/lcm32f06x_adc.c ****   }
 554:Library/src/lcm32f06x_adc.c ****   else
 555:Library/src/lcm32f06x_adc.c ****   {
 556:Library/src/lcm32f06x_adc.c ****     ADCx->DMACFG  &= ~SOCx_DMA;
 557:Library/src/lcm32f06x_adc.c ****   }
 558:Library/src/lcm32f06x_adc.c **** }
 2016              		.loc 1 558 1 view .LVU612
 2017              		@ sp needed
 2018 000a 7047     		bx	lr
 2019              	.L142:
 556:Library/src/lcm32f06x_adc.c ****   }
 2020              		.loc 1 556 5 is_stmt 1 view .LVU613
 556:Library/src/lcm32f06x_adc.c ****   }
 2021              		.loc 1 556 19 is_stmt 0 view .LVU614
 2022 000c 8B43     		bics	r3, r1
 2023 000e 8362     		str	r3, [r0, #40]
 2024              		.loc 1 558 1 view .LVU615
 2025 0010 FBE7     		b	.L141
 2026              		.cfi_endproc
 2027              	.LFE59:
 2029 0012 C046     		.section	.text.ADC_ITConfig,"ax",%progbits
 2030              		.align	1
 2031              		.p2align 2,,3
 2032              		.global	ADC_ITConfig
 2033              		.syntax unified
 2034              		.code	16
 2035              		.thumb_func
 2037              	ADC_ITConfig:
 2038              	.LVL152:
 2039              	.LFB60:
 559:Library/src/lcm32f06x_adc.c **** 
 560:Library/src/lcm32f06x_adc.c **** /**
 561:Library/src/lcm32f06x_adc.c ****   * @name   ADC_ITConfig
 562:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Enables or disables the specified ADC interrupts.
 563:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC?§Ø??
 564:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 565:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 566:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 567:Library/src/lcm32f06x_adc.c ****   * @param  ADC_IT: 
 568:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC interrupt sources to be enabled or disabled.
 569:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC?§Ø????
 570:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_DOF
 571:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD0
 572:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD1
ARM GAS  /tmp/cclh89PE.s 			page 74


 573:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 574:Library/src/lcm32f06x_adc.c ****   *         EN: new state of the specified ADC interrupts.
 575:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC?§Ø????????
 576:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 577:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 578:Library/src/lcm32f06x_adc.c ****   * @retval None
 579:Library/src/lcm32f06x_adc.c ****   */
 580:Library/src/lcm32f06x_adc.c **** void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
 581:Library/src/lcm32f06x_adc.c **** {
 2040              		.loc 1 581 1 is_stmt 1 view -0
 2041              		.cfi_startproc
 2042              		@ args = 0, pretend = 0, frame = 0
 2043              		@ frame_needed = 0, uses_anonymous_args = 0
 2044              		@ link register save eliminated.
 582:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_IT(ADC_IT));
 2045              		.loc 1 582 3 view .LVU617
 583:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 584:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 2046              		.loc 1 584 3 view .LVU618
 585:Library/src/lcm32f06x_adc.c ****   {
 586:Library/src/lcm32f06x_adc.c ****     /* Enable the selected ADC interrupts */
 587:Library/src/lcm32f06x_adc.c ****     ADCx->IER |= ADC_IT;
 2047              		.loc 1 587 9 is_stmt 0 view .LVU619
 2048 0000 8368     		ldr	r3, [r0, #8]
 584:Library/src/lcm32f06x_adc.c ****   {
 2049              		.loc 1 584 6 view .LVU620
 2050 0002 002A     		cmp	r2, #0
 2051 0004 02D0     		beq	.L145
 2052              		.loc 1 587 5 is_stmt 1 view .LVU621
 2053              		.loc 1 587 15 is_stmt 0 view .LVU622
 2054 0006 0B43     		orrs	r3, r1
 2055 0008 8360     		str	r3, [r0, #8]
 2056              	.L144:
 588:Library/src/lcm32f06x_adc.c ****   }
 589:Library/src/lcm32f06x_adc.c ****   else
 590:Library/src/lcm32f06x_adc.c ****   {
 591:Library/src/lcm32f06x_adc.c ****     /* Disable the selected ADC interrupts */
 592:Library/src/lcm32f06x_adc.c ****     ADCx->IER &= (~(uint32_t)ADC_IT);
 593:Library/src/lcm32f06x_adc.c ****   }
 594:Library/src/lcm32f06x_adc.c **** }
 2057              		.loc 1 594 1 view .LVU623
 2058              		@ sp needed
 2059 000a 7047     		bx	lr
 2060              	.L145:
 592:Library/src/lcm32f06x_adc.c ****   }
 2061              		.loc 1 592 5 is_stmt 1 view .LVU624
 592:Library/src/lcm32f06x_adc.c ****   }
 2062              		.loc 1 592 15 is_stmt 0 view .LVU625
 2063 000c 8B43     		bics	r3, r1
 2064 000e 8360     		str	r3, [r0, #8]
 2065              		.loc 1 594 1 view .LVU626
 2066 0010 FBE7     		b	.L144
 2067              		.cfi_endproc
 2068              	.LFE60:
 2070 0012 C046     		.section	.text.ADC_SOC_ITConfig,"ax",%progbits
 2071              		.align	1
 2072              		.p2align 2,,3
ARM GAS  /tmp/cclh89PE.s 			page 75


 2073              		.global	ADC_SOC_ITConfig
 2074              		.syntax unified
 2075              		.code	16
 2076              		.thumb_func
 2078              	ADC_SOC_ITConfig:
 2079              	.LVL153:
 2080              	.LFB61:
 595:Library/src/lcm32f06x_adc.c **** 
 596:Library/src/lcm32f06x_adc.c **** /**
 597:Library/src/lcm32f06x_adc.c ****   * @name   ADC_SOC_ITConfig
 598:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Enables or disables the specified ADC interrupts.
 599:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC SOC?§Ø??
 600:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 601:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 602:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 603:Library/src/lcm32f06x_adc.c ****   * @param  SOC_IT: 
 604:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC SOC interrupt sources to be enabled or disabled.
 605:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC SOC?§Ø????
 606:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_EOC0...ADC_IT_EOC15
 607:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_POF0...ADC_IT_POF15
 608:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 609:Library/src/lcm32f06x_adc.c ****   *         EN: new state of the specified ADC interrupts.
 610:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC?§Ø????????
 611:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 612:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 613:Library/src/lcm32f06x_adc.c ****   * @retval None
 614:Library/src/lcm32f06x_adc.c ****   */
 615:Library/src/lcm32f06x_adc.c **** void ADC_SOC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_SOC_IT, FunctionalState NewState)
 616:Library/src/lcm32f06x_adc.c **** {
 2081              		.loc 1 616 1 is_stmt 1 view -0
 2082              		.cfi_startproc
 2083              		@ args = 0, pretend = 0, frame = 0
 2084              		@ frame_needed = 0, uses_anonymous_args = 0
 2085              		@ link register save eliminated.
 617:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_SOC_IT(ADC_SOC_IT));
 2086              		.loc 1 617 3 view .LVU628
 618:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 619:Library/src/lcm32f06x_adc.c ****   if (NewState != DISABLE)
 2087              		.loc 1 619 3 view .LVU629
 620:Library/src/lcm32f06x_adc.c ****   {
 621:Library/src/lcm32f06x_adc.c ****     /* Enable the selected ADC interrupts */
 622:Library/src/lcm32f06x_adc.c ****     ADCx->SOCIER |= ADC_SOC_IT;
 2088              		.loc 1 622 9 is_stmt 0 view .LVU630
 2089 0000 0369     		ldr	r3, [r0, #16]
 619:Library/src/lcm32f06x_adc.c ****   {
 2090              		.loc 1 619 6 view .LVU631
 2091 0002 002A     		cmp	r2, #0
 2092 0004 02D0     		beq	.L148
 2093              		.loc 1 622 5 is_stmt 1 view .LVU632
 2094              		.loc 1 622 18 is_stmt 0 view .LVU633
 2095 0006 0B43     		orrs	r3, r1
 2096 0008 0361     		str	r3, [r0, #16]
 2097              	.L147:
 623:Library/src/lcm32f06x_adc.c ****   }
 624:Library/src/lcm32f06x_adc.c ****   else
 625:Library/src/lcm32f06x_adc.c ****   {
 626:Library/src/lcm32f06x_adc.c ****     /* Disable the selected ADC interrupts */
ARM GAS  /tmp/cclh89PE.s 			page 76


 627:Library/src/lcm32f06x_adc.c ****     ADCx->SOCIER &= (~(uint32_t)ADC_SOC_IT);
 628:Library/src/lcm32f06x_adc.c ****   }
 629:Library/src/lcm32f06x_adc.c **** }
 2098              		.loc 1 629 1 view .LVU634
 2099              		@ sp needed
 2100 000a 7047     		bx	lr
 2101              	.L148:
 627:Library/src/lcm32f06x_adc.c ****   }
 2102              		.loc 1 627 5 is_stmt 1 view .LVU635
 627:Library/src/lcm32f06x_adc.c ****   }
 2103              		.loc 1 627 18 is_stmt 0 view .LVU636
 2104 000c 8B43     		bics	r3, r1
 2105 000e 0361     		str	r3, [r0, #16]
 2106              		.loc 1 629 1 view .LVU637
 2107 0010 FBE7     		b	.L147
 2108              		.cfi_endproc
 2109              	.LFE61:
 2111 0012 C046     		.section	.text.ADC_GetFlagStatus,"ax",%progbits
 2112              		.align	1
 2113              		.p2align 2,,3
 2114              		.global	ADC_GetFlagStatus
 2115              		.syntax unified
 2116              		.code	16
 2117              		.thumb_func
 2119              	ADC_GetFlagStatus:
 2120              	.LVL154:
 2121              	.LFB62:
 630:Library/src/lcm32f06x_adc.c **** 
 631:Library/src/lcm32f06x_adc.c **** /**
 632:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetFlagStatus
 633:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Read ADC status flags.
 634:Library/src/lcm32f06x_adc.c ****   *         CN: ??? ADC ???????
 635:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 636:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 637:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 638:Library/src/lcm32f06x_adc.c ****   * @param  ADC_FLAG: 
 639:Library/src/lcm32f06x_adc.c ****   *         EN: Specify the ADC flag to be read.
 640:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC??????????
 641:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_FLAG_READY
 642:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_FLAG_BUSY
 643:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_FLAG_PENDING0
 644:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 645:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_FLAG_PENDING15
 646:Library/src/lcm32f06x_adc.c ****   * @retval FlagStatus
 647:Library/src/lcm32f06x_adc.c ****   */
 648:Library/src/lcm32f06x_adc.c **** FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint32_t ADC_FLAG)
 649:Library/src/lcm32f06x_adc.c **** {
 2122              		.loc 1 649 1 is_stmt 1 view -0
 2123              		.cfi_startproc
 2124              		@ args = 0, pretend = 0, frame = 0
 2125              		@ frame_needed = 0, uses_anonymous_args = 0
 2126              		@ link register save eliminated.
 650:Library/src/lcm32f06x_adc.c ****   FlagStatus bitstatus = RESET;
 2127              		.loc 1 650 3 view .LVU639
 651:Library/src/lcm32f06x_adc.c ****   uint32_t tmpreg = 0;
 2128              		.loc 1 651 3 view .LVU640
 652:Library/src/lcm32f06x_adc.c **** 
ARM GAS  /tmp/cclh89PE.s 			page 77


 653:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 654:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_FLAG(ADC_FLAG));
 2129              		.loc 1 654 3 view .LVU641
 655:Library/src/lcm32f06x_adc.c **** 
 656:Library/src/lcm32f06x_adc.c ****   tmpreg = ADCx->SR;
 2130              		.loc 1 656 3 view .LVU642
 2131              		.loc 1 656 10 is_stmt 0 view .LVU643
 2132 0000 0368     		ldr	r3, [r0]
 2133              	.LVL155:
 657:Library/src/lcm32f06x_adc.c **** 
 658:Library/src/lcm32f06x_adc.c ****   /* Check the status of the specified ADC flag */
 659:Library/src/lcm32f06x_adc.c ****   if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
 2134              		.loc 1 659 3 is_stmt 1 view .LVU644
 660:Library/src/lcm32f06x_adc.c ****   {
 661:Library/src/lcm32f06x_adc.c ****     /* ADC_FLAG is set */
 662:Library/src/lcm32f06x_adc.c ****     bitstatus = SET;
 663:Library/src/lcm32f06x_adc.c ****   }
 664:Library/src/lcm32f06x_adc.c ****   else
 665:Library/src/lcm32f06x_adc.c ****   {
 666:Library/src/lcm32f06x_adc.c ****     /* ADC_FLAG is reset */
 667:Library/src/lcm32f06x_adc.c ****     bitstatus = RESET;
 668:Library/src/lcm32f06x_adc.c ****   }
 669:Library/src/lcm32f06x_adc.c ****   /* Return the ADC_FLAG status */
 670:Library/src/lcm32f06x_adc.c ****   return bitstatus;
 2135              		.loc 1 670 3 view .LVU645
 671:Library/src/lcm32f06x_adc.c **** }
 2136              		.loc 1 671 1 is_stmt 0 view .LVU646
 2137              		@ sp needed
 659:Library/src/lcm32f06x_adc.c ****   {
 2138              		.loc 1 659 15 view .LVU647
 2139 0002 1940     		ands	r1, r3
 2140              	.LVL156:
 659:Library/src/lcm32f06x_adc.c ****   {
 2141              		.loc 1 659 15 view .LVU648
 2142 0004 0800     		movs	r0, r1
 2143              	.LVL157:
 659:Library/src/lcm32f06x_adc.c ****   {
 2144              		.loc 1 659 6 view .LVU649
 2145 0006 431E     		subs	r3, r0, #1
 2146 0008 9841     		sbcs	r0, r0, r3
 2147              	.LVL158:
 670:Library/src/lcm32f06x_adc.c **** }
 2148              		.loc 1 670 10 discriminator 1 view .LVU650
 2149 000a C0B2     		uxtb	r0, r0
 2150              		.loc 1 671 1 view .LVU651
 2151 000c 7047     		bx	lr
 2152              		.cfi_endproc
 2153              	.LFE62:
 2155 000e C046     		.section	.text.ADC_GetITStatus,"ax",%progbits
 2156              		.align	1
 2157              		.p2align 2,,3
 2158              		.global	ADC_GetITStatus
 2159              		.syntax unified
 2160              		.code	16
 2161              		.thumb_func
 2163              	ADC_GetITStatus:
 2164              	.LVL159:
ARM GAS  /tmp/cclh89PE.s 			page 78


 2165              	.LFB63:
 672:Library/src/lcm32f06x_adc.c **** 
 673:Library/src/lcm32f06x_adc.c **** /**
 674:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetITStatus
 675:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Read the specified ADC interrupt status.
 676:Library/src/lcm32f06x_adc.c ****   *         CN: ????????ADC?§Ø?????
 677:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 678:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 679:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 680:Library/src/lcm32f06x_adc.c ****   * @param  ADC_IT: 
 681:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC interrupt sources to be read.
 682:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????ADC?§Ø????
 683:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_DOF
 684:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD0
 685:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD1
 686:Library/src/lcm32f06x_adc.c ****   * @retval ITStatus
 687:Library/src/lcm32f06x_adc.c ****   */
 688:Library/src/lcm32f06x_adc.c **** ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint32_t ADC_IT)
 689:Library/src/lcm32f06x_adc.c **** {
 2166              		.loc 1 689 1 is_stmt 1 view -0
 2167              		.cfi_startproc
 2168              		@ args = 0, pretend = 0, frame = 0
 2169              		@ frame_needed = 0, uses_anonymous_args = 0
 2170              		@ link register save eliminated.
 690:Library/src/lcm32f06x_adc.c ****   ITStatus bitstatus = RESET;
 2171              		.loc 1 690 3 view .LVU653
 691:Library/src/lcm32f06x_adc.c ****   uint32_t enablestatus = 0;
 2172              		.loc 1 691 3 view .LVU654
 692:Library/src/lcm32f06x_adc.c **** 
 693:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 694:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_IT(ADC_IT));
 2173              		.loc 1 694 3 view .LVU655
 695:Library/src/lcm32f06x_adc.c **** 
 696:Library/src/lcm32f06x_adc.c ****   /* Get the ADC_IT enable bit status */
 697:Library/src/lcm32f06x_adc.c ****   enablestatus = (uint32_t)(ADCx->IER & ADC_IT);
 2174              		.loc 1 697 3 view .LVU656
 2175              		.loc 1 697 33 is_stmt 0 view .LVU657
 2176 0000 8268     		ldr	r2, [r0, #8]
 2177              	.LVL160:
 698:Library/src/lcm32f06x_adc.c **** 
 699:Library/src/lcm32f06x_adc.c ****   /* Check the status of the specified ADC interrupt */
 700:Library/src/lcm32f06x_adc.c ****   if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 2178              		.loc 1 700 3 is_stmt 1 view .LVU658
 2179              		.loc 1 700 23 is_stmt 0 view .LVU659
 2180 0002 4368     		ldr	r3, [r0, #4]
 701:Library/src/lcm32f06x_adc.c ****   {
 702:Library/src/lcm32f06x_adc.c ****     /* ADC_IT is set */
 703:Library/src/lcm32f06x_adc.c ****     bitstatus = SET;
 704:Library/src/lcm32f06x_adc.c ****   }
 705:Library/src/lcm32f06x_adc.c ****   else
 706:Library/src/lcm32f06x_adc.c ****   {
 707:Library/src/lcm32f06x_adc.c ****     /* ADC_IT is reset */
 708:Library/src/lcm32f06x_adc.c ****     bitstatus = RESET;
 2181              		.loc 1 708 15 view .LVU660
 2182 0004 0020     		movs	r0, #0
 2183              	.LVL161:
 700:Library/src/lcm32f06x_adc.c ****   {
ARM GAS  /tmp/cclh89PE.s 			page 79


 2184              		.loc 1 700 6 view .LVU661
 2185 0006 1942     		tst	r1, r3
 2186 0008 03D0     		beq	.L152
 697:Library/src/lcm32f06x_adc.c **** 
 2187              		.loc 1 697 16 view .LVU662
 2188 000a 1140     		ands	r1, r2
 2189              	.LVL162:
 700:Library/src/lcm32f06x_adc.c ****   {
 2190              		.loc 1 700 59 discriminator 1 view .LVU663
 2191 000c 4B1E     		subs	r3, r1, #1
 2192 000e 9941     		sbcs	r1, r1, r3
 2193              	.LVL163:
 700:Library/src/lcm32f06x_adc.c ****   {
 2194              		.loc 1 700 59 discriminator 1 view .LVU664
 2195 0010 C8B2     		uxtb	r0, r1
 2196              	.L152:
 2197              	.LVL164:
 709:Library/src/lcm32f06x_adc.c ****   }
 710:Library/src/lcm32f06x_adc.c ****   /* Return the ADC_IT status */
 711:Library/src/lcm32f06x_adc.c ****   return bitstatus;
 2198              		.loc 1 711 3 is_stmt 1 view .LVU665
 712:Library/src/lcm32f06x_adc.c **** }
 2199              		.loc 1 712 1 is_stmt 0 view .LVU666
 2200              		@ sp needed
 2201 0012 7047     		bx	lr
 2202              		.cfi_endproc
 2203              	.LFE63:
 2205              		.section	.text.ADC_GetSOCITStatus,"ax",%progbits
 2206              		.align	1
 2207              		.p2align 2,,3
 2208              		.global	ADC_GetSOCITStatus
 2209              		.syntax unified
 2210              		.code	16
 2211              		.thumb_func
 2213              	ADC_GetSOCITStatus:
 2214              	.LVL165:
 2215              	.LFB64:
 713:Library/src/lcm32f06x_adc.c **** 
 714:Library/src/lcm32f06x_adc.c **** /**
 715:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetSOCITStatus
 716:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Read the specified ADC SOC interrupt status.
 717:Library/src/lcm32f06x_adc.c ****   *         CN: ????????ADC SOC?§Ø?????
 718:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 719:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 720:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 721:Library/src/lcm32f06x_adc.c ****   * @param  ADC_IT: 
 722:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC SOC interrupt sources to be enabled or disabled.
 723:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC SOC ?§Ø????
 724:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_POF0
 725:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 726:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_POF15
 727:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_EOC0
 728:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 729:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_EOC15
 730:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 731:Library/src/lcm32f06x_adc.c ****   *         EN: new state of the specified ADC SOC interrupts.
 732:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADC SOC?§Ø????????
ARM GAS  /tmp/cclh89PE.s 			page 80


 733:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 734:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 735:Library/src/lcm32f06x_adc.c ****   * @retval ITStatus
 736:Library/src/lcm32f06x_adc.c ****   */
 737:Library/src/lcm32f06x_adc.c **** ITStatus ADC_GetSOCITStatus(ADC_TypeDef *ADCx, uint32_t ADC_SOC_IT)
 738:Library/src/lcm32f06x_adc.c **** {
 2216              		.loc 1 738 1 is_stmt 1 view -0
 2217              		.cfi_startproc
 2218              		@ args = 0, pretend = 0, frame = 0
 2219              		@ frame_needed = 0, uses_anonymous_args = 0
 2220              		@ link register save eliminated.
 739:Library/src/lcm32f06x_adc.c ****   ITStatus bitstatus = RESET;
 2221              		.loc 1 739 3 view .LVU668
 740:Library/src/lcm32f06x_adc.c ****   uint32_t enablestatus = 0;
 2222              		.loc 1 740 3 view .LVU669
 741:Library/src/lcm32f06x_adc.c **** 
 742:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 743:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_SOC_IT(ADC_SOC_IT));
 2223              		.loc 1 743 3 view .LVU670
 744:Library/src/lcm32f06x_adc.c **** 
 745:Library/src/lcm32f06x_adc.c ****   /* Get the ADC_IT enable bit status */
 746:Library/src/lcm32f06x_adc.c ****   enablestatus = (uint32_t)(ADCx->SOCIER & ADC_SOC_IT);
 2224              		.loc 1 746 3 view .LVU671
 2225              		.loc 1 746 33 is_stmt 0 view .LVU672
 2226 0000 0269     		ldr	r2, [r0, #16]
 2227              	.LVL166:
 747:Library/src/lcm32f06x_adc.c **** 
 748:Library/src/lcm32f06x_adc.c ****   /* Check the status of the specified ADC interrupt */
 749:Library/src/lcm32f06x_adc.c ****   if (((uint32_t)(ADCx->SOCISR & ADC_SOC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESE
 2228              		.loc 1 749 3 is_stmt 1 view .LVU673
 2229              		.loc 1 749 23 is_stmt 0 view .LVU674
 2230 0002 C368     		ldr	r3, [r0, #12]
 750:Library/src/lcm32f06x_adc.c ****   {
 751:Library/src/lcm32f06x_adc.c ****     /* ADC_IT is set */
 752:Library/src/lcm32f06x_adc.c ****     bitstatus = SET;
 753:Library/src/lcm32f06x_adc.c ****   }
 754:Library/src/lcm32f06x_adc.c ****   else
 755:Library/src/lcm32f06x_adc.c ****   {
 756:Library/src/lcm32f06x_adc.c ****     /* ADC_IT is reset */
 757:Library/src/lcm32f06x_adc.c ****     bitstatus = RESET;
 2231              		.loc 1 757 15 view .LVU675
 2232 0004 0020     		movs	r0, #0
 2233              	.LVL167:
 749:Library/src/lcm32f06x_adc.c ****   {
 2234              		.loc 1 749 6 view .LVU676
 2235 0006 1942     		tst	r1, r3
 2236 0008 03D0     		beq	.L156
 746:Library/src/lcm32f06x_adc.c **** 
 2237              		.loc 1 746 16 view .LVU677
 2238 000a 1140     		ands	r1, r2
 2239              	.LVL168:
 749:Library/src/lcm32f06x_adc.c ****   {
 2240              		.loc 1 749 66 discriminator 1 view .LVU678
 2241 000c 4B1E     		subs	r3, r1, #1
 2242 000e 9941     		sbcs	r1, r1, r3
 2243              	.LVL169:
 749:Library/src/lcm32f06x_adc.c ****   {
ARM GAS  /tmp/cclh89PE.s 			page 81


 2244              		.loc 1 749 66 discriminator 1 view .LVU679
 2245 0010 C8B2     		uxtb	r0, r1
 2246              	.L156:
 2247              	.LVL170:
 758:Library/src/lcm32f06x_adc.c ****   }
 759:Library/src/lcm32f06x_adc.c ****   /* Return the ADC_IT status */
 760:Library/src/lcm32f06x_adc.c ****   return bitstatus;
 2248              		.loc 1 760 3 is_stmt 1 view .LVU680
 761:Library/src/lcm32f06x_adc.c **** }
 2249              		.loc 1 761 1 is_stmt 0 view .LVU681
 2250              		@ sp needed
 2251 0012 7047     		bx	lr
 2252              		.cfi_endproc
 2253              	.LFE64:
 2255              		.section	.text.ADC_ClearITPendingBit,"ax",%progbits
 2256              		.align	1
 2257              		.p2align 2,,3
 2258              		.global	ADC_ClearITPendingBit
 2259              		.syntax unified
 2260              		.code	16
 2261              		.thumb_func
 2263              	ADC_ClearITPendingBit:
 2264              	.LVL171:
 2265              	.LFB65:
 762:Library/src/lcm32f06x_adc.c **** 
 763:Library/src/lcm32f06x_adc.c **** /**
 764:Library/src/lcm32f06x_adc.c ****   * @name   ADC_ClearITPendingBit
 765:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Clears the ADCx's interrupt pending bits.
 766:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADCx???§Ø????¦Ë??
 767:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 768:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 769:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 770:Library/src/lcm32f06x_adc.c ****   * @param  ADC_IT: 
 771:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC interrupt sources to be enabled or disabled.
 772:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC?§Ø????
 773:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_DOF
 774:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD0
 775:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_AWD1
 776:Library/src/lcm32f06x_adc.c ****   * @retval None
 777:Library/src/lcm32f06x_adc.c ****   */
 778:Library/src/lcm32f06x_adc.c **** void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
 779:Library/src/lcm32f06x_adc.c **** {
 2266              		.loc 1 779 1 is_stmt 1 view -0
 2267              		.cfi_startproc
 2268              		@ args = 0, pretend = 0, frame = 0
 2269              		@ frame_needed = 0, uses_anonymous_args = 0
 2270              		@ link register save eliminated.
 780:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 781:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_IT(ADC_IT));
 2271              		.loc 1 781 3 view .LVU683
 782:Library/src/lcm32f06x_adc.c **** 
 783:Library/src/lcm32f06x_adc.c ****   /* Clear the selected ADC interrupt pending bits */
 784:Library/src/lcm32f06x_adc.c ****   ADCx->ISR = (uint32_t)ADC_IT; 
 2272              		.loc 1 784 3 view .LVU684
 2273              		.loc 1 784 13 is_stmt 0 view .LVU685
 2274 0000 4160     		str	r1, [r0, #4]
 785:Library/src/lcm32f06x_adc.c **** }
ARM GAS  /tmp/cclh89PE.s 			page 82


 2275              		.loc 1 785 1 view .LVU686
 2276              		@ sp needed
 2277 0002 7047     		bx	lr
 2278              		.cfi_endproc
 2279              	.LFE65:
 2281              		.section	.text.ADC_ClearSOCITPendingBit,"ax",%progbits
 2282              		.align	1
 2283              		.p2align 2,,3
 2284              		.global	ADC_ClearSOCITPendingBit
 2285              		.syntax unified
 2286              		.code	16
 2287              		.thumb_func
 2289              	ADC_ClearSOCITPendingBit:
 2290              	.LVL172:
 2291              	.LFB66:
 786:Library/src/lcm32f06x_adc.c **** 
 787:Library/src/lcm32f06x_adc.c **** /**
 788:Library/src/lcm32f06x_adc.c ****   * @name   ADC_ClearSOCITPendingBit
 789:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Clears the ADCx's SOC interrupt pending bits.
 790:Library/src/lcm32f06x_adc.c ****   *         CN: ???ADCx??SOC?§Ø????¦Ë??
 791:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 792:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 793:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 794:Library/src/lcm32f06x_adc.c ****   * @param  ADC_IT: 
 795:Library/src/lcm32f06x_adc.c ****   *         EN: Specifies the ADC SOC interrupt sources to be enabled or disabled.
 796:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????????ADC SOC?§Ø????
 797:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_POF0
 798:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 799:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_POF15
 800:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_EOC0
 801:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 802:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_IT_EOC15
 803:Library/src/lcm32f06x_adc.c ****   * @retval None
 804:Library/src/lcm32f06x_adc.c ****   */
 805:Library/src/lcm32f06x_adc.c **** void ADC_ClearSOCITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_SOC_IT)
 806:Library/src/lcm32f06x_adc.c **** {
 2292              		.loc 1 806 1 is_stmt 1 view -0
 2293              		.cfi_startproc
 2294              		@ args = 0, pretend = 0, frame = 0
 2295              		@ frame_needed = 0, uses_anonymous_args = 0
 2296              		@ link register save eliminated.
 807:Library/src/lcm32f06x_adc.c ****   /* Check the parameters */
 808:Library/src/lcm32f06x_adc.c ****   assert_param(IS_ADC_SOC_IT(ADC_SOC_IT));
 2297              		.loc 1 808 3 view .LVU688
 809:Library/src/lcm32f06x_adc.c **** 
 810:Library/src/lcm32f06x_adc.c ****   /* Clear the selected ADC interrupt pending bits */
 811:Library/src/lcm32f06x_adc.c ****   ADCx->SOCISR = (uint32_t)ADC_SOC_IT; 
 2298              		.loc 1 811 3 view .LVU689
 2299              		.loc 1 811 16 is_stmt 0 view .LVU690
 2300 0000 C160     		str	r1, [r0, #12]
 812:Library/src/lcm32f06x_adc.c **** }
 2301              		.loc 1 812 1 view .LVU691
 2302              		@ sp needed
 2303 0002 7047     		bx	lr
 2304              		.cfi_endproc
 2305              	.LFE66:
 2307              		.section	.text.ADC_Trim,"ax",%progbits
ARM GAS  /tmp/cclh89PE.s 			page 83


 2308              		.align	1
 2309              		.p2align 2,,3
 2310              		.global	ADC_Trim
 2311              		.syntax unified
 2312              		.code	16
 2313              		.thumb_func
 2315              	ADC_Trim:
 2316              	.LVL173:
 2317              	.LFB67:
 813:Library/src/lcm32f06x_adc.c **** 
 814:Library/src/lcm32f06x_adc.c **** 
 815:Library/src/lcm32f06x_adc.c **** /**
 816:Library/src/lcm32f06x_adc.c ****   * @name   ADC_Trim
 817:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC calibration value writing.
 818:Library/src/lcm32f06x_adc.c ****   *         CN: ADC §µ??§Õ??
 819:Library/src/lcm32f06x_adc.c ****   * @param  VosTrim:
 820:Library/src/lcm32f06x_adc.c ****   *         EN: ADC offset.
 821:Library/src/lcm32f06x_adc.c ****   *         CN: ADC ????
 822:Library/src/lcm32f06x_adc.c ****   * @param  GainTrim: 
 823:Library/src/lcm32f06x_adc.c ****   *         EN: ADC gain.
 824:Library/src/lcm32f06x_adc.c ****   *         CN: ADC ???µµ
 825:Library/src/lcm32f06x_adc.c ****   * @retval None
 826:Library/src/lcm32f06x_adc.c ****   */
 827:Library/src/lcm32f06x_adc.c **** void ADC_Trim(ADC_TypeDef *ADCx, uint8_t VosTrim, uint8_t GainTrim)
 828:Library/src/lcm32f06x_adc.c **** {
 2318              		.loc 1 828 1 is_stmt 1 view -0
 2319              		.cfi_startproc
 2320              		@ args = 0, pretend = 0, frame = 0
 2321              		@ frame_needed = 0, uses_anonymous_args = 0
 829:Library/src/lcm32f06x_adc.c ****   /* Write Trim Value*/
 830:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.VOS_TRIM = VosTrim;
 2322              		.loc 1 830 3 view .LVU693
 828:Library/src/lcm32f06x_adc.c ****   /* Write Trim Value*/
 2323              		.loc 1 828 1 is_stmt 0 view .LVU694
 2324 0000 30B5     		push	{r4, r5, lr}
 2325              	.LCFI5:
 2326              		.cfi_def_cfa_offset 12
 2327              		.cfi_offset 4, -12
 2328              		.cfi_offset 5, -8
 2329              		.cfi_offset 14, -4
 2330              		.loc 1 830 25 view .LVU695
 2331 0002 FF24     		movs	r4, #255
 831:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 832:Library/src/lcm32f06x_adc.c **** }
 2332              		.loc 1 832 1 view .LVU696
 2333              		@ sp needed
 830:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 2334              		.loc 1 830 25 view .LVU697
 2335 0004 036A     		ldr	r3, [r0, #32]
 2336 0006 054D     		ldr	r5, .L162
 2337 0008 0904     		lsls	r1, r1, #16
 2338              	.LVL174:
 830:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 2339              		.loc 1 830 25 view .LVU698
 2340 000a 2B40     		ands	r3, r5
 2341 000c 0B43     		orrs	r3, r1
 2342 000e 0362     		str	r3, [r0, #32]
ARM GAS  /tmp/cclh89PE.s 			page 84


 831:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 2343              		.loc 1 831 3 is_stmt 1 view .LVU699
 831:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 2344              		.loc 1 831 26 is_stmt 0 view .LVU700
 2345 0010 036A     		ldr	r3, [r0, #32]
 2346 0012 2240     		ands	r2, r4
 2347              	.LVL175:
 831:Library/src/lcm32f06x_adc.c ****   ADCx->TRIM_b.GAIN_TRIM = GainTrim;
 2348              		.loc 1 831 26 view .LVU701
 2349 0014 A343     		bics	r3, r4
 2350 0016 1343     		orrs	r3, r2
 2351 0018 0362     		str	r3, [r0, #32]
 2352              		.loc 1 832 1 view .LVU702
 2353 001a 30BD     		pop	{r4, r5, pc}
 2354              	.L163:
 2355              		.align	2
 2356              	.L162:
 2357 001c FFFF00FF 		.word	-16711681
 2358              		.cfi_endproc
 2359              	.LFE67:
 2361              		.section	.text.ADC_SoftTrig,"ax",%progbits
 2362              		.align	1
 2363              		.p2align 2,,3
 2364              		.global	ADC_SoftTrig
 2365              		.syntax unified
 2366              		.code	16
 2367              		.thumb_func
 2369              	ADC_SoftTrig:
 2370              	.LVL176:
 2371              	.LFB68:
 833:Library/src/lcm32f06x_adc.c **** 
 834:Library/src/lcm32f06x_adc.c **** /**
 835:Library/src/lcm32f06x_adc.c ****   * @name   ADC_SoftTrig
 836:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC software triggering.
 837:Library/src/lcm32f06x_adc.c ****   *         CN: ADC ??????????
 838:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 839:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 840:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 841:Library/src/lcm32f06x_adc.c ****   * @param  SofTrig: 
 842:Library/src/lcm32f06x_adc.c ****   *         EN: ADC SOC software trigger bit.
 843:Library/src/lcm32f06x_adc.c ****   *         CN: ADC SOC ????????¦Ë??
 844:Library/src/lcm32f06x_adc.c ****   *         @arg SOC0_TRIG
 845:Library/src/lcm32f06x_adc.c ****   *         @arg ...
 846:Library/src/lcm32f06x_adc.c ****   *         @arg SOC15_TRIG
 847:Library/src/lcm32f06x_adc.c ****   * @retval None
 848:Library/src/lcm32f06x_adc.c ****   */
 849:Library/src/lcm32f06x_adc.c **** void ADC_SoftTrig(ADC_TypeDef *ADCx, uint32_t SofTrig)
 850:Library/src/lcm32f06x_adc.c **** {
 2372              		.loc 1 850 1 is_stmt 1 view -0
 2373              		.cfi_startproc
 2374              		@ args = 0, pretend = 0, frame = 0
 2375              		@ frame_needed = 0, uses_anonymous_args = 0
 2376              		@ link register save eliminated.
 851:Library/src/lcm32f06x_adc.c ****     ADCx->CR = SofTrig;
 2377              		.loc 1 851 5 view .LVU704
 2378              		.loc 1 851 14 is_stmt 0 view .LVU705
 2379 0000 4161     		str	r1, [r0, #20]
ARM GAS  /tmp/cclh89PE.s 			page 85


 852:Library/src/lcm32f06x_adc.c ****     while (!(ADCx->SR & SofTrig))
 2380              		.loc 1 852 5 is_stmt 1 view .LVU706
 2381              		.loc 1 852 12 view .LVU707
 2382              		.loc 1 852 18 is_stmt 0 view .LVU708
 2383 0002 0368     		ldr	r3, [r0]
 2384              		.loc 1 852 12 view .LVU709
 2385 0004 0B42     		tst	r3, r1
 2386 0006 07D1     		bne	.L164
 2387              	.L166:
 853:Library/src/lcm32f06x_adc.c ****     {
 854:Library/src/lcm32f06x_adc.c ****         __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 2388              		.loc 1 854 9 is_stmt 1 view .LVU710
 2389              		.syntax divided
 2390              	@ 854 "Library/src/lcm32f06x_adc.c" 1
 2391 0008 C046     		nop
 2392              	@ 0 "" 2
 2393              		.loc 1 854 18 view .LVU711
 2394              	@ 854 "Library/src/lcm32f06x_adc.c" 1
 2395 000a C046     		nop
 2396              	@ 0 "" 2
 2397              		.loc 1 854 27 view .LVU712
 2398              	@ 854 "Library/src/lcm32f06x_adc.c" 1
 2399 000c C046     		nop
 2400              	@ 0 "" 2
 2401              		.loc 1 854 36 view .LVU713
 2402              	@ 854 "Library/src/lcm32f06x_adc.c" 1
 2403 000e C046     		nop
 2404              	@ 0 "" 2
 2405              		.loc 1 854 45 view .LVU714
 2406              	@ 854 "Library/src/lcm32f06x_adc.c" 1
 2407 0010 C046     		nop
 2408              	@ 0 "" 2
 852:Library/src/lcm32f06x_adc.c ****     while (!(ADCx->SR & SofTrig))
 2409              		.loc 1 852 12 view .LVU715
 852:Library/src/lcm32f06x_adc.c ****     while (!(ADCx->SR & SofTrig))
 2410              		.loc 1 852 18 is_stmt 0 view .LVU716
 2411              		.thumb
 2412              		.syntax unified
 2413 0012 0368     		ldr	r3, [r0]
 852:Library/src/lcm32f06x_adc.c ****     while (!(ADCx->SR & SofTrig))
 2414              		.loc 1 852 12 view .LVU717
 2415 0014 1942     		tst	r1, r3
 2416 0016 F7D0     		beq	.L166
 2417              	.L164:
 855:Library/src/lcm32f06x_adc.c ****     };
 856:Library/src/lcm32f06x_adc.c **** }
 2418              		.loc 1 856 1 view .LVU718
 2419              		@ sp needed
 2420 0018 7047     		bx	lr
 2421              		.cfi_endproc
 2422              	.LFE68:
 2424 001a C046     		.section	.text.ADC_AnalogWatchdogThresholdsConfg,"ax",%progbits
 2425              		.align	1
 2426              		.p2align 2,,3
 2427              		.global	ADC_AnalogWatchdogThresholdsConfg
 2428              		.syntax unified
 2429              		.code	16
ARM GAS  /tmp/cclh89PE.s 			page 86


 2430              		.thumb_func
 2432              	ADC_AnalogWatchdogThresholdsConfg:
 2433              	.LVL177:
 2434              	.LFB69:
 857:Library/src/lcm32f06x_adc.c **** 
 858:Library/src/lcm32f06x_adc.c **** 
 859:Library/src/lcm32f06x_adc.c **** /**
 860:Library/src/lcm32f06x_adc.c ****   * @name   ADC_AnalogWatchdogThresholdsConfg
 861:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC Analog Watchdog Thresholds Config.
 862:Library/src/lcm32f06x_adc.c ****   *         CN: ADC????????????¨¢?
 863:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 864:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 865:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 866:Library/src/lcm32f06x_adc.c ****   * @param  AWDx_SEL: 
 867:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog selection.
 868:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????
 869:Library/src/lcm32f06x_adc.c ****   *             @arg AWD0
 870:Library/src/lcm32f06x_adc.c ****   *             @arg AWD1
 871:Library/src/lcm32f06x_adc.c ****   * @param  HighThreshold: 
 872:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog monitoring high threshold.
 873:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????????
 874:Library/src/lcm32f06x_adc.c ****   * @param  LowThreshold: 
 875:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog monitoring low threshold.
 876:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????????
 877:Library/src/lcm32f06x_adc.c ****   * @retval None
 878:Library/src/lcm32f06x_adc.c ****   */
 879:Library/src/lcm32f06x_adc.c **** void ADC_AnalogWatchdogThresholdsConfg(ADC_TypeDef *ADCx, uint8_t AWDx_SEL, uint16_t HighThreshold,
 880:Library/src/lcm32f06x_adc.c **** {
 2435              		.loc 1 880 1 is_stmt 1 view -0
 2436              		.cfi_startproc
 2437              		@ args = 0, pretend = 0, frame = 0
 2438              		@ frame_needed = 0, uses_anonymous_args = 0
 2439              		@ link register save eliminated.
 881:Library/src/lcm32f06x_adc.c ****   /* Set the ADCx high and low threshold */
 882:Library/src/lcm32f06x_adc.c ****   if(AWDx_SEL == AWD0)
 2440              		.loc 1 882 3 view .LVU720
 2441              		.loc 1 882 5 is_stmt 0 view .LVU721
 2442 0000 0129     		cmp	r1, #1
 2443 0002 06D0     		beq	.L172
 883:Library/src/lcm32f06x_adc.c ****   {
 884:Library/src/lcm32f06x_adc.c ****     ADCx->AWD0_TR = LowThreshold | ((uint32_t)HighThreshold << 16);
 885:Library/src/lcm32f06x_adc.c ****   }
 886:Library/src/lcm32f06x_adc.c ****   else if (AWDx_SEL == AWD1)
 2444              		.loc 1 886 8 is_stmt 1 view .LVU722
 2445              		.loc 1 886 11 is_stmt 0 view .LVU723
 2446 0004 0229     		cmp	r1, #2
 2447 0006 00D0     		beq	.L173
 2448              	.LVL178:
 2449              	.L169:
 887:Library/src/lcm32f06x_adc.c ****   {
 888:Library/src/lcm32f06x_adc.c ****     ADCx->AWD1_TR = LowThreshold | ((uint32_t)HighThreshold << 16);
 889:Library/src/lcm32f06x_adc.c ****   }
 890:Library/src/lcm32f06x_adc.c **** }
 2450              		.loc 1 890 1 view .LVU724
 2451              		@ sp needed
 2452 0008 7047     		bx	lr
 2453              	.LVL179:
ARM GAS  /tmp/cclh89PE.s 			page 87


 2454              	.L173:
 888:Library/src/lcm32f06x_adc.c ****   }
 2455              		.loc 1 888 5 is_stmt 1 view .LVU725
 888:Library/src/lcm32f06x_adc.c ****   }
 2456              		.loc 1 888 61 is_stmt 0 view .LVU726
 2457 000a 1204     		lsls	r2, r2, #16
 2458              	.LVL180:
 888:Library/src/lcm32f06x_adc.c ****   }
 2459              		.loc 1 888 34 view .LVU727
 2460 000c 1A43     		orrs	r2, r3
 888:Library/src/lcm32f06x_adc.c ****   }
 2461              		.loc 1 888 19 view .LVU728
 2462 000e 4265     		str	r2, [r0, #84]
 2463              		.loc 1 890 1 view .LVU729
 2464 0010 FAE7     		b	.L169
 2465              	.LVL181:
 2466              	.L172:
 884:Library/src/lcm32f06x_adc.c ****   }
 2467              		.loc 1 884 5 is_stmt 1 view .LVU730
 884:Library/src/lcm32f06x_adc.c ****   }
 2468              		.loc 1 884 61 is_stmt 0 view .LVU731
 2469 0012 1204     		lsls	r2, r2, #16
 2470              	.LVL182:
 884:Library/src/lcm32f06x_adc.c ****   }
 2471              		.loc 1 884 34 view .LVU732
 2472 0014 1A43     		orrs	r2, r3
 884:Library/src/lcm32f06x_adc.c ****   }
 2473              		.loc 1 884 19 view .LVU733
 2474 0016 0265     		str	r2, [r0, #80]
 2475 0018 F6E7     		b	.L169
 2476              		.cfi_endproc
 2477              	.LFE69:
 2479 001a C046     		.section	.text.ADC_AnalogWatchdogSingleChannelConfig,"ax",%progbits
 2480              		.align	1
 2481              		.p2align 2,,3
 2482              		.global	ADC_AnalogWatchdogSingleChannelConfig
 2483              		.syntax unified
 2484              		.code	16
 2485              		.thumb_func
 2487              	ADC_AnalogWatchdogSingleChannelConfig:
 2488              	.LVL183:
 2489              	.LFB70:
 891:Library/src/lcm32f06x_adc.c **** 
 892:Library/src/lcm32f06x_adc.c **** /**
 893:Library/src/lcm32f06x_adc.c ****   * @name   ADC_AnalogWatchdogSingleChannelConfig
 894:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC Configure monitoring channels for analog watchdog.
 895:Library/src/lcm32f06x_adc.c ****   *         CN: ADC???????????????????
 896:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 897:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 898:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 899:Library/src/lcm32f06x_adc.c ****   * @param  AWDx_SEL: 
 900:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog selection.
 901:Library/src/lcm32f06x_adc.c ****   *         CN: ?????????
 902:Library/src/lcm32f06x_adc.c ****   *             @arg AWD0
 903:Library/src/lcm32f06x_adc.c ****   *             @arg AWD1
 904:Library/src/lcm32f06x_adc.c ****   * @param  ADC_AWD_Channel: 
 905:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog monitoring channel selection.
ARM GAS  /tmp/cclh89PE.s 			page 88


 906:Library/src/lcm32f06x_adc.c ****   *         CN: ???????????????
 907:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_AWD_Channel_0
 908:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_AWD_Channel_1
 909:Library/src/lcm32f06x_adc.c ****   *             @arg ...
 910:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_AWD_Channel_15
 911:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 912:Library/src/lcm32f06x_adc.c ****   *         EN: Analog watchdog monitoring channel enable.
 913:Library/src/lcm32f06x_adc.c ****   *         CN: ????????????????
 914:Library/src/lcm32f06x_adc.c ****   * @retval None
 915:Library/src/lcm32f06x_adc.c ****   */
 916:Library/src/lcm32f06x_adc.c **** void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t AWDx_SEL, uint32_t ADC_AWD_Ch
 917:Library/src/lcm32f06x_adc.c **** {
 2490              		.loc 1 917 1 is_stmt 1 view -0
 2491              		.cfi_startproc
 2492              		@ args = 0, pretend = 0, frame = 0
 2493              		@ frame_needed = 0, uses_anonymous_args = 0
 2494              		@ link register save eliminated.
 918:Library/src/lcm32f06x_adc.c **** 
 919:Library/src/lcm32f06x_adc.c ****   if(AWDx_SEL == AWD0)
 2495              		.loc 1 919 3 view .LVU735
 2496              		.loc 1 919 5 is_stmt 0 view .LVU736
 2497 0000 0129     		cmp	r1, #1
 2498 0002 08D0     		beq	.L179
 920:Library/src/lcm32f06x_adc.c ****   {
 921:Library/src/lcm32f06x_adc.c ****     if (NewState != DISABLE)
 922:Library/src/lcm32f06x_adc.c ****     {
 923:Library/src/lcm32f06x_adc.c ****       ADCx->AWD0_CFGR |= (uint32_t)ADC_AWD_Channel;
 924:Library/src/lcm32f06x_adc.c ****     }
 925:Library/src/lcm32f06x_adc.c ****     else
 926:Library/src/lcm32f06x_adc.c ****     {
 927:Library/src/lcm32f06x_adc.c ****       ADCx->AWD0_CFGR &= (~(uint32_t)ADC_AWD_Channel);
 928:Library/src/lcm32f06x_adc.c ****     }
 929:Library/src/lcm32f06x_adc.c ****   }
 930:Library/src/lcm32f06x_adc.c ****   else if (AWDx_SEL == AWD1)
 2499              		.loc 1 930 8 is_stmt 1 view .LVU737
 2500              		.loc 1 930 11 is_stmt 0 view .LVU738
 2501 0004 0229     		cmp	r1, #2
 2502 0006 00D0     		beq	.L180
 2503              	.LVL184:
 2504              	.L174:
 931:Library/src/lcm32f06x_adc.c ****   {
 932:Library/src/lcm32f06x_adc.c ****     if (NewState != DISABLE)
 933:Library/src/lcm32f06x_adc.c ****     {
 934:Library/src/lcm32f06x_adc.c ****       ADCx->AWD1_CFGR |= (uint32_t)ADC_AWD_Channel;
 935:Library/src/lcm32f06x_adc.c ****     }
 936:Library/src/lcm32f06x_adc.c ****     else
 937:Library/src/lcm32f06x_adc.c ****     {
 938:Library/src/lcm32f06x_adc.c ****       ADCx->AWD1_CFGR &= (~(uint32_t)ADC_AWD_Channel);
 939:Library/src/lcm32f06x_adc.c ****     }
 940:Library/src/lcm32f06x_adc.c ****   }
 941:Library/src/lcm32f06x_adc.c **** }
 2505              		.loc 1 941 1 view .LVU739
 2506              		@ sp needed
 2507 0008 7047     		bx	lr
 2508              	.LVL185:
 2509              	.L180:
 932:Library/src/lcm32f06x_adc.c ****     {
ARM GAS  /tmp/cclh89PE.s 			page 89


 2510              		.loc 1 932 5 is_stmt 1 view .LVU740
 932:Library/src/lcm32f06x_adc.c ****     {
 2511              		.loc 1 932 8 is_stmt 0 view .LVU741
 2512 000a 002B     		cmp	r3, #0
 2513 000c 0DD0     		beq	.L178
 934:Library/src/lcm32f06x_adc.c ****     }
 2514              		.loc 1 934 7 is_stmt 1 view .LVU742
 934:Library/src/lcm32f06x_adc.c ****     }
 2515              		.loc 1 934 11 is_stmt 0 view .LVU743
 2516 000e 436C     		ldr	r3, [r0, #68]
 2517              	.LVL186:
 934:Library/src/lcm32f06x_adc.c ****     }
 2518              		.loc 1 934 23 view .LVU744
 2519 0010 1343     		orrs	r3, r2
 2520 0012 4364     		str	r3, [r0, #68]
 2521 0014 F8E7     		b	.L174
 2522              	.LVL187:
 2523              	.L179:
 921:Library/src/lcm32f06x_adc.c ****     {
 2524              		.loc 1 921 5 is_stmt 1 view .LVU745
 921:Library/src/lcm32f06x_adc.c ****     {
 2525              		.loc 1 921 8 is_stmt 0 view .LVU746
 2526 0016 002B     		cmp	r3, #0
 2527 0018 03D0     		beq	.L176
 923:Library/src/lcm32f06x_adc.c ****     }
 2528              		.loc 1 923 7 is_stmt 1 view .LVU747
 923:Library/src/lcm32f06x_adc.c ****     }
 2529              		.loc 1 923 11 is_stmt 0 view .LVU748
 2530 001a 036C     		ldr	r3, [r0, #64]
 2531              	.LVL188:
 923:Library/src/lcm32f06x_adc.c ****     }
 2532              		.loc 1 923 23 view .LVU749
 2533 001c 1343     		orrs	r3, r2
 2534 001e 0364     		str	r3, [r0, #64]
 2535 0020 F2E7     		b	.L174
 2536              	.LVL189:
 2537              	.L176:
 927:Library/src/lcm32f06x_adc.c ****     }
 2538              		.loc 1 927 7 is_stmt 1 view .LVU750
 927:Library/src/lcm32f06x_adc.c ****     }
 2539              		.loc 1 927 11 is_stmt 0 view .LVU751
 2540 0022 036C     		ldr	r3, [r0, #64]
 2541              	.LVL190:
 927:Library/src/lcm32f06x_adc.c ****     }
 2542              		.loc 1 927 23 view .LVU752
 2543 0024 9343     		bics	r3, r2
 2544 0026 0364     		str	r3, [r0, #64]
 2545 0028 EEE7     		b	.L174
 2546              	.LVL191:
 2547              	.L178:
 938:Library/src/lcm32f06x_adc.c ****     }
 2548              		.loc 1 938 7 is_stmt 1 view .LVU753
 938:Library/src/lcm32f06x_adc.c ****     }
 2549              		.loc 1 938 11 is_stmt 0 view .LVU754
 2550 002a 436C     		ldr	r3, [r0, #68]
 2551              	.LVL192:
 938:Library/src/lcm32f06x_adc.c ****     }
ARM GAS  /tmp/cclh89PE.s 			page 90


 2552              		.loc 1 938 23 view .LVU755
 2553 002c 9343     		bics	r3, r2
 2554 002e 4364     		str	r3, [r0, #68]
 2555              		.loc 1 941 1 view .LVU756
 2556 0030 EAE7     		b	.L174
 2557              		.cfi_endproc
 2558              	.LFE70:
 2560 0032 C046     		.section	.text.ADC_Vref_Cmd,"ax",%progbits
 2561              		.align	1
 2562              		.p2align 2,,3
 2563              		.global	ADC_Vref_Cmd
 2564              		.syntax unified
 2565              		.code	16
 2566              		.thumb_func
 2568              	ADC_Vref_Cmd:
 2569              	.LVL193:
 2570              	.LFB71:
 942:Library/src/lcm32f06x_adc.c **** 
 943:Library/src/lcm32f06x_adc.c **** 
 944:Library/src/lcm32f06x_adc.c **** /**
 945:Library/src/lcm32f06x_adc.c ****   * @name   ADC_Vref_Cmd
 946:Library/src/lcm32f06x_adc.c ****   * @brief  EN: Reference voltage module of the designated ADC for power on or off.
 947:Library/src/lcm32f06x_adc.c ****   *         CN: ????????????ADC??¦Ï??????î•
 948:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 949:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 950:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 951:Library/src/lcm32f06x_adc.c ****   * @param  NewState: 
 952:Library/src/lcm32f06x_adc.c ****   *         EN: The new state of the reference voltage module of ADC.
 953:Library/src/lcm32f06x_adc.c ****   *         CN: ADC??¦Ï??????????????
 954:Library/src/lcm32f06x_adc.c ****   *             @arg ENABLE
 955:Library/src/lcm32f06x_adc.c ****   *             @arg DISABLE
 956:Library/src/lcm32f06x_adc.c ****   * @retval None
 957:Library/src/lcm32f06x_adc.c ****   */
 958:Library/src/lcm32f06x_adc.c **** void ADC_Vref_Cmd(ADC_TypeDef *ADCx, FunctionalState State)
 959:Library/src/lcm32f06x_adc.c **** {
 2571              		.loc 1 959 1 is_stmt 1 view -0
 2572              		.cfi_startproc
 2573              		@ args = 0, pretend = 0, frame = 0
 2574              		@ frame_needed = 0, uses_anonymous_args = 0
 2575              		@ link register save eliminated.
 960:Library/src/lcm32f06x_adc.c ****   if (State != DISABLE)
 2576              		.loc 1 960 3 view .LVU758
 961:Library/src/lcm32f06x_adc.c ****   {
 962:Library/src/lcm32f06x_adc.c ****     /* Set the PD_REF bit to Power on the ADC reference voltage module */
 963:Library/src/lcm32f06x_adc.c ****     while (ADCx->CR & ADC_CR_START_Msk)
 2577              		.loc 1 963 16 is_stmt 0 view .LVU759
 2578 0000 4369     		ldr	r3, [r0, #20]
 960:Library/src/lcm32f06x_adc.c ****   if (State != DISABLE)
 2579              		.loc 1 960 6 view .LVU760
 2580 0002 0029     		cmp	r1, #0
 2581 0004 0FD0     		beq	.L182
 2582              		.loc 1 963 12 is_stmt 1 view .LVU761
 2583 0006 5B07     		lsls	r3, r3, #29
 2584 0008 08D5     		bpl	.L183
 2585              		.loc 1 963 21 is_stmt 0 view .LVU762
 2586 000a 0422     		movs	r2, #4
 2587              	.L184:
ARM GAS  /tmp/cclh89PE.s 			page 91


 964:Library/src/lcm32f06x_adc.c ****     {
 965:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 2588              		.loc 1 965 7 is_stmt 1 view .LVU763
 2589              		.syntax divided
 2590              	@ 965 "Library/src/lcm32f06x_adc.c" 1
 2591 000c C046     		nop
 2592              	@ 0 "" 2
 2593              		.loc 1 965 16 view .LVU764
 2594              	@ 965 "Library/src/lcm32f06x_adc.c" 1
 2595 000e C046     		nop
 2596              	@ 0 "" 2
 2597              		.loc 1 965 25 view .LVU765
 2598              	@ 965 "Library/src/lcm32f06x_adc.c" 1
 2599 0010 C046     		nop
 2600              	@ 0 "" 2
 2601              		.loc 1 965 34 view .LVU766
 2602              	@ 965 "Library/src/lcm32f06x_adc.c" 1
 2603 0012 C046     		nop
 2604              	@ 0 "" 2
 2605              		.loc 1 965 43 view .LVU767
 2606              	@ 965 "Library/src/lcm32f06x_adc.c" 1
 2607 0014 C046     		nop
 2608              	@ 0 "" 2
 963:Library/src/lcm32f06x_adc.c ****     {
 2609              		.loc 1 963 12 view .LVU768
 963:Library/src/lcm32f06x_adc.c ****     {
 2610              		.loc 1 963 16 is_stmt 0 view .LVU769
 2611              		.thumb
 2612              		.syntax unified
 2613 0016 4369     		ldr	r3, [r0, #20]
 963:Library/src/lcm32f06x_adc.c ****     {
 2614              		.loc 1 963 12 view .LVU770
 2615 0018 1A42     		tst	r2, r3
 2616 001a F7D1     		bne	.L184
 2617              	.L183:
 966:Library/src/lcm32f06x_adc.c ****     };
 2618              		.loc 1 966 6 is_stmt 1 view .LVU771
 967:Library/src/lcm32f06x_adc.c ****     ADCx->ANA &= ~ADC_ANA_PD_REF_Msk;
 2619              		.loc 1 967 5 view .LVU772
 2620              		.loc 1 967 9 is_stmt 0 view .LVU773
 2621 001c 436A     		ldr	r3, [r0, #36]
 2622              		.loc 1 967 15 view .LVU774
 2623 001e 104A     		ldr	r2, .L201
 2624 0020 1340     		ands	r3, r2
 2625 0022 4362     		str	r3, [r0, #36]
 2626              	.L181:
 968:Library/src/lcm32f06x_adc.c ****   }
 969:Library/src/lcm32f06x_adc.c ****   else
 970:Library/src/lcm32f06x_adc.c ****   {
 971:Library/src/lcm32f06x_adc.c ****     ADCx->CR_b.STOP = 1;
 972:Library/src/lcm32f06x_adc.c ****     do
 973:Library/src/lcm32f06x_adc.c ****     {
 974:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 975:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 976:Library/src/lcm32f06x_adc.c ****     while (ADCx->CR & ADC_CR_START_Msk)
 977:Library/src/lcm32f06x_adc.c ****     {
 978:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
ARM GAS  /tmp/cclh89PE.s 			page 92


 979:Library/src/lcm32f06x_adc.c ****     };
 980:Library/src/lcm32f06x_adc.c ****     ADCx->ANA |= ADC_ANA_PD_REF_Msk;
 981:Library/src/lcm32f06x_adc.c ****   }
 982:Library/src/lcm32f06x_adc.c **** }
 2627              		.loc 1 982 1 view .LVU775
 2628              		@ sp needed
 2629 0024 7047     		bx	lr
 2630              	.L182:
 971:Library/src/lcm32f06x_adc.c ****     do
 2631              		.loc 1 971 5 is_stmt 1 view .LVU776
 971:Library/src/lcm32f06x_adc.c ****     do
 2632              		.loc 1 971 21 is_stmt 0 view .LVU777
 2633 0026 0822     		movs	r2, #8
 2634 0028 1343     		orrs	r3, r2
 2635 002a 4361     		str	r3, [r0, #20]
 2636              	.L186:
 972:Library/src/lcm32f06x_adc.c ****     {
 2637              		.loc 1 972 5 is_stmt 1 view .LVU778
 974:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 2638              		.loc 1 974 7 view .LVU779
 2639              		.syntax divided
 2640              	@ 974 "Library/src/lcm32f06x_adc.c" 1
 2641 002c C046     		nop
 2642              	@ 0 "" 2
 974:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 2643              		.loc 1 974 16 view .LVU780
 2644              	@ 974 "Library/src/lcm32f06x_adc.c" 1
 2645 002e C046     		nop
 2646              	@ 0 "" 2
 974:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 2647              		.loc 1 974 25 view .LVU781
 2648              	@ 974 "Library/src/lcm32f06x_adc.c" 1
 2649 0030 C046     		nop
 2650              	@ 0 "" 2
 974:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 2651              		.loc 1 974 34 view .LVU782
 2652              	@ 974 "Library/src/lcm32f06x_adc.c" 1
 2653 0032 C046     		nop
 2654              	@ 0 "" 2
 974:Library/src/lcm32f06x_adc.c ****     } while (ADCx->CR_b.STOP);
 2655              		.loc 1 974 43 view .LVU783
 2656              	@ 974 "Library/src/lcm32f06x_adc.c" 1
 2657 0034 C046     		nop
 2658              	@ 0 "" 2
 975:Library/src/lcm32f06x_adc.c ****     while (ADCx->CR & ADC_CR_START_Msk)
 2659              		.loc 1 975 14 discriminator 1 view .LVU784
 975:Library/src/lcm32f06x_adc.c ****     while (ADCx->CR & ADC_CR_START_Msk)
 2660              		.loc 1 975 24 is_stmt 0 discriminator 1 view .LVU785
 2661              		.thumb
 2662              		.syntax unified
 2663 0036 4369     		ldr	r3, [r0, #20]
 975:Library/src/lcm32f06x_adc.c ****     while (ADCx->CR & ADC_CR_START_Msk)
 2664              		.loc 1 975 14 discriminator 1 view .LVU786
 2665 0038 1B07     		lsls	r3, r3, #28
 2666 003a F7D4     		bmi	.L186
 976:Library/src/lcm32f06x_adc.c ****     {
 2667              		.loc 1 976 12 is_stmt 1 view .LVU787
ARM GAS  /tmp/cclh89PE.s 			page 93


 976:Library/src/lcm32f06x_adc.c ****     {
 2668              		.loc 1 976 16 is_stmt 0 view .LVU788
 2669 003c 4369     		ldr	r3, [r0, #20]
 976:Library/src/lcm32f06x_adc.c ****     {
 2670              		.loc 1 976 12 view .LVU789
 2671 003e 5B07     		lsls	r3, r3, #29
 2672 0040 08D5     		bpl	.L187
 976:Library/src/lcm32f06x_adc.c ****     {
 2673              		.loc 1 976 21 view .LVU790
 2674 0042 0422     		movs	r2, #4
 2675              	.L188:
 978:Library/src/lcm32f06x_adc.c ****     };
 2676              		.loc 1 978 7 is_stmt 1 view .LVU791
 2677              		.syntax divided
 2678              	@ 978 "Library/src/lcm32f06x_adc.c" 1
 2679 0044 C046     		nop
 2680              	@ 0 "" 2
 978:Library/src/lcm32f06x_adc.c ****     };
 2681              		.loc 1 978 16 view .LVU792
 2682              	@ 978 "Library/src/lcm32f06x_adc.c" 1
 2683 0046 C046     		nop
 2684              	@ 0 "" 2
 978:Library/src/lcm32f06x_adc.c ****     };
 2685              		.loc 1 978 25 view .LVU793
 2686              	@ 978 "Library/src/lcm32f06x_adc.c" 1
 2687 0048 C046     		nop
 2688              	@ 0 "" 2
 978:Library/src/lcm32f06x_adc.c ****     };
 2689              		.loc 1 978 34 view .LVU794
 2690              	@ 978 "Library/src/lcm32f06x_adc.c" 1
 2691 004a C046     		nop
 2692              	@ 0 "" 2
 978:Library/src/lcm32f06x_adc.c ****     };
 2693              		.loc 1 978 43 view .LVU795
 2694              	@ 978 "Library/src/lcm32f06x_adc.c" 1
 2695 004c C046     		nop
 2696              	@ 0 "" 2
 976:Library/src/lcm32f06x_adc.c ****     {
 2697              		.loc 1 976 12 view .LVU796
 976:Library/src/lcm32f06x_adc.c ****     {
 2698              		.loc 1 976 16 is_stmt 0 view .LVU797
 2699              		.thumb
 2700              		.syntax unified
 2701 004e 4369     		ldr	r3, [r0, #20]
 976:Library/src/lcm32f06x_adc.c ****     {
 2702              		.loc 1 976 12 view .LVU798
 2703 0050 1A42     		tst	r2, r3
 2704 0052 F7D1     		bne	.L188
 2705              	.L187:
 979:Library/src/lcm32f06x_adc.c ****     ADCx->ANA |= ADC_ANA_PD_REF_Msk;
 2706              		.loc 1 979 6 is_stmt 1 view .LVU799
 980:Library/src/lcm32f06x_adc.c ****   }
 2707              		.loc 1 980 5 view .LVU800
 980:Library/src/lcm32f06x_adc.c ****   }
 2708              		.loc 1 980 15 is_stmt 0 view .LVU801
 2709 0054 8023     		movs	r3, #128
 980:Library/src/lcm32f06x_adc.c ****   }
ARM GAS  /tmp/cclh89PE.s 			page 94


 2710              		.loc 1 980 9 view .LVU802
 2711 0056 426A     		ldr	r2, [r0, #36]
 980:Library/src/lcm32f06x_adc.c ****   }
 2712              		.loc 1 980 15 view .LVU803
 2713 0058 DB01     		lsls	r3, r3, #7
 2714 005a 1343     		orrs	r3, r2
 2715 005c 4362     		str	r3, [r0, #36]
 2716              		.loc 1 982 1 view .LVU804
 2717 005e E1E7     		b	.L181
 2718              	.L202:
 2719              		.align	2
 2720              	.L201:
 2721 0060 FFBFFFFF 		.word	-16385
 2722              		.cfi_endproc
 2723              	.LFE71:
 2725              		.section	.text.ADC_ForExternVref_Cmd,"ax",%progbits
 2726              		.align	1
 2727              		.p2align 2,,3
 2728              		.global	ADC_ForExternVref_Cmd
 2729              		.syntax unified
 2730              		.code	16
 2731              		.thumb_func
 2733              	ADC_ForExternVref_Cmd:
 2734              	.LVL194:
 2735              	.LFB72:
 983:Library/src/lcm32f06x_adc.c **** 
 984:Library/src/lcm32f06x_adc.c **** /**
 985:Library/src/lcm32f06x_adc.c ****   * @name   ADC_ForExternVref_Cmd(?????????????ADC?¦Ï?????????????)
 986:Library/src/lcm32f06x_adc.c ****   * @brief  EN: When other peripherals besides ADC require ADC reference voltage, the reference vol
 987:Library/src/lcm32f06x_adc.c ****   *         CN: ??ADC?????????????ADC?¦Ï???????????????ADC??¦Ï??????î•
 988:Library/src/lcm32f06x_adc.c ****   * @param  ADCx:
 989:Library/src/lcm32f06x_adc.c ****   *         EN: where x is 0 to select the ADC peripheral.
 990:Library/src/lcm32f06x_adc.c ****   *         CN: ???? x ?? 0 ????? ADC ???ÒÂ
 991:Library/src/lcm32f06x_adc.c ****   * @retval None
 992:Library/src/lcm32f06x_adc.c ****   */
 993:Library/src/lcm32f06x_adc.c **** void ADC_ForExternVref_Cmd(ADC_TypeDef *ADCx)
 994:Library/src/lcm32f06x_adc.c **** {
 2736              		.loc 1 994 1 is_stmt 1 view -0
 2737              		.cfi_startproc
 2738              		@ args = 0, pretend = 0, frame = 0
 2739              		@ frame_needed = 0, uses_anonymous_args = 0
 2740              		@ link register save eliminated.
 995:Library/src/lcm32f06x_adc.c ****   /* Set the PD_REF bit to Power on the ADC reference voltage module */
 996:Library/src/lcm32f06x_adc.c ****   while (ADCx->CR & ADC_CR_START_Msk)
 2741              		.loc 1 996 3 view .LVU806
 2742              		.loc 1 996 10 view .LVU807
 2743              		.loc 1 996 14 is_stmt 0 view .LVU808
 2744 0000 4369     		ldr	r3, [r0, #20]
 2745              		.loc 1 996 10 view .LVU809
 2746 0002 5B07     		lsls	r3, r3, #29
 2747 0004 08D5     		bpl	.L204
 2748              		.loc 1 996 19 view .LVU810
 2749 0006 0422     		movs	r2, #4
 2750              	.L205:
 997:Library/src/lcm32f06x_adc.c ****   {
 998:Library/src/lcm32f06x_adc.c ****       __NOP(); __NOP(); __NOP(); __NOP(); __NOP();
 2751              		.loc 1 998 7 is_stmt 1 view .LVU811
ARM GAS  /tmp/cclh89PE.s 			page 95


 2752              		.syntax divided
 2753              	@ 998 "Library/src/lcm32f06x_adc.c" 1
 2754 0008 C046     		nop
 2755              	@ 0 "" 2
 2756              		.loc 1 998 16 view .LVU812
 2757              	@ 998 "Library/src/lcm32f06x_adc.c" 1
 2758 000a C046     		nop
 2759              	@ 0 "" 2
 2760              		.loc 1 998 25 view .LVU813
 2761              	@ 998 "Library/src/lcm32f06x_adc.c" 1
 2762 000c C046     		nop
 2763              	@ 0 "" 2
 2764              		.loc 1 998 34 view .LVU814
 2765              	@ 998 "Library/src/lcm32f06x_adc.c" 1
 2766 000e C046     		nop
 2767              	@ 0 "" 2
 2768              		.loc 1 998 43 view .LVU815
 2769              	@ 998 "Library/src/lcm32f06x_adc.c" 1
 2770 0010 C046     		nop
 2771              	@ 0 "" 2
 996:Library/src/lcm32f06x_adc.c ****   {
 2772              		.loc 1 996 10 view .LVU816
 996:Library/src/lcm32f06x_adc.c ****   {
 2773              		.loc 1 996 14 is_stmt 0 view .LVU817
 2774              		.thumb
 2775              		.syntax unified
 2776 0012 4369     		ldr	r3, [r0, #20]
 996:Library/src/lcm32f06x_adc.c ****   {
 2777              		.loc 1 996 10 view .LVU818
 2778 0014 1A42     		tst	r2, r3
 2779 0016 F7D1     		bne	.L205
 2780              	.L204:
 999:Library/src/lcm32f06x_adc.c ****   };
 2781              		.loc 1 999 4 is_stmt 1 view .LVU819
1000:Library/src/lcm32f06x_adc.c ****   ADCx->ANA &= ~ADC_ANA_PD_REF_Msk;
 2782              		.loc 1 1000 3 view .LVU820
1001:Library/src/lcm32f06x_adc.c **** }
 2783              		.loc 1 1001 1 is_stmt 0 view .LVU821
 2784              		@ sp needed
1000:Library/src/lcm32f06x_adc.c ****   ADCx->ANA &= ~ADC_ANA_PD_REF_Msk;
 2785              		.loc 1 1000 7 view .LVU822
 2786 0018 436A     		ldr	r3, [r0, #36]
1000:Library/src/lcm32f06x_adc.c ****   ADCx->ANA &= ~ADC_ANA_PD_REF_Msk;
 2787              		.loc 1 1000 13 view .LVU823
 2788 001a 024A     		ldr	r2, .L211
 2789 001c 1340     		ands	r3, r2
 2790 001e 4362     		str	r3, [r0, #36]
 2791              		.loc 1 1001 1 view .LVU824
 2792 0020 7047     		bx	lr
 2793              	.L212:
 2794 0022 C046     		.align	2
 2795              	.L211:
 2796 0024 FFBFFFFF 		.word	-16385
 2797              		.cfi_endproc
 2798              	.LFE72:
 2800              		.section	.text.ADC_GetVTStemperature,"ax",%progbits
 2801              		.align	1
ARM GAS  /tmp/cclh89PE.s 			page 96


 2802              		.p2align 2,,3
 2803              		.global	ADC_GetVTStemperature
 2804              		.syntax unified
 2805              		.code	16
 2806              		.thumb_func
 2808              	ADC_GetVTStemperature:
 2809              	.LVL195:
 2810              	.LFB73:
1002:Library/src/lcm32f06x_adc.c **** 
1003:Library/src/lcm32f06x_adc.c **** /**
1004:Library/src/lcm32f06x_adc.c ****   * @name   ADC_GetVTStemperature
1005:Library/src/lcm32f06x_adc.c ****   * @brief  EN: ADC temperature sampling value converted to temperature.
1006:Library/src/lcm32f06x_adc.c ****   *         CN: ADC ???????????????
1007:Library/src/lcm32f06x_adc.c ****   * @param  ADCValueNow:
1008:Library/src/lcm32f06x_adc.c ****   *         EN: ADC current sampling temperature value.
1009:Library/src/lcm32f06x_adc.c ****   *         CN: ADC ?????????????
1010:Library/src/lcm32f06x_adc.c ****   * @param  Vref: 
1011:Library/src/lcm32f06x_adc.c ****   *         EN: Reference voltage selection.
1012:Library/src/lcm32f06x_adc.c ****   *         CN: ?¦Ï???????
1013:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ReferenceVoltage_3V2
1014:Library/src/lcm32f06x_adc.c ****   *             @arg ADC_ReferenceVoltage_4V9
1015:Library/src/lcm32f06x_adc.c ****   * @retval None
1016:Library/src/lcm32f06x_adc.c ****   */
1017:Library/src/lcm32f06x_adc.c **** int ADC_GetVTStemperature(int ADCValueNow, uint32_t Vref)
1018:Library/src/lcm32f06x_adc.c **** {
 2811              		.loc 1 1018 1 is_stmt 1 view -0
 2812              		.cfi_startproc
 2813              		@ args = 0, pretend = 0, frame = 0
 2814              		@ frame_needed = 0, uses_anonymous_args = 0
1019:Library/src/lcm32f06x_adc.c ****   int temperatureNormalADC4V9_3V2, temperatureHighADC4V9_3V2;
 2815              		.loc 1 1019 3 view .LVU826
1020:Library/src/lcm32f06x_adc.c ****   int slope, temperatureNormal, temperatureHigh, temperatureNormalADC, temperatureHighADC, temperat
 2816              		.loc 1 1020 3 view .LVU827
1021:Library/src/lcm32f06x_adc.c ****   temperatureNormal = (*(int *)(0x1FFFF780));
 2817              		.loc 1 1021 3 view .LVU828
1022:Library/src/lcm32f06x_adc.c ****   temperatureHigh = (*(int *)(0x1FFFF784));
 2818              		.loc 1 1022 3 view .LVU829
1023:Library/src/lcm32f06x_adc.c ****   temperatureNormalADC4V9_3V2 = (*(int *)(0x1FFFF7E0)); // 4.9V??3.2V???¦Ï???AD?????
 2819              		.loc 1 1023 3 view .LVU830
 2820              		.loc 1 1023 31 is_stmt 0 view .LVU831
 2821 0000 144B     		ldr	r3, .L221
1018:Library/src/lcm32f06x_adc.c ****   int temperatureNormalADC4V9_3V2, temperatureHighADC4V9_3V2;
 2822              		.loc 1 1018 1 view .LVU832
 2823 0002 70B5     		push	{r4, r5, r6, lr}
 2824              	.LCFI6:
 2825              		.cfi_def_cfa_offset 16
 2826              		.cfi_offset 4, -16
 2827              		.cfi_offset 5, -12
 2828              		.cfi_offset 6, -8
 2829              		.cfi_offset 14, -4
 2830              		.loc 1 1023 31 view .LVU833
 2831 0004 1B68     		ldr	r3, [r3]
 2832              	.LVL196:
1024:Library/src/lcm32f06x_adc.c ****   temperatureHighADC4V9_3V2 = (*(int *)(0x1FFFF7E4));   // 4.9V??3.2V???¦Ï???AD?????
 2833              		.loc 1 1024 3 is_stmt 1 view .LVU834
1025:Library/src/lcm32f06x_adc.c ****   if (temperatureNormalADC4V9_3V2 != 0xFFFFFFFF)
 2834              		.loc 1 1025 3 view .LVU835
ARM GAS  /tmp/cclh89PE.s 			page 97


1018:Library/src/lcm32f06x_adc.c ****   int temperatureNormalADC4V9_3V2, temperatureHighADC4V9_3V2;
 2835              		.loc 1 1018 1 is_stmt 0 view .LVU836
 2836 0006 0400     		movs	r4, r0
 2837 0008 0020     		movs	r0, #0
 2838              	.LVL197:
 2839              		.loc 1 1025 6 view .LVU837
 2840 000a 5D1C     		adds	r5, r3, #1
 2841 000c 1CD0     		beq	.L213
1024:Library/src/lcm32f06x_adc.c ****   temperatureHighADC4V9_3V2 = (*(int *)(0x1FFFF7E4));   // 4.9V??3.2V???¦Ï???AD?????
 2842              		.loc 1 1024 29 view .LVU838
 2843 000e 1248     		ldr	r0, .L221+4
 2844              	.LVL198:
1024:Library/src/lcm32f06x_adc.c ****   temperatureHighADC4V9_3V2 = (*(int *)(0x1FFFF7E4));   // 4.9V??3.2V???¦Ï???AD?????
 2845              		.loc 1 1024 29 view .LVU839
 2846 0010 0068     		ldr	r0, [r0]
 2847              	.LVL199:
1026:Library/src/lcm32f06x_adc.c ****   {
1027:Library/src/lcm32f06x_adc.c ****     switch (Vref)
 2848              		.loc 1 1027 5 is_stmt 1 view .LVU840
 2849 0012 0029     		cmp	r1, #0
 2850 0014 19D0     		beq	.L215
 2851 0016 8025     		movs	r5, #128
 2852 0018 AD02     		lsls	r5, r5, #10
 2853 001a A942     		cmp	r1, r5
 2854 001c 03D1     		bne	.L217
1028:Library/src/lcm32f06x_adc.c ****     {
1029:Library/src/lcm32f06x_adc.c ****     case ADC_ReferenceVoltage_3V2:
1030:Library/src/lcm32f06x_adc.c ****       temperatureNormalADC = temperatureNormalADC4V9_3V2 & 0x0000FFFF; // ??16¦Ë?¦Ï??3.2V
1031:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = temperatureHighADC4V9_3V2 & 0x0000FFFF;
1032:Library/src/lcm32f06x_adc.c ****       break;
1033:Library/src/lcm32f06x_adc.c **** 
1034:Library/src/lcm32f06x_adc.c ****     case ADC_ReferenceVoltage_4V9:
1035:Library/src/lcm32f06x_adc.c ****       temperatureNormalADC = (temperatureNormalADC4V9_3V2 & 0x0FFF0000) >> 16; // ??16¦Ë?¦Ï??4.9V
 2855              		.loc 1 1035 7 view .LVU841
 2856              		.loc 1 1035 28 is_stmt 0 view .LVU842
 2857 001e 1B01     		lsls	r3, r3, #4
 2858              	.LVL200:
1036:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = (temperatureHighADC4V9_3V2 & 0x0FFF0000) >> 16;
 2859              		.loc 1 1036 26 view .LVU843
 2860 0020 0001     		lsls	r0, r0, #4
 2861              	.LVL201:
1035:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = (temperatureHighADC4V9_3V2 & 0x0FFF0000) >> 16;
 2862              		.loc 1 1035 28 view .LVU844
 2863 0022 1E0D     		lsrs	r6, r3, #20
 2864              	.LVL202:
 2865              		.loc 1 1036 7 is_stmt 1 view .LVU845
 2866              		.loc 1 1036 26 is_stmt 0 view .LVU846
 2867 0024 020D     		lsrs	r2, r0, #20
 2868              	.LVL203:
1037:Library/src/lcm32f06x_adc.c ****       break;
 2869              		.loc 1 1037 7 is_stmt 1 view .LVU847
 2870              	.L217:
1038:Library/src/lcm32f06x_adc.c **** 
1039:Library/src/lcm32f06x_adc.c ****     default:
1040:Library/src/lcm32f06x_adc.c ****       break;
1041:Library/src/lcm32f06x_adc.c ****     }
1042:Library/src/lcm32f06x_adc.c ****     slope = ((temperatureHighADC - temperatureNormalADC) * 100) / (temperatureHigh - temperatureNor
ARM GAS  /tmp/cclh89PE.s 			page 98


1043:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2871              		.loc 1 1043 57 is_stmt 0 view .LVU848
 2872 0026 6420     		movs	r0, #100
1022:Library/src/lcm32f06x_adc.c ****   temperatureNormalADC4V9_3V2 = (*(int *)(0x1FFFF7E0)); // 4.9V??3.2V???¦Ï???AD?????
 2873              		.loc 1 1022 19 view .LVU849
 2874 0028 0C4B     		ldr	r3, .L221+8
 2875              	.LVL204:
 2876              		.loc 1 1043 35 view .LVU850
 2877 002a A41A     		subs	r4, r4, r2
 2878              	.LVL205:
1022:Library/src/lcm32f06x_adc.c ****   temperatureNormalADC4V9_3V2 = (*(int *)(0x1FFFF7E0)); // 4.9V??3.2V???¦Ï???AD?????
 2879              		.loc 1 1022 19 view .LVU851
 2880 002c 1D68     		ldr	r5, [r3]
 2881              	.LVL206:
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2882              		.loc 1 1042 5 is_stmt 1 view .LVU852
 2883              		.loc 1 1043 5 view .LVU853
1021:Library/src/lcm32f06x_adc.c ****   temperatureHigh = (*(int *)(0x1FFFF784));
 2884              		.loc 1 1021 21 is_stmt 0 view .LVU854
 2885 002e 0C4B     		ldr	r3, .L221+12
 2886              	.LVL207:
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2887              		.loc 1 1042 34 view .LVU855
 2888 0030 921B     		subs	r2, r2, r6
 2889              	.LVL208:
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2890              		.loc 1 1042 84 view .LVU856
 2891 0032 1968     		ldr	r1, [r3]
 2892              	.LVL209:
 2893              		.loc 1 1043 57 view .LVU857
 2894 0034 4443     		muls	r4, r0
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2895              		.loc 1 1042 84 view .LVU858
 2896 0036 691A     		subs	r1, r5, r1
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2897              		.loc 1 1042 58 view .LVU859
 2898 0038 5043     		muls	r0, r2
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2899              		.loc 1 1042 11 view .LVU860
 2900 003a FFF7FEFF 		bl	__aeabi_idiv
 2901              	.LVL210:
1042:Library/src/lcm32f06x_adc.c ****     temperatureNow = (ADCValueNow - temperatureHighADC) * 100 / slope + temperatureHigh;
 2902              		.loc 1 1042 11 view .LVU861
 2903 003e 0100     		movs	r1, r0
 2904              		.loc 1 1043 63 view .LVU862
 2905 0040 2000     		movs	r0, r4
 2906 0042 FFF7FEFF 		bl	__aeabi_idiv
 2907              	.LVL211:
 2908              		.loc 1 1043 20 view .LVU863
 2909 0046 4019     		adds	r0, r0, r5
 2910              	.LVL212:
 2911              	.L213:
1044:Library/src/lcm32f06x_adc.c ****   }
1045:Library/src/lcm32f06x_adc.c ****   return temperatureNow;
1046:Library/src/lcm32f06x_adc.c **** }
 2912              		.loc 1 1046 1 view .LVU864
 2913              		@ sp needed
ARM GAS  /tmp/cclh89PE.s 			page 99


 2914 0048 70BD     		pop	{r4, r5, r6, pc}
 2915              	.LVL213:
 2916              	.L215:
1030:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = temperatureHighADC4V9_3V2 & 0x0000FFFF;
 2917              		.loc 1 1030 7 is_stmt 1 view .LVU865
1030:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = temperatureHighADC4V9_3V2 & 0x0000FFFF;
 2918              		.loc 1 1030 28 is_stmt 0 view .LVU866
 2919 004a 1B04     		lsls	r3, r3, #16
 2920              	.LVL214:
1031:Library/src/lcm32f06x_adc.c ****       break;
 2921              		.loc 1 1031 26 view .LVU867
 2922 004c 0004     		lsls	r0, r0, #16
 2923              	.LVL215:
1030:Library/src/lcm32f06x_adc.c ****       temperatureHighADC = temperatureHighADC4V9_3V2 & 0x0000FFFF;
 2924              		.loc 1 1030 28 view .LVU868
 2925 004e 1E0C     		lsrs	r6, r3, #16
 2926              	.LVL216:
1031:Library/src/lcm32f06x_adc.c ****       break;
 2927              		.loc 1 1031 7 is_stmt 1 view .LVU869
1031:Library/src/lcm32f06x_adc.c ****       break;
 2928              		.loc 1 1031 26 is_stmt 0 view .LVU870
 2929 0050 020C     		lsrs	r2, r0, #16
 2930              	.LVL217:
1032:Library/src/lcm32f06x_adc.c **** 
 2931              		.loc 1 1032 7 is_stmt 1 view .LVU871
 2932 0052 E8E7     		b	.L217
 2933              	.L222:
 2934              		.align	2
 2935              	.L221:
 2936 0054 E0F7FF1F 		.word	536868832
 2937 0058 E4F7FF1F 		.word	536868836
 2938 005c 84F7FF1F 		.word	536868740
 2939 0060 80F7FF1F 		.word	536868736
 2940              		.cfi_endproc
 2941              	.LFE73:
 2943              		.text
 2944              	.Letext0:
 2945              		.file 3 "Library/inc/lcm32f06x.h"
 2946              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 2947              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 2948              		.file 6 "Library/inc/lcm32f06x_adc.h"
 2949              		.file 7 "Library/inc/lcm32f06x_rcc.h"
ARM GAS  /tmp/cclh89PE.s 			page 100


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_adc.c
     /tmp/cclh89PE.s:17     .text.ADC_DeInit:00000000 $t
     /tmp/cclh89PE.s:24     .text.ADC_DeInit:00000000 ADC_DeInit
     /tmp/cclh89PE.s:69     .text.ADC_DeInit:00000020 $d
     /tmp/cclh89PE.s:74     .text.ADC_Cmd:00000000 $t
     /tmp/cclh89PE.s:81     .text.ADC_Cmd:00000000 ADC_Cmd
     /tmp/cclh89PE.s:269    .text.ADC_Cmd:00000098 $d
     /tmp/cclh89PE.s:277    .text.ADC_StructInit:00000000 $t
     /tmp/cclh89PE.s:284    .text.ADC_StructInit:00000000 ADC_StructInit
     /tmp/cclh89PE.s:343    .text.ADC_Init:00000000 $t
     /tmp/cclh89PE.s:350    .text.ADC_Init:00000000 ADC_Init
     /tmp/cclh89PE.s:592    .text.ADC_Init:000000b8 $d
     /tmp/cclh89PE.s:601    .text.ADC_ExternTrigger_Config:00000000 $t
     /tmp/cclh89PE.s:608    .text.ADC_ExternTrigger_Config:00000000 ADC_ExternTrigger_Config
     /tmp/cclh89PE.s:713    .text.ADC_ExternTrigger_Config:00000044 $d
     /tmp/cclh89PE.s:719    .text.ADC_StopOfConversion:00000000 $t
     /tmp/cclh89PE.s:726    .text.ADC_StopOfConversion:00000000 ADC_StopOfConversion
     /tmp/cclh89PE.s:791    .text.ADC_StartOfConversion:00000000 $t
     /tmp/cclh89PE.s:798    .text.ADC_StartOfConversion:00000000 ADC_StartOfConversion
     /tmp/cclh89PE.s:916    .text.ADC_CloseAdc:00000000 $t
     /tmp/cclh89PE.s:923    .text.ADC_CloseAdc:00000000 ADC_CloseAdc
     /tmp/cclh89PE.s:1033   .text.ADC_GetConversionValue:00000000 $t
     /tmp/cclh89PE.s:1040   .text.ADC_GetConversionValue:00000000 ADC_GetConversionValue
     /tmp/cclh89PE.s:1108   .text.ADC_GetConversionValue:00000028 $d
     /tmp/cclh89PE.s:1113   .text.ADC_GetDMAValue:00000000 $t
     /tmp/cclh89PE.s:1120   .text.ADC_GetDMAValue:00000000 ADC_GetDMAValue
     /tmp/cclh89PE.s:1142   .text.ADC_SOC_Config_New:00000000 $t
     /tmp/cclh89PE.s:1149   .text.ADC_SOC_Config_New:00000000 ADC_SOC_Config_New
     /tmp/cclh89PE.s:1187   .text.ADC_SOC_Config:00000000 $t
     /tmp/cclh89PE.s:1194   .text.ADC_SOC_Config:00000000 ADC_SOC_Config
     /tmp/cclh89PE.s:1217   .rodata.ADC_SOC_Config:00000000 $d
     /tmp/cclh89PE.s:1512   .text.ADC_SOC_Config:000000d0 $d
     /tmp/cclh89PE.s:1517   .text.TrigSelect_Config:00000000 $t
     /tmp/cclh89PE.s:1524   .text.TrigSelect_Config:00000000 TrigSelect_Config
     /tmp/cclh89PE.s:1938   .text.TrigSelect_Config:000000b8 $d
     /tmp/cclh89PE.s:1947   .text.ADC_DMA_Cmd:00000000 $t
     /tmp/cclh89PE.s:1954   .text.ADC_DMA_Cmd:00000000 ADC_DMA_Cmd
     /tmp/cclh89PE.s:1990   .text.ADC_DMA_TransReq:00000000 $t
     /tmp/cclh89PE.s:1997   .text.ADC_DMA_TransReq:00000000 ADC_DMA_TransReq
     /tmp/cclh89PE.s:2030   .text.ADC_ITConfig:00000000 $t
     /tmp/cclh89PE.s:2037   .text.ADC_ITConfig:00000000 ADC_ITConfig
     /tmp/cclh89PE.s:2071   .text.ADC_SOC_ITConfig:00000000 $t
     /tmp/cclh89PE.s:2078   .text.ADC_SOC_ITConfig:00000000 ADC_SOC_ITConfig
     /tmp/cclh89PE.s:2112   .text.ADC_GetFlagStatus:00000000 $t
     /tmp/cclh89PE.s:2119   .text.ADC_GetFlagStatus:00000000 ADC_GetFlagStatus
     /tmp/cclh89PE.s:2156   .text.ADC_GetITStatus:00000000 $t
     /tmp/cclh89PE.s:2163   .text.ADC_GetITStatus:00000000 ADC_GetITStatus
     /tmp/cclh89PE.s:2206   .text.ADC_GetSOCITStatus:00000000 $t
     /tmp/cclh89PE.s:2213   .text.ADC_GetSOCITStatus:00000000 ADC_GetSOCITStatus
     /tmp/cclh89PE.s:2256   .text.ADC_ClearITPendingBit:00000000 $t
     /tmp/cclh89PE.s:2263   .text.ADC_ClearITPendingBit:00000000 ADC_ClearITPendingBit
     /tmp/cclh89PE.s:2282   .text.ADC_ClearSOCITPendingBit:00000000 $t
     /tmp/cclh89PE.s:2289   .text.ADC_ClearSOCITPendingBit:00000000 ADC_ClearSOCITPendingBit
     /tmp/cclh89PE.s:2308   .text.ADC_Trim:00000000 $t
     /tmp/cclh89PE.s:2315   .text.ADC_Trim:00000000 ADC_Trim
     /tmp/cclh89PE.s:2357   .text.ADC_Trim:0000001c $d
ARM GAS  /tmp/cclh89PE.s 			page 101


     /tmp/cclh89PE.s:2362   .text.ADC_SoftTrig:00000000 $t
     /tmp/cclh89PE.s:2369   .text.ADC_SoftTrig:00000000 ADC_SoftTrig
     /tmp/cclh89PE.s:2425   .text.ADC_AnalogWatchdogThresholdsConfg:00000000 $t
     /tmp/cclh89PE.s:2432   .text.ADC_AnalogWatchdogThresholdsConfg:00000000 ADC_AnalogWatchdogThresholdsConfg
     /tmp/cclh89PE.s:2480   .text.ADC_AnalogWatchdogSingleChannelConfig:00000000 $t
     /tmp/cclh89PE.s:2487   .text.ADC_AnalogWatchdogSingleChannelConfig:00000000 ADC_AnalogWatchdogSingleChannelConfig
     /tmp/cclh89PE.s:2561   .text.ADC_Vref_Cmd:00000000 $t
     /tmp/cclh89PE.s:2568   .text.ADC_Vref_Cmd:00000000 ADC_Vref_Cmd
     /tmp/cclh89PE.s:2721   .text.ADC_Vref_Cmd:00000060 $d
     /tmp/cclh89PE.s:2726   .text.ADC_ForExternVref_Cmd:00000000 $t
     /tmp/cclh89PE.s:2733   .text.ADC_ForExternVref_Cmd:00000000 ADC_ForExternVref_Cmd
     /tmp/cclh89PE.s:2796   .text.ADC_ForExternVref_Cmd:00000024 $d
     /tmp/cclh89PE.s:2801   .text.ADC_GetVTStemperature:00000000 $t
     /tmp/cclh89PE.s:2808   .text.ADC_GetVTStemperature:00000000 ADC_GetVTStemperature
     /tmp/cclh89PE.s:2936   .text.ADC_GetVTStemperature:00000054 $d

UNDEFINED SYMBOLS
RCC_APB0PeriphResetCmd
delay10us
__aeabi_idiv
