ARM GAS  /tmp/cciZ31jV.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"protocol.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "User/protocol.c"
  16              		.section	.rodata.__protocol_on_step.str1.4,"aMS",%progbits,1
  17              		.align	2
  18              	.LC4:
  19 0000 56414C55 		.ascii	"VALUE:%d\012\000"
  19      453A2564 
  19      0A00
  20              		.section	.text.__protocol_on_step,"ax",%progbits
  21              		.align	1
  22              		.p2align 2,,3
  23              		.syntax unified
  24              		.code	16
  25              		.thumb_func
  27              	__protocol_on_step:
  28              	.LFB63:
   1:User/protocol.c **** #include "protocol.h"
   2:User/protocol.c **** #include "lcm32f06x.h"
   3:User/protocol.c **** 
   4:User/protocol.c **** #include "string.h"
   5:User/protocol.c **** #include "dji.h"
   6:User/protocol.c **** #include "adc.h"
   7:User/protocol.c **** #include "global.h"
   8:User/protocol.c **** #include "uart.h"
   9:User/protocol.c **** #include "motor.h"
  10:User/protocol.c **** #include "B11A1.h"
  11:User/protocol.c **** 
  12:User/protocol.c **** static bool reset_flag = false;
  13:User/protocol.c **** 
  14:User/protocol.c **** #define PI (0x7FFFFFFF)
  15:User/protocol.c **** #define _PI (0x80000000)
  16:User/protocol.c **** #define PI_2 (0x40000000)
  17:User/protocol.c **** #define _PI_2 (0xC0000000)
  18:User/protocol.c **** 
  19:User/protocol.c **** // Q格式宏定义
  20:User/protocol.c **** #define Q31_BITS 31
  21:User/protocol.c **** #define Q16_BITS 16
  22:User/protocol.c **** #define Q15_BITS 15
  23:User/protocol.c **** #define Q8_BITS 8
  24:User/protocol.c **** 
  25:User/protocol.c **** #define MAX(a, b) (a > b ? a : b)
  26:User/protocol.c **** #define MIN(a, b) (a < b ? a : b)
  27:User/protocol.c **** #define SATURATION(x, min, max) MIN(MAX(x, min), max)
  28:User/protocol.c **** 
ARM GAS  /tmp/cciZ31jV.s 			page 2


  29:User/protocol.c **** // 通用浮点转Q格式宏 (支持任意小数位数)
  30:User/protocol.c **** #define FLOAT_TO_Q(x, bits) ((int32_t)((x) * (1 << (bits))))
  31:User/protocol.c **** 
  32:User/protocol.c **** // 通用Q格式转浮点宏 (支持任意小数位数)
  33:User/protocol.c **** #define Q_TO_FLOAT(x, bits) ((float)(x) / (1 << (bits)))
  34:User/protocol.c **** 
  35:User/protocol.c **** // 通用Q格式之间的转换宏
  36:User/protocol.c **** #define Q_CONVERT(x, from_bits, to_bits) \
  37:User/protocol.c ****     ((to_bits) > (from_bits) ? ((int32_t)(x) << ((to_bits) - (from_bits))) : ((x) >> ((from_bits) -
  38:User/protocol.c **** 
  39:User/protocol.c **** // 特定格式的浮点转Q格式 (保持向后兼容)
  40:User/protocol.c **** #define FLOAT_TO_Q31(x) FLOAT_TO_Q(x, Q31_BITS)
  41:User/protocol.c **** #define FLOAT_TO_Q16(x) FLOAT_TO_Q(x, Q16_BITS)
  42:User/protocol.c **** #define FLOAT_TO_Q15(x) ((int16_t)FLOAT_TO_Q(x, Q15_BITS))
  43:User/protocol.c **** #define FLOAT_TO_Q8(x) ((int16_t)FLOAT_TO_Q(x, Q8_BITS))
  44:User/protocol.c **** 
  45:User/protocol.c **** // 特定格式的Q格式转浮点 (保持向后兼容)
  46:User/protocol.c **** #define Q31_TO_FLOAT(x) Q_TO_FLOAT(x, Q31_BITS)
  47:User/protocol.c **** #define Q16_TO_FLOAT(x) Q_TO_FLOAT(x, Q16_BITS)
  48:User/protocol.c **** #define Q15_TO_FLOAT(x) Q_TO_FLOAT(x, Q15_BITS)
  49:User/protocol.c **** #define Q8_TO_FLOAT(x) Q_TO_FLOAT(x, Q8_BITS)
  50:User/protocol.c **** 
  51:User/protocol.c **** // 特定格式之间的转换 (保持向后兼容)
  52:User/protocol.c **** #define Q31_TO_Q16(x) Q_CONVERT(x, Q31_BITS, Q16_BITS)
  53:User/protocol.c **** #define Q16_TO_Q31(x) Q_CONVERT(x, Q16_BITS, Q31_BITS)
  54:User/protocol.c **** #define Q16_TO_Q15(x) Q_CONVERT(x, Q16_BITS, Q15_BITS)
  55:User/protocol.c **** #define Q15_TO_Q16(x) Q_CONVERT(x, Q15_BITS, Q16_BITS)
  56:User/protocol.c **** 
  57:User/protocol.c **** /**
  58:User/protocol.c ****  * @brief 处理0x01命令 - 获取版本信息
  59:User/protocol.c ****  * @param self DJI实例
  60:User/protocol.c ****  * @param message 接收到的消息
  61:User/protocol.c ****  * @note 返回硬件版本号、loader版本、app版本信息
  62:User/protocol.c ****  */
  63:User/protocol.c **** static void __protocol_0x01_echo(dji_t self, dji_message_t message)
  64:User/protocol.c **** {
  65:User/protocol.c **** #pragma pack(1)
  66:User/protocol.c **** 
  67:User/protocol.c ****     static struct
  68:User/protocol.c ****     {
  69:User/protocol.c ****         uint8_t code;      // 返回码
  70:User/protocol.c ****         char hardware[16]; // 硬件版本号
  71:User/protocol.c ****         uint16_t loader;   // Loader版本
  72:User/protocol.c ****         uint16_t app;      // APP版本
  73:User/protocol.c ****     } echo = {
  74:User/protocol.c ****         .code = 0x00,
  75:User/protocol.c ****         .app = APP_VERSION,
  76:User/protocol.c ****     };
  77:User/protocol.c **** 
  78:User/protocol.c **** #pragma pack()
  79:User/protocol.c **** 
  80:User/protocol.c ****     memcpy(&echo.hardware, (uint8_t *)ADDR_VER_HW, sizeof(echo.hardware));
  81:User/protocol.c ****     memcpy(&echo.loader, (uint8_t *)ADDR_VER_LD, sizeof(echo.loader));
  82:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
  83:User/protocol.c **** }
  84:User/protocol.c **** 
  85:User/protocol.c **** /**
ARM GAS  /tmp/cciZ31jV.s 			page 3


  86:User/protocol.c ****  * @brief 处理0x03命令 - 设置SN码
  87:User/protocol.c ****  * @param self DJI实例
  88:User/protocol.c ****  * @param message 接收到的消息，包含14字节序列号
  89:User/protocol.c ****  * @note 设置扫地机无刷行走轮序列号，返回设置结果
  90:User/protocol.c ****  */
  91:User/protocol.c **** static void __protocol_0x03_echo(dji_t self, dji_message_t message)
  92:User/protocol.c **** {
  93:User/protocol.c ****     uint8_t echo;
  94:User/protocol.c ****     if (message->len != sizeof(g_save.activate.sn))
  95:User/protocol.c ****     {
  96:User/protocol.c ****         echo = 0x01; // 设置SN码失败
  97:User/protocol.c ****     }
  98:User/protocol.c ****     else
  99:User/protocol.c ****     {
 100:User/protocol.c ****         echo = 0x00; // 设置成功
 101:User/protocol.c ****         memcpy(g_save.activate.sn, message->data, message->len);
 102:User/protocol.c ****         save_write();
 103:User/protocol.c ****     }
 104:User/protocol.c ****     dji_echo(self, &echo, 1);
 105:User/protocol.c **** }
 106:User/protocol.c **** 
 107:User/protocol.c **** /**
 108:User/protocol.c ****  * @brief 处理0x04命令 - 读取SN码
 109:User/protocol.c ****  * @param self DJI实例
 110:User/protocol.c ****  * @param message 接收到的消息
 111:User/protocol.c ****  * @note 获取扫地机无刷行走轮序列号
 112:User/protocol.c ****  */
 113:User/protocol.c **** static void __protocol_0x04_echo(dji_t self, dji_message_t message)
 114:User/protocol.c **** {
 115:User/protocol.c **** #pragma pack(1)
 116:User/protocol.c ****     struct
 117:User/protocol.c ****     {
 118:User/protocol.c ****         uint8_t code; // 返回码
 119:User/protocol.c ****         char sn[14];  // 序列号
 120:User/protocol.c ****     } echo = {.code = 0x00};
 121:User/protocol.c **** #pragma pack()
 122:User/protocol.c ****     memcpy(echo.sn, g_save.activate.sn, sizeof(echo.sn));
 123:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 124:User/protocol.c **** }
 125:User/protocol.c **** 
 126:User/protocol.c **** /**
 127:User/protocol.c ****  * @brief 处理0x05命令 - 获取激活状态
 128:User/protocol.c ****  * @param self DJI实例
 129:User/protocol.c ****  * @param message 接收到的消息
 130:User/protocol.c ****  * @note 检查扫地机无刷行走轮是否已激活，返回激活状态和时间信息
 131:User/protocol.c ****  */
 132:User/protocol.c **** static void __protocol_0x05_echo(dji_t self, dji_message_t message)
 133:User/protocol.c **** {
 134:User/protocol.c **** 
 135:User/protocol.c **** #pragma pack(1)
 136:User/protocol.c ****     struct
 137:User/protocol.c ****     {
 138:User/protocol.c ****         uint8_t state;  // 激活状态：0=已激活，1=未激活
 139:User/protocol.c ****         uint16_t year;  // 年份（未激活时为0）
 140:User/protocol.c ****         uint8_t month;  // 月份
 141:User/protocol.c ****         uint8_t day;    // 日期
 142:User/protocol.c ****         uint8_t hour;   // 小时
ARM GAS  /tmp/cciZ31jV.s 			page 4


 143:User/protocol.c ****         uint8_t minute; // 分钟
 144:User/protocol.c ****         uint8_t second; // 秒
 145:User/protocol.c ****         uint8_t sn[14]; // 序列号
 146:User/protocol.c ****     } echo = {.state = g_save.activate.state};
 147:User/protocol.c **** #pragma pack()
 148:User/protocol.c **** 
 149:User/protocol.c ****     echo.year = g_save.activate.year;
 150:User/protocol.c ****     echo.month = g_save.activate.month;
 151:User/protocol.c ****     echo.day = g_save.activate.day;
 152:User/protocol.c ****     echo.hour = g_save.activate.hour;
 153:User/protocol.c ****     echo.minute = g_save.activate.minute;
 154:User/protocol.c ****     echo.second = g_save.activate.second;
 155:User/protocol.c ****     memcpy(echo.sn, g_save.activate.sn, sizeof(echo.sn));
 156:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 157:User/protocol.c **** }
 158:User/protocol.c **** 
 159:User/protocol.c **** /**
 160:User/protocol.c ****  * @brief 处理0x06命令 - 设置激活状态
 161:User/protocol.c ****  * @param self DJI实例
 162:User/protocol.c ****  * @param message 接收到的消息，包含激活时间信息（7字节）
 163:User/protocol.c ****  * @note 激活扫地机无刷行走轮，设置激活时间
 164:User/protocol.c ****  */
 165:User/protocol.c **** static void __protocol_0x06_echo(dji_t self, dji_message_t message)
 166:User/protocol.c **** {
 167:User/protocol.c **** #pragma pack(1)
 168:User/protocol.c ****     struct
 169:User/protocol.c ****     {
 170:User/protocol.c ****         uint8_t code;   // 返回码：0=激活成功，其他=激活失败
 171:User/protocol.c ****         uint16_t year;  // 年份
 172:User/protocol.c ****         uint8_t month;  // 月份
 173:User/protocol.c ****         uint8_t day;    // 日期
 174:User/protocol.c ****         uint8_t hour;   // 小时
 175:User/protocol.c ****         uint8_t minute; // 分钟
 176:User/protocol.c ****         uint8_t second; // 秒
 177:User/protocol.c ****         char sn[14];    // 序列号
 178:User/protocol.c ****     } echo;
 179:User/protocol.c **** #pragma pack()
 180:User/protocol.c **** 
 181:User/protocol.c ****     if (message->len == 7)
 182:User/protocol.c ****     {
 183:User/protocol.c ****         echo.code = 0x00; // 激活成功
 184:User/protocol.c ****         memcpy(&echo.year, message->data, 7);
 185:User/protocol.c ****         g_save.activate.state = false;
 186:User/protocol.c ****         g_save.activate.year = echo.year;
 187:User/protocol.c ****         g_save.activate.month = echo.month;
 188:User/protocol.c ****         g_save.activate.day = echo.day;
 189:User/protocol.c ****         g_save.activate.hour = echo.hour;
 190:User/protocol.c ****         g_save.activate.minute = echo.minute;
 191:User/protocol.c ****         g_save.activate.second = echo.second;
 192:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 193:User/protocol.c ****         save_write();
 194:User/protocol.c ****     }
 195:User/protocol.c ****     else
 196:User/protocol.c ****     {
 197:User/protocol.c ****         echo.code = 0x01; // 激活失败
 198:User/protocol.c ****         echo.year = g_save.activate.year;
 199:User/protocol.c ****         echo.month = g_save.activate.month;
ARM GAS  /tmp/cciZ31jV.s 			page 5


 200:User/protocol.c ****         echo.day = g_save.activate.day;
 201:User/protocol.c ****         echo.hour = g_save.activate.hour;
 202:User/protocol.c ****         echo.minute = g_save.activate.minute;
 203:User/protocol.c ****         echo.second = g_save.activate.second;
 204:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 205:User/protocol.c ****     }
 206:User/protocol.c **** 
 207:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 208:User/protocol.c **** }
 209:User/protocol.c **** 
 210:User/protocol.c **** /**
 211:User/protocol.c ****  * @brief 处理0x07命令 - 反激活
 212:User/protocol.c ****  * @param self DJI实例
 213:User/protocol.c ****  * @param message 接收到的消息
 214:User/protocol.c ****  * @note 扫地机无刷行走轮反激活操作
 215:User/protocol.c ****  */
 216:User/protocol.c **** static void __protocol_0x07_echo(dji_t self, dji_message_t message)
 217:User/protocol.c **** {
 218:User/protocol.c **** 
 219:User/protocol.c ****     uint8_t echo = 0x00;
 220:User/protocol.c ****     g_save.activate.state = true;
 221:User/protocol.c ****     memset(&g_save.activate, 0, sizeof(g_save.activate));
 222:User/protocol.c ****     save_write();
 223:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 224:User/protocol.c **** }
 225:User/protocol.c **** 
 226:User/protocol.c **** /**
 227:User/protocol.c ****  * @brief 处理0x12命令 - 霍尔标定
 228:User/protocol.c ****  * @param self DJI实例
 229:User/protocol.c ****  * @param message 接收到的消息，包含操作类型（1字节）
 230:User/protocol.c ****  * @note 霍尔标定控制：1=查询校准状态，2=开始校准
 231:User/protocol.c ****  */
 232:User/protocol.c **** static void __protocol_0x12_echo(dji_t self, dji_message_t message)
 233:User/protocol.c **** {
 234:User/protocol.c **** 
 235:User/protocol.c ****     uint8_t echo;
 236:User/protocol.c **** 
 237:User/protocol.c ****     if (message->len != 1)
 238:User/protocol.c ****     {
 239:User/protocol.c ****         return;
 240:User/protocol.c ****     }
 241:User/protocol.c ****     else if (message->data[0] == 1)
 242:User/protocol.c ****     {
 243:User/protocol.c ****         echo = B11A1_Y.Info.CaliFlag;
 244:User/protocol.c ****     }
 245:User/protocol.c ****     else if (message->data[0] == 2)
 246:User/protocol.c ****     {
 247:User/protocol.c ****         echo = B11A1_Y.Info.CaliFlag;
 248:User/protocol.c ****         Save.Flag = NoStoredInfo;
 249:User/protocol.c ****         B11A1_U.Control.Mode = CalibrationMode;
 250:User/protocol.c ****     }
 251:User/protocol.c ****     else
 252:User/protocol.c ****     {
 253:User/protocol.c ****         return;
 254:User/protocol.c ****     }
 255:User/protocol.c **** 
 256:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
ARM GAS  /tmp/cciZ31jV.s 			page 6


 257:User/protocol.c **** }
 258:User/protocol.c **** 
 259:User/protocol.c **** /**
 260:User/protocol.c ****  * @brief 处理0x13命令 - 读写霍尔标定信息
 261:User/protocol.c ****  * @param self DJI实例
 262:User/protocol.c ****  * @param message 接收到的消息，包含操作类型（1字节）
 263:User/protocol.c ****  * @note 霍尔标定信息操作：0=读取标定信息，1=清除标定信息
 264:User/protocol.c ****  */
 265:User/protocol.c **** static void __protocol_0x13_echo(dji_t self, dji_message_t message)
 266:User/protocol.c **** {
 267:User/protocol.c **** #pragma pack(1)
 268:User/protocol.c ****     struct
 269:User/protocol.c ****     {
 270:User/protocol.c ****         uint8_t state;          // 信息状态：0=无校准信息，1=有校准信息
 271:User/protocol.c ****         int16_t hall_a_max;     // hall_A 最大值
 272:User/protocol.c ****         int16_t hall_a_min;     // hall_A 最小值
 273:User/protocol.c ****         int16_t hall_b_max;     // hall_B 最大值
 274:User/protocol.c ****         int16_t hall_b_min;     // hall_B 最小值
 275:User/protocol.c ****         int16_t angle_bias;     // 电角度偏置
 276:User/protocol.c ****         int16_t current_a_bias; // A相电流偏置
 277:User/protocol.c ****         int16_t current_b_bias; // B相电流偏置
 278:User/protocol.c ****     } echo = {0};
 279:User/protocol.c **** #pragma pack()
 280:User/protocol.c **** 
 281:User/protocol.c ****     if (message->len != 1)
 282:User/protocol.c ****     {
 283:User/protocol.c ****         return;
 284:User/protocol.c ****     }
 285:User/protocol.c ****     else if (message->data[0] == 0)
 286:User/protocol.c ****     {
 287:User/protocol.c ****         echo.state = g_save.motor.state;
 288:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 289:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 290:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 291:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 292:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
 293:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 294:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 295:User/protocol.c ****     }
 296:User/protocol.c ****     else if (message->data[0] == 1)
 297:User/protocol.c ****     {
 298:User/protocol.c ****         Save.Flag = NoStoredInfo;
 299:User/protocol.c ****         g_save.motor.state = false;
 300:User/protocol.c ****         echo.state = g_save.motor.state;
 301:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 302:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 303:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 304:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 305:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
 306:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 307:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 308:User/protocol.c ****         save_write();
 309:User/protocol.c ****     }
 310:User/protocol.c ****     else
 311:User/protocol.c ****     {
 312:User/protocol.c ****         return;
 313:User/protocol.c ****     }
ARM GAS  /tmp/cciZ31jV.s 			page 7


 314:User/protocol.c **** 
 315:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 316:User/protocol.c **** }
 317:User/protocol.c **** 
 318:User/protocol.c **** /**
 319:User/protocol.c ****  * @brief 处理0x15命令 - 获取异常状态
 320:User/protocol.c ****  * @param self DJI实例
 321:User/protocol.c ****  * @param message 接收到的消息
 322:User/protocol.c ****  * @note 获取电机异常状态：[2]温度异常，[1]电压异常，[0]过流异常
 323:User/protocol.c ****  */
 324:User/protocol.c **** static void __protocol_0x15_echo(dji_t self, dji_message_t message)
 325:User/protocol.c **** {
 326:User/protocol.c ****     uint8_t fault = motor_get_fault();
 327:User/protocol.c ****     dji_echo(self, &fault, sizeof(fault));
 328:User/protocol.c **** }
 329:User/protocol.c **** 
 330:User/protocol.c **** /**
 331:User/protocol.c ****  * @brief 处理0x16命令 - 清除异常状态
 332:User/protocol.c ****  * @param self DJI实例
 333:User/protocol.c ****  * @param message 接收到的消息，包含清除标志（1字节）
 334:User/protocol.c ****  * @note 清除电机异常状态：[2]清除温度异常，[1]清除电压异常，[0]清除过流
 335:User/protocol.c ****  */
 336:User/protocol.c **** static void __protocol_0x16_echo(dji_t self, dji_message_t message)
 337:User/protocol.c **** {
 338:User/protocol.c **** 
 339:User/protocol.c ****     uint8_t echo = 1; // 默认失败
 340:User/protocol.c ****     if (message->len < 1)
 341:User/protocol.c ****         return;
 342:User/protocol.c ****     echo = motor_reset_fault(message->data[0]);
 343:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 344:User/protocol.c **** }
 345:User/protocol.c **** 
 346:User/protocol.c **** /**
 347:User/protocol.c ****  * @brief 处理0x17命令 - UID读取
 348:User/protocol.c ****  * @param self DJI实例
 349:User/protocol.c ****  * @param message 接收到的消息
 350:User/protocol.c ****  * @note 预留命令，可根据具体需求实现相应功能
 351:User/protocol.c ****  */
 352:User/protocol.c **** static void __protocol_0x17_echo(dji_t self, dji_message_t message)
 353:User/protocol.c **** {
 354:User/protocol.c ****     // LCM32F06x系列MCU的UID寄存器地址
 355:User/protocol.c ****     // 根据具体芯片手册调整地址
 356:User/protocol.c ****     // UID基地址，需要根据实际芯片调整
 357:User/protocol.c **** #define UID_BASE_ADDR 0x1FFFF7B0
 358:User/protocol.c ****     uint8_t echo[12];
 359:User/protocol.c ****     memcpy(echo, (uint8_t *)UID_BASE_ADDR, sizeof(echo));
 360:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 361:User/protocol.c **** }
 362:User/protocol.c **** 
 363:User/protocol.c **** /**
 364:User/protocol.c ****  * @brief 处理0x18命令 - 获取版本
 365:User/protocol.c ****  * @param self DJI实例
 366:User/protocol.c ****  * @param message 接收到的消息
 367:User/protocol.c ****  * @note 获取当前电机转速，返回rpm*100格式的速度值（有符号32位整数）
 368:User/protocol.c ****  */
 369:User/protocol.c **** static void __protocol_0x18_echo(dji_t self, dji_message_t message)
 370:User/protocol.c **** {
ARM GAS  /tmp/cciZ31jV.s 			page 8


 371:User/protocol.c ****     uart_printf("Firmware compilation time :%s %s", __DATE__, __TIME__);
 372:User/protocol.c **** }
 373:User/protocol.c **** 
 374:User/protocol.c **** /**
 375:User/protocol.c ****  * @brief 处理0x20命令 - 电机控制指令
 376:User/protocol.c ****  * @param self DJI实例
 377:User/protocol.c ****  * @param message 接收到的消息，包含电机控制参数（3字节）
 378:User/protocol.c ****  * @note 控制扫地机无刷行走轮，设置电机状态和目标值，返回电机运行状态
 379:User/protocol.c ****  */
 380:User/protocol.c **** static void __protocol_0x20_echo(dji_t self, dji_message_t message)
 381:User/protocol.c **** {
 382:User/protocol.c **** 
 383:User/protocol.c **** #pragma pack(1)
 384:User/protocol.c ****     struct
 385:User/protocol.c ****     {
 386:User/protocol.c ****         uint8_t mode;
 387:User/protocol.c ****         int16_t target;
 388:User/protocol.c ****     } *recv = (void *)message->data;
 389:User/protocol.c ****     struct
 390:User/protocol.c ****     {
 391:User/protocol.c ****         uint8_t state;      // 电机控制模式：0=非使能，1=开环控制，2=电流环控�
 392:User/protocol.c ****         uint8_t fault;      // 故障状态：[2]温度异常，[1]电压异常，[0]过流异常
 393:User/protocol.c ****         int16_t target;     // 接收到的目标值
 394:User/protocol.c ****         int16_t dc_voltage; // 母线电压 mV
 395:User/protocol.c ****         int16_t temp;       // 电机温度 摄氏度 × 100
 396:User/protocol.c ****         int16_t velocity;   // 电机速度(有符号，rpm × 100)
 397:User/protocol.c ****         int16_t current;    // 相电流 Is
 398:User/protocol.c ****         int16_t voltage;    // 电压 单位 mV
 399:User/protocol.c ****     } echo;
 400:User/protocol.c **** #pragma pack()
 401:User/protocol.c **** 
 402:User/protocol.c ****     if (message->len < 3)
 403:User/protocol.c ****     {
 404:User/protocol.c ****         B11A1_U.Control.Mode = StopMode;
 405:User/protocol.c ****     }
 406:User/protocol.c ****     else
 407:User/protocol.c ****     {
 408:User/protocol.c ****         B11A1_U.Control.Mode = recv->mode;
 409:User/protocol.c ****         switch (B11A1_U.Control.Mode)
 410:User/protocol.c ****         {
 411:User/protocol.c ****         case StopMode:
 412:User/protocol.c ****             break;
 413:User/protocol.c ****         case VoltageMode:
 414:User/protocol.c ****             B11A1_U.Control.Udq[1] = ((int)SATURATION(recv->target, -9000, 8999) << 15) / 9000;
 415:User/protocol.c ****             break;
 416:User/protocol.c ****         case CurrentMode:
 417:User/protocol.c ****             B11A1_U.Control.Idq[1] = ((int)SATURATION(recv->target, -4500, 4499) << 15) / 4500;
 418:User/protocol.c ****             break;
 419:User/protocol.c ****         case VelocityMode:
 420:User/protocol.c ****             B11A1_U.Control.Velocity = ((int)SATURATION(recv->target, -30000, 29999) << 15) / 30000
 421:User/protocol.c ****             break;
 422:User/protocol.c ****         case PositionMode:
 423:User/protocol.c ****             break;
 424:User/protocol.c ****         }
 425:User/protocol.c ****     }
 426:User/protocol.c **** 
 427:User/protocol.c ****     echo.state = B11A1_U.Control.Mode;
ARM GAS  /tmp/cciZ31jV.s 			page 9


 428:User/protocol.c ****     echo.fault = motor_get_fault();
 429:User/protocol.c ****     echo.target = recv->target;
 430:User/protocol.c ****     echo.dc_voltage = SATURATION(B11A1_Y.Info.Udc, -32768, 32767);
 431:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 432:User/protocol.c ****     echo.voltage = SATURATION(B11A1_Y.Info.Udq[1], -32768, 32767);
 433:User/protocol.c ****     echo.velocity = SATURATION(B11A1_Y.Info.Velocity, -32768, 32767);
 434:User/protocol.c ****     echo.temp = B11A1_Y.Info.Temp;
 435:User/protocol.c ****     // echo.temp = ADC_GetVTStemperature(INTERNALTEMPSENSOR, ADC_ReferenceVoltage_4V9)*100; // ADC_
 436:User/protocol.c ****     // echo.velocity = ADC_GetVTStemperature(INTERNALTEMPSENSOR, ADC_ReferenceVoltage_4V9) * 100;
 437:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 438:User/protocol.c **** }
 439:User/protocol.c **** static void __protocol_0x21_echo(dji_t self, dji_message_t message)
 440:User/protocol.c **** {
 441:User/protocol.c **** #pragma pack(1)
 442:User/protocol.c ****     struct
 443:User/protocol.c ****     {
 444:User/protocol.c ****         uint8_t reset;
 445:User/protocol.c ****         uint16_t kp;
 446:User/protocol.c ****         uint16_t ki;
 447:User/protocol.c ****         int16_t res[4];
 448:User/protocol.c ****     } *recv = (void *)message->data;
 449:User/protocol.c ****     struct
 450:User/protocol.c ****     {
 451:User/protocol.c ****         uint8_t reset;
 452:User/protocol.c ****         uint16_t kp;
 453:User/protocol.c ****         uint16_t ki;
 454:User/protocol.c ****         int16_t res[4];
 455:User/protocol.c ****     } echo = {.res = 0};
 456:User/protocol.c **** #pragma pack()
 457:User/protocol.c ****     if (message->len < sizeof(recv))
 458:User/protocol.c ****     {
 459:User/protocol.c ****         dji_echo(self, &echo, sizeof(echo));
 460:User/protocol.c ****         return;
 461:User/protocol.c ****     }
 462:User/protocol.c ****     switch (recv->reset)
 463:User/protocol.c ****     {
 464:User/protocol.c **** 
 465:User/protocol.c ****     case 0:
 466:User/protocol.c ****         B11A1_U.Control.ResetPI = true;
 467:User/protocol.c ****         B11A1_U.Control.ResetLPF = true;
 468:User/protocol.c ****         break;
 469:User/protocol.c **** 
 470:User/protocol.c ****     case 1:
 471:User/protocol.c ****         B11A1_U.Control.ResetPI = true;
 472:User/protocol.c ****         break;
 473:User/protocol.c **** 
 474:User/protocol.c ****         // case 2:
 475:User/protocol.c ****         //     Save.Info.VelocityConfig.Kp = MOTOR_DEFAULT_VELOCITY_KP;
 476:User/protocol.c ****         //     Save.Info.VelocityConfig.Ki = MOTOR_DEFAULT_VELOCITY_KI;
 477:User/protocol.c ****         //     break;
 478:User/protocol.c **** 
 479:User/protocol.c ****     case 3:
 480:User/protocol.c ****         Save.Info.VelocityConfig.Kp = SATURATION((recv->kp * 29606.8517647058f), 0, FLOAT_TO_Q(20.0
 481:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 482:User/protocol.c ****         break;
 483:User/protocol.c **** 
 484:User/protocol.c ****     default:
ARM GAS  /tmp/cciZ31jV.s 			page 10


 485:User/protocol.c ****         break;
 486:User/protocol.c ****     }
 487:User/protocol.c **** 
 488:User/protocol.c ****     echo.reset = recv->reset;
 489:User/protocol.c ****     echo.kp = (uint16_t)(Save.Info.VelocityConfig.Kp / 296068.517647058f);
 490:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 491:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 492:User/protocol.c **** }
 493:User/protocol.c **** 
 494:User/protocol.c **** /**
 495:User/protocol.c ****  * @brief 处理0x70命令 - 进入升级模式
 496:User/protocol.c ****  * @param self DJI实例
 497:User/protocol.c ****  * @param message 接收到的消息，包含升级文件大小（4字节）
 498:User/protocol.c ****  * @note 准备进入固件升级模式
 499:User/protocol.c ****  */
 500:User/protocol.c **** static void __protocol_0x70_echo(dji_t self, dji_message_t message)
 501:User/protocol.c **** {
 502:User/protocol.c **** #pragma pack(1)
 503:User/protocol.c ****     struct
 504:User/protocol.c ****     {
 505:User/protocol.c ****         uint8_t code;           // 返回码：0=进入升级成功，1=进入升级失败
 506:User/protocol.c ****         uint16_t max_pack_size; // 最大包大小
 507:User/protocol.c ****     } echo = {0};
 508:User/protocol.c **** #pragma pack()
 509:User/protocol.c **** 
 510:User/protocol.c ****     if (*(uint32_t *)message->data < MAX_APP_SIZE)
 511:User/protocol.c ****     {
 512:User/protocol.c ****         echo.code = 0x00; // 响应进入升级
 513:User/protocol.c ****     }
 514:User/protocol.c ****     else
 515:User/protocol.c ****     {
 516:User/protocol.c ****         echo.code = 0x01; // 响应进入升级失败
 517:User/protocol.c ****     }
 518:User/protocol.c ****     echo.max_pack_size = MAX_UPDATE_PACK_SIZE;
 519:User/protocol.c **** 
 520:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 521:User/protocol.c **** }
 522:User/protocol.c **** 
 523:User/protocol.c **** /**
 524:User/protocol.c ****  * @brief 处理0x71命令 - 当前升级状态
 525:User/protocol.c ****  * @param self DJI实例
 526:User/protocol.c ****  * @param message 接收到的消息
 527:User/protocol.c ****  * @note 获取当前固件升级状态
 528:User/protocol.c ****  */
 529:User/protocol.c **** static void __protocol_0x71_echo(dji_t self, dji_message_t message)
 530:User/protocol.c **** {
 531:User/protocol.c **** #pragma pack(1)
 532:User/protocol.c ****     struct
 533:User/protocol.c ****     {
 534:User/protocol.c ****         uint8_t code; // 返回码：0=升级数据包接收成功
 535:User/protocol.c ****     } echo = {.code = 0x00};
 536:User/protocol.c **** #pragma pack()
 537:User/protocol.c **** 
 538:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 539:User/protocol.c **** }
 540:User/protocol.c **** 
 541:User/protocol.c **** static void __protocol_0x72_echo(dji_t self, dji_message_t message)
ARM GAS  /tmp/cciZ31jV.s 			page 11


 542:User/protocol.c **** {
 543:User/protocol.c **** #pragma pack(1)
 544:User/protocol.c ****     struct
 545:User/protocol.c ****     {
 546:User/protocol.c ****         uint8_t data;
 547:User/protocol.c ****     } echo = {.data = false};
 548:User/protocol.c **** #pragma pack()
 549:User/protocol.c ****     reset_flag = true;
 550:User/protocol.c ****     save_flag(0);
 551:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 552:User/protocol.c **** }
 553:User/protocol.c **** 
 554:User/protocol.c **** /**
 555:User/protocol.c ****  * @brief DJI消息处理函数
 556:User/protocol.c ****  * @param self DJI实例
 557:User/protocol.c ****  * @param message 接收到的消息
 558:User/protocol.c ****  * @note 根据命令ID分发到对应的处理函数
 559:User/protocol.c ****  */
 560:User/protocol.c **** static void __protocol_on_message(dji_t self, dji_message_t message)
 561:User/protocol.c **** {
 562:User/protocol.c ****     CommandUpdate();
 563:User/protocol.c ****     switch (message->cmd)
 564:User/protocol.c ****     {
 565:User/protocol.c ****     case 0x01: // 获取版本信息
 566:User/protocol.c ****         __protocol_0x01_echo(self, message);
 567:User/protocol.c ****         break;
 568:User/protocol.c **** 
 569:User/protocol.c ****     case 0x03: // 设置SN码
 570:User/protocol.c ****         __protocol_0x03_echo(self, message);
 571:User/protocol.c ****         break;
 572:User/protocol.c **** 
 573:User/protocol.c ****     case 0x04: // 读取SN码
 574:User/protocol.c ****         __protocol_0x04_echo(self, message);
 575:User/protocol.c ****         break;
 576:User/protocol.c **** 
 577:User/protocol.c ****     case 0x05: // 获取激活状态
 578:User/protocol.c ****         __protocol_0x05_echo(self, message);
 579:User/protocol.c ****         break;
 580:User/protocol.c **** 
 581:User/protocol.c ****     case 0x06: // 设置激活状态
 582:User/protocol.c ****         __protocol_0x06_echo(self, message);
 583:User/protocol.c ****         break;
 584:User/protocol.c **** 
 585:User/protocol.c ****     case 0x07: // 反激活
 586:User/protocol.c ****         __protocol_0x07_echo(self, message);
 587:User/protocol.c ****         break;
 588:User/protocol.c **** 
 589:User/protocol.c ****     case 0x12: // 霍尔标定
 590:User/protocol.c ****         __protocol_0x12_echo(self, message);
 591:User/protocol.c ****         break;
 592:User/protocol.c **** 
 593:User/protocol.c ****     case 0x13: // 读写霍尔标定信息
 594:User/protocol.c ****         __protocol_0x13_echo(self, message);
 595:User/protocol.c ****         break;
 596:User/protocol.c **** 
 597:User/protocol.c ****     case 0x15: // 获取异常状态
 598:User/protocol.c ****         __protocol_0x15_echo(self, message);
ARM GAS  /tmp/cciZ31jV.s 			page 12


 599:User/protocol.c ****         break;
 600:User/protocol.c **** 
 601:User/protocol.c ****     case 0x16: // 清除异常状态
 602:User/protocol.c ****         __protocol_0x16_echo(self, message);
 603:User/protocol.c ****         break;
 604:User/protocol.c **** 
 605:User/protocol.c ****     case 0x17: // UID读取
 606:User/protocol.c ****         __protocol_0x17_echo(self, message);
 607:User/protocol.c ****         break;
 608:User/protocol.c **** 
 609:User/protocol.c ****     // case 0x18: // 编译时间读取
 610:User/protocol.c ****     //     __protocol_0x18_echo(self, message);
 611:User/protocol.c ****     //     break;
 612:User/protocol.c **** 
 613:User/protocol.c ****     case 0x20: // 电机控制指令
 614:User/protocol.c ****         __protocol_0x20_echo(self, message);
 615:User/protocol.c ****         break;
 616:User/protocol.c **** 
 617:User/protocol.c ****     case 0x21: // 设置重置 KpKi
 618:User/protocol.c ****         __protocol_0x21_echo(self, message);
 619:User/protocol.c ****         break;
 620:User/protocol.c **** 
 621:User/protocol.c ****     case 0x70: // 进入升级模式
 622:User/protocol.c ****         __protocol_0x70_echo(self, message);
 623:User/protocol.c ****         break;
 624:User/protocol.c **** 
 625:User/protocol.c ****     case 0x71: // 当前升级状态
 626:User/protocol.c ****         __protocol_0x71_echo(self, message);
 627:User/protocol.c ****         break;
 628:User/protocol.c **** 
 629:User/protocol.c ****     case 0x72: // 进入loader模式
 630:User/protocol.c ****         __protocol_0x72_echo(self, message);
 631:User/protocol.c ****         break;
 632:User/protocol.c **** 
 633:User/protocol.c ****     default:
 634:User/protocol.c ****         break;
 635:User/protocol.c ****     }
 636:User/protocol.c **** }
 637:User/protocol.c **** 
 638:User/protocol.c **** /**
 639:User/protocol.c ****  * @brief DJI周期性处理函数
 640:User/protocol.c ****  * @note 处理UART接收数据并调用DJI协议栈
 641:User/protocol.c ****  */
 642:User/protocol.c **** static void __protocol_on_step(void)
 643:User/protocol.c **** {
  29              		.loc 1 643 1 view -0
  30              		.cfi_startproc
  31              		@ args = 0, pretend = 0, frame = 64
  32              		@ frame_needed = 0, uses_anonymous_args = 0
 644:User/protocol.c ****     static uint32_t count = 0;
  33              		.loc 1 644 5 view .LVU1
 645:User/protocol.c ****     uint8_t data[64];
  34              		.loc 1 645 5 view .LVU2
 646:User/protocol.c ****     uint32_t length;
  35              		.loc 1 646 5 view .LVU3
 647:User/protocol.c **** 
 648:User/protocol.c ****     while (uart_available())
ARM GAS  /tmp/cciZ31jV.s 			page 13


  36              		.loc 1 648 5 view .LVU4
 643:User/protocol.c ****     static uint32_t count = 0;
  37              		.loc 1 643 1 is_stmt 0 view .LVU5
  38 0000 10B5     		push	{r4, lr}
  39              	.LCFI0:
  40              		.cfi_def_cfa_offset 8
  41              		.cfi_offset 4, -8
  42              		.cfi_offset 14, -4
  43 0002 1A4C     		ldr	r4, .L12
  44 0004 90B0     		sub	sp, sp, #64
  45              	.LCFI1:
  46              		.cfi_def_cfa_offset 72
  47              		.loc 1 648 11 view .LVU6
  48 0006 08E0     		b	.L2
  49              	.L3:
 649:User/protocol.c ****     {
 650:User/protocol.c ****         length = uart_recv(data, sizeof(data));
  50              		.loc 1 650 9 is_stmt 1 view .LVU7
  51              		.loc 1 650 18 is_stmt 0 view .LVU8
  52 0008 4021     		movs	r1, #64
  53 000a 6846     		mov	r0, sp
  54 000c FFF7FEFF 		bl	uart_recv
  55              	.LVL0:
 651:User/protocol.c ****         dji_on_recv(&g_dji_handle, data, length);
  56              		.loc 1 651 9 view .LVU9
  57 0010 6946     		mov	r1, sp
 650:User/protocol.c ****         dji_on_recv(&g_dji_handle, data, length);
  58              		.loc 1 650 18 view .LVU10
  59 0012 0200     		movs	r2, r0
  60              	.LVL1:
  61              		.loc 1 651 9 is_stmt 1 view .LVU11
  62 0014 2000     		movs	r0, r4
  63              	.LVL2:
  64              		.loc 1 651 9 is_stmt 0 view .LVU12
  65 0016 FFF7FEFF 		bl	dji_on_recv
  66              	.LVL3:
  67              	.L2:
 648:User/protocol.c ****     {
  68              		.loc 1 648 12 is_stmt 1 view .LVU13
  69 001a FFF7FEFF 		bl	uart_available
  70              	.LVL4:
 648:User/protocol.c ****     {
  71              		.loc 1 648 12 is_stmt 0 discriminator 1 view .LVU14
  72 001e 0028     		cmp	r0, #0
  73 0020 F2D1     		bne	.L3
 652:User/protocol.c ****     }
 653:User/protocol.c **** 
 654:User/protocol.c ****     if (reset_flag)
  74              		.loc 1 654 5 is_stmt 1 view .LVU15
  75              		.loc 1 654 9 is_stmt 0 view .LVU16
  76 0022 134B     		ldr	r3, .L12+4
  77              		.loc 1 654 8 view .LVU17
  78 0024 1B78     		ldrb	r3, [r3]
  79 0026 002B     		cmp	r3, #0
  80 0028 05D0     		beq	.L6
 655:User/protocol.c ****     {
 656:User/protocol.c ****         if (!uart_send_end())
ARM GAS  /tmp/cciZ31jV.s 			page 14


  81              		.loc 1 656 9 is_stmt 1 view .LVU18
  82              		.loc 1 656 14 is_stmt 0 view .LVU19
  83 002a FFF7FEFF 		bl	uart_send_end
  84              	.LVL5:
  85              		.loc 1 656 12 discriminator 1 view .LVU20
  86 002e 0028     		cmp	r0, #0
  87 0030 0CD1     		bne	.L5
 657:User/protocol.c ****         {
 658:User/protocol.c ****             count = 0;
  88              		.loc 1 658 13 is_stmt 1 view .LVU21
  89              		.loc 1 658 19 is_stmt 0 view .LVU22
  90 0032 104B     		ldr	r3, .L12+8
  91 0034 1860     		str	r0, [r3]
  92              	.L6:
 659:User/protocol.c ****         }
 660:User/protocol.c ****         else if (++count > 4)
 661:User/protocol.c ****         {
 662:User/protocol.c ****             NVIC_SystemReset();
 663:User/protocol.c ****         }
 664:User/protocol.c ****     }
 665:User/protocol.c ****     uart_printf("VALUE:%d\n",B11A1_DW.ITaskControl.AngleOffset);
  93              		.loc 1 665 5 is_stmt 1 view .LVU23
  94 0036 104B     		ldr	r3, .L12+12
  95 0038 1048     		ldr	r0, .L12+16
  96 003a 196C     		ldr	r1, [r3, #64]
  97 003c FFF7FEFF 		bl	uart_printf
  98              	.LVL6:
 666:User/protocol.c ****     dji_on_step(&g_dji_handle, 1);
  99              		.loc 1 666 5 view .LVU24
 100 0040 0121     		movs	r1, #1
 101 0042 2000     		movs	r0, r4
 102 0044 FFF7FEFF 		bl	dji_on_step
 103              	.LVL7:
 667:User/protocol.c **** }
 104              		.loc 1 667 1 is_stmt 0 view .LVU25
 105 0048 10B0     		add	sp, sp, #64
 106              		@ sp needed
 107 004a 10BD     		pop	{r4, pc}
 108              	.L5:
 660:User/protocol.c ****         {
 109              		.loc 1 660 14 is_stmt 1 view .LVU26
 660:User/protocol.c ****         {
 110              		.loc 1 660 18 is_stmt 0 view .LVU27
 111 004c 094A     		ldr	r2, .L12+8
 112 004e 1368     		ldr	r3, [r2]
 113 0050 0133     		adds	r3, r3, #1
 660:User/protocol.c ****         {
 114              		.loc 1 660 17 view .LVU28
 115 0052 1360     		str	r3, [r2]
 116 0054 042B     		cmp	r3, #4
 117 0056 EED9     		bls	.L6
 662:User/protocol.c ****         }
 118              		.loc 1 662 13 is_stmt 1 view .LVU29
 119              	.LBB16:
 120              	.LBI16:
 121              		.file 2 "Core/core_cm0.h"
   1:Core/core_cm0.h **** /**************************************************************************//**
ARM GAS  /tmp/cciZ31jV.s 			page 15


   2:Core/core_cm0.h ****  * @file     core_cm0.h
   3:Core/core_cm0.h ****  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
   4:Core/core_cm0.h ****  * @version  V5.0.8
   5:Core/core_cm0.h ****  * @date     21. August 2019
   6:Core/core_cm0.h ****  ******************************************************************************/
   7:Core/core_cm0.h **** /*
   8:Core/core_cm0.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Core/core_cm0.h ****  *
  10:Core/core_cm0.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/core_cm0.h ****  *
  12:Core/core_cm0.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/core_cm0.h ****  * not use this file except in compliance with the License.
  14:Core/core_cm0.h ****  * You may obtain a copy of the License at
  15:Core/core_cm0.h ****  *
  16:Core/core_cm0.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/core_cm0.h ****  *
  18:Core/core_cm0.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/core_cm0.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/core_cm0.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/core_cm0.h ****  * See the License for the specific language governing permissions and
  22:Core/core_cm0.h ****  * limitations under the License.
  23:Core/core_cm0.h ****  */
  24:Core/core_cm0.h **** 
  25:Core/core_cm0.h **** #if   defined ( __ICCARM__ )
  26:Core/core_cm0.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Core/core_cm0.h **** #elif defined (__clang__)
  28:Core/core_cm0.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Core/core_cm0.h **** #endif
  30:Core/core_cm0.h **** 
  31:Core/core_cm0.h **** #ifndef __CORE_CM0_H_GENERIC
  32:Core/core_cm0.h **** #define __CORE_CM0_H_GENERIC
  33:Core/core_cm0.h **** 
  34:Core/core_cm0.h **** #include <stdint.h>
  35:Core/core_cm0.h **** 
  36:Core/core_cm0.h **** #ifdef __cplusplus
  37:Core/core_cm0.h ****  extern "C" {
  38:Core/core_cm0.h **** #endif
  39:Core/core_cm0.h **** 
  40:Core/core_cm0.h **** /**
  41:Core/core_cm0.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Core/core_cm0.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Core/core_cm0.h **** 
  44:Core/core_cm0.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  45:Core/core_cm0.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Core/core_cm0.h **** 
  47:Core/core_cm0.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Core/core_cm0.h ****      Unions are used for effective representation of core registers.
  49:Core/core_cm0.h **** 
  50:Core/core_cm0.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Core/core_cm0.h ****      Function-like macros are used to allow more efficient code.
  52:Core/core_cm0.h ****  */
  53:Core/core_cm0.h **** 
  54:Core/core_cm0.h **** 
  55:Core/core_cm0.h **** /*******************************************************************************
  56:Core/core_cm0.h ****  *                 CMSIS definitions
  57:Core/core_cm0.h ****  ******************************************************************************/
  58:Core/core_cm0.h **** /**
ARM GAS  /tmp/cciZ31jV.s 			page 16


  59:Core/core_cm0.h ****   \ingroup Cortex_M0
  60:Core/core_cm0.h ****   @{
  61:Core/core_cm0.h ****  */
  62:Core/core_cm0.h **** 
  63:Core/core_cm0.h **** #include "cmsis_version.h"
  64:Core/core_cm0.h ****  
  65:Core/core_cm0.h **** /*  CMSIS CM0 definitions */
  66:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
  67:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
  68:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
  69:Core/core_cm0.h ****                                     __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
  70:Core/core_cm0.h **** 
  71:Core/core_cm0.h **** #define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
  72:Core/core_cm0.h **** 
  73:Core/core_cm0.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Core/core_cm0.h ****     This core does not support an FPU at all
  75:Core/core_cm0.h **** */
  76:Core/core_cm0.h **** #define __FPU_USED       0U
  77:Core/core_cm0.h **** 
  78:Core/core_cm0.h **** #if defined ( __CC_ARM )
  79:Core/core_cm0.h ****   #if defined __TARGET_FPU_VFP
  80:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  81:Core/core_cm0.h ****   #endif
  82:Core/core_cm0.h **** 
  83:Core/core_cm0.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  84:Core/core_cm0.h ****   #if defined __ARM_FP
  85:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86:Core/core_cm0.h ****   #endif
  87:Core/core_cm0.h **** 
  88:Core/core_cm0.h **** #elif defined ( __GNUC__ )
  89:Core/core_cm0.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  90:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  91:Core/core_cm0.h ****   #endif
  92:Core/core_cm0.h **** 
  93:Core/core_cm0.h **** #elif defined ( __ICCARM__ )
  94:Core/core_cm0.h ****   #if defined __ARMVFP__
  95:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  96:Core/core_cm0.h ****   #endif
  97:Core/core_cm0.h **** 
  98:Core/core_cm0.h **** #elif defined ( __TI_ARM__ )
  99:Core/core_cm0.h ****   #if defined __TI_VFP_SUPPORT__
 100:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 101:Core/core_cm0.h ****   #endif
 102:Core/core_cm0.h **** 
 103:Core/core_cm0.h **** #elif defined ( __TASKING__ )
 104:Core/core_cm0.h ****   #if defined __FPU_VFP__
 105:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 106:Core/core_cm0.h ****   #endif
 107:Core/core_cm0.h **** 
 108:Core/core_cm0.h **** #elif defined ( __CSMC__ )
 109:Core/core_cm0.h ****   #if ( __CSMC__ & 0x400U)
 110:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 111:Core/core_cm0.h ****   #endif
 112:Core/core_cm0.h **** 
 113:Core/core_cm0.h **** #endif
 114:Core/core_cm0.h **** 
 115:Core/core_cm0.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
ARM GAS  /tmp/cciZ31jV.s 			page 17


 116:Core/core_cm0.h **** 
 117:Core/core_cm0.h **** 
 118:Core/core_cm0.h **** #ifdef __cplusplus
 119:Core/core_cm0.h **** }
 120:Core/core_cm0.h **** #endif
 121:Core/core_cm0.h **** 
 122:Core/core_cm0.h **** #endif /* __CORE_CM0_H_GENERIC */
 123:Core/core_cm0.h **** 
 124:Core/core_cm0.h **** #ifndef __CMSIS_GENERIC
 125:Core/core_cm0.h **** 
 126:Core/core_cm0.h **** #ifndef __CORE_CM0_H_DEPENDANT
 127:Core/core_cm0.h **** #define __CORE_CM0_H_DEPENDANT
 128:Core/core_cm0.h **** 
 129:Core/core_cm0.h **** #ifdef __cplusplus
 130:Core/core_cm0.h ****  extern "C" {
 131:Core/core_cm0.h **** #endif
 132:Core/core_cm0.h **** 
 133:Core/core_cm0.h **** /* check device defines and use defaults */
 134:Core/core_cm0.h **** #if defined __CHECK_DEVICE_DEFINES
 135:Core/core_cm0.h ****   #ifndef __CM0_REV
 136:Core/core_cm0.h ****     #define __CM0_REV               0x0000U
 137:Core/core_cm0.h ****     #warning "__CM0_REV not defined in device header file; using default!"
 138:Core/core_cm0.h ****   #endif
 139:Core/core_cm0.h **** 
 140:Core/core_cm0.h ****   #ifndef __NVIC_PRIO_BITS
 141:Core/core_cm0.h ****     #define __NVIC_PRIO_BITS          2U
 142:Core/core_cm0.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 143:Core/core_cm0.h ****   #endif
 144:Core/core_cm0.h **** 
 145:Core/core_cm0.h ****   #ifndef __Vendor_SysTickConfig
 146:Core/core_cm0.h ****     #define __Vendor_SysTickConfig    0U
 147:Core/core_cm0.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 148:Core/core_cm0.h ****   #endif
 149:Core/core_cm0.h **** #endif
 150:Core/core_cm0.h **** 
 151:Core/core_cm0.h **** /* IO definitions (access restrictions to peripheral registers) */
 152:Core/core_cm0.h **** /**
 153:Core/core_cm0.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 154:Core/core_cm0.h **** 
 155:Core/core_cm0.h ****     <strong>IO Type Qualifiers</strong> are used
 156:Core/core_cm0.h ****     \li to specify the access to peripheral variables.
 157:Core/core_cm0.h ****     \li for automatic generation of peripheral register debug information.
 158:Core/core_cm0.h **** */
 159:Core/core_cm0.h **** #ifdef __cplusplus
 160:Core/core_cm0.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 161:Core/core_cm0.h **** #else
 162:Core/core_cm0.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 163:Core/core_cm0.h **** #endif
 164:Core/core_cm0.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 165:Core/core_cm0.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 166:Core/core_cm0.h **** 
 167:Core/core_cm0.h **** /* following defines should be used for structure members */
 168:Core/core_cm0.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 169:Core/core_cm0.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 170:Core/core_cm0.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 171:Core/core_cm0.h **** 
 172:Core/core_cm0.h **** /*@} end of group Cortex_M0 */
ARM GAS  /tmp/cciZ31jV.s 			page 18


 173:Core/core_cm0.h **** 
 174:Core/core_cm0.h **** 
 175:Core/core_cm0.h **** 
 176:Core/core_cm0.h **** /*******************************************************************************
 177:Core/core_cm0.h ****  *                 Register Abstraction
 178:Core/core_cm0.h ****   Core Register contain:
 179:Core/core_cm0.h ****   - Core Register
 180:Core/core_cm0.h ****   - Core NVIC Register
 181:Core/core_cm0.h ****   - Core SCB Register
 182:Core/core_cm0.h ****   - Core SysTick Register
 183:Core/core_cm0.h ****  ******************************************************************************/
 184:Core/core_cm0.h **** /**
 185:Core/core_cm0.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 186:Core/core_cm0.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 187:Core/core_cm0.h **** */
 188:Core/core_cm0.h **** 
 189:Core/core_cm0.h **** /**
 190:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 191:Core/core_cm0.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 192:Core/core_cm0.h ****   \brief      Core Register type definitions.
 193:Core/core_cm0.h ****   @{
 194:Core/core_cm0.h ****  */
 195:Core/core_cm0.h **** 
 196:Core/core_cm0.h **** /**
 197:Core/core_cm0.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 198:Core/core_cm0.h ****  */
 199:Core/core_cm0.h **** typedef union
 200:Core/core_cm0.h **** {
 201:Core/core_cm0.h ****   struct
 202:Core/core_cm0.h ****   {
 203:Core/core_cm0.h ****     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
 204:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 205:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 206:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 207:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 208:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 209:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 210:Core/core_cm0.h **** } APSR_Type;
 211:Core/core_cm0.h **** 
 212:Core/core_cm0.h **** /* APSR Register Definitions */
 213:Core/core_cm0.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 214:Core/core_cm0.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 215:Core/core_cm0.h **** 
 216:Core/core_cm0.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 217:Core/core_cm0.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 218:Core/core_cm0.h **** 
 219:Core/core_cm0.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 220:Core/core_cm0.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 221:Core/core_cm0.h **** 
 222:Core/core_cm0.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 223:Core/core_cm0.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 224:Core/core_cm0.h **** 
 225:Core/core_cm0.h **** 
 226:Core/core_cm0.h **** /**
 227:Core/core_cm0.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 228:Core/core_cm0.h ****  */
 229:Core/core_cm0.h **** typedef union
ARM GAS  /tmp/cciZ31jV.s 			page 19


 230:Core/core_cm0.h **** {
 231:Core/core_cm0.h ****   struct
 232:Core/core_cm0.h ****   {
 233:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 234:Core/core_cm0.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 235:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 236:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 237:Core/core_cm0.h **** } IPSR_Type;
 238:Core/core_cm0.h **** 
 239:Core/core_cm0.h **** /* IPSR Register Definitions */
 240:Core/core_cm0.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 241:Core/core_cm0.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 242:Core/core_cm0.h **** 
 243:Core/core_cm0.h **** 
 244:Core/core_cm0.h **** /**
 245:Core/core_cm0.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 246:Core/core_cm0.h ****  */
 247:Core/core_cm0.h **** typedef union
 248:Core/core_cm0.h **** {
 249:Core/core_cm0.h ****   struct
 250:Core/core_cm0.h ****   {
 251:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 252:Core/core_cm0.h ****     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
 253:Core/core_cm0.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 254:Core/core_cm0.h ****     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
 255:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 256:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 257:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 258:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 259:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 260:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 261:Core/core_cm0.h **** } xPSR_Type;
 262:Core/core_cm0.h **** 
 263:Core/core_cm0.h **** /* xPSR Register Definitions */
 264:Core/core_cm0.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 265:Core/core_cm0.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 266:Core/core_cm0.h **** 
 267:Core/core_cm0.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 268:Core/core_cm0.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 269:Core/core_cm0.h **** 
 270:Core/core_cm0.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 271:Core/core_cm0.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 272:Core/core_cm0.h **** 
 273:Core/core_cm0.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 274:Core/core_cm0.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 275:Core/core_cm0.h **** 
 276:Core/core_cm0.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 277:Core/core_cm0.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 278:Core/core_cm0.h **** 
 279:Core/core_cm0.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 280:Core/core_cm0.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 281:Core/core_cm0.h **** 
 282:Core/core_cm0.h **** 
 283:Core/core_cm0.h **** /**
 284:Core/core_cm0.h ****   \brief  Union type to access the Control Registers (CONTROL).
 285:Core/core_cm0.h ****  */
 286:Core/core_cm0.h **** typedef union
ARM GAS  /tmp/cciZ31jV.s 			page 20


 287:Core/core_cm0.h **** {
 288:Core/core_cm0.h ****   struct
 289:Core/core_cm0.h ****   {
 290:Core/core_cm0.h ****     uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
 291:Core/core_cm0.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 292:Core/core_cm0.h ****     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 293:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 294:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 295:Core/core_cm0.h **** } CONTROL_Type;
 296:Core/core_cm0.h **** 
 297:Core/core_cm0.h **** /* CONTROL Register Definitions */
 298:Core/core_cm0.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 299:Core/core_cm0.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 300:Core/core_cm0.h **** 
 301:Core/core_cm0.h **** /*@} end of group CMSIS_CORE */
 302:Core/core_cm0.h **** 
 303:Core/core_cm0.h **** 
 304:Core/core_cm0.h **** /**
 305:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 306:Core/core_cm0.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 307:Core/core_cm0.h ****   \brief      Type definitions for the NVIC Registers
 308:Core/core_cm0.h ****   @{
 309:Core/core_cm0.h ****  */
 310:Core/core_cm0.h **** 
 311:Core/core_cm0.h **** /**
 312:Core/core_cm0.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 313:Core/core_cm0.h ****  */
 314:Core/core_cm0.h **** typedef struct
 315:Core/core_cm0.h **** {
 316:Core/core_cm0.h ****   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 317:Core/core_cm0.h ****         uint32_t RESERVED0[31U];
 318:Core/core_cm0.h ****   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 319:Core/core_cm0.h ****         uint32_t RESERVED1[31U];
 320:Core/core_cm0.h ****   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 321:Core/core_cm0.h ****         uint32_t RESERVED2[31U];
 322:Core/core_cm0.h ****   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 323:Core/core_cm0.h ****         uint32_t RESERVED3[31U];
 324:Core/core_cm0.h ****         uint32_t RESERVED4[64U];
 325:Core/core_cm0.h ****   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 326:Core/core_cm0.h **** }  NVIC_Type;
 327:Core/core_cm0.h **** 
 328:Core/core_cm0.h **** /*@} end of group CMSIS_NVIC */
 329:Core/core_cm0.h **** 
 330:Core/core_cm0.h **** 
 331:Core/core_cm0.h **** /**
 332:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 333:Core/core_cm0.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 334:Core/core_cm0.h ****   \brief    Type definitions for the System Control Block Registers
 335:Core/core_cm0.h ****   @{
 336:Core/core_cm0.h ****  */
 337:Core/core_cm0.h **** 
 338:Core/core_cm0.h **** /**
 339:Core/core_cm0.h ****   \brief  Structure type to access the System Control Block (SCB).
 340:Core/core_cm0.h ****  */
 341:Core/core_cm0.h **** typedef struct
 342:Core/core_cm0.h **** {
 343:Core/core_cm0.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
ARM GAS  /tmp/cciZ31jV.s 			page 21


 344:Core/core_cm0.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 345:Core/core_cm0.h ****         uint32_t RESERVED0;
 346:Core/core_cm0.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 347:Core/core_cm0.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 348:Core/core_cm0.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 349:Core/core_cm0.h ****         uint32_t RESERVED1;
 350:Core/core_cm0.h ****   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registe
 351:Core/core_cm0.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 352:Core/core_cm0.h **** } SCB_Type;
 353:Core/core_cm0.h **** 
 354:Core/core_cm0.h **** /* SCB CPUID Register Definitions */
 355:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 356:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 357:Core/core_cm0.h **** 
 358:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 359:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 360:Core/core_cm0.h **** 
 361:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 362:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 363:Core/core_cm0.h **** 
 364:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 365:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 366:Core/core_cm0.h **** 
 367:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 368:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 369:Core/core_cm0.h **** 
 370:Core/core_cm0.h **** /* SCB Interrupt Control State Register Definitions */
 371:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 372:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 373:Core/core_cm0.h **** 
 374:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 375:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 376:Core/core_cm0.h **** 
 377:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 378:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 379:Core/core_cm0.h **** 
 380:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 381:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 382:Core/core_cm0.h **** 
 383:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 384:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 385:Core/core_cm0.h **** 
 386:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 387:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 388:Core/core_cm0.h **** 
 389:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 390:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 391:Core/core_cm0.h **** 
 392:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 393:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 394:Core/core_cm0.h **** 
 395:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 396:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 397:Core/core_cm0.h **** 
 398:Core/core_cm0.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 399:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 400:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
ARM GAS  /tmp/cciZ31jV.s 			page 22


 401:Core/core_cm0.h **** 
 402:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 403:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 404:Core/core_cm0.h **** 
 405:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 406:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 407:Core/core_cm0.h **** 
 408:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 409:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 410:Core/core_cm0.h **** 
 411:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 412:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 413:Core/core_cm0.h **** 
 414:Core/core_cm0.h **** /* SCB System Control Register Definitions */
 415:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 416:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 417:Core/core_cm0.h **** 
 418:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 419:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 420:Core/core_cm0.h **** 
 421:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 422:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 423:Core/core_cm0.h **** 
 424:Core/core_cm0.h **** /* SCB Configuration Control Register Definitions */
 425:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 426:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 427:Core/core_cm0.h **** 
 428:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 429:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 430:Core/core_cm0.h **** 
 431:Core/core_cm0.h **** /* SCB System Handler Control and State Register Definitions */
 432:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 433:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
 434:Core/core_cm0.h **** 
 435:Core/core_cm0.h **** /*@} end of group CMSIS_SCB */
 436:Core/core_cm0.h **** 
 437:Core/core_cm0.h **** 
 438:Core/core_cm0.h **** /**
 439:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 440:Core/core_cm0.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 441:Core/core_cm0.h ****   \brief    Type definitions for the System Timer Registers.
 442:Core/core_cm0.h ****   @{
 443:Core/core_cm0.h ****  */
 444:Core/core_cm0.h **** 
 445:Core/core_cm0.h **** /**
 446:Core/core_cm0.h ****   \brief  Structure type to access the System Timer (SysTick).
 447:Core/core_cm0.h ****  */
 448:Core/core_cm0.h **** typedef struct
 449:Core/core_cm0.h **** {
 450:Core/core_cm0.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 451:Core/core_cm0.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 452:Core/core_cm0.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 453:Core/core_cm0.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 454:Core/core_cm0.h **** } SysTick_Type;
 455:Core/core_cm0.h **** 
 456:Core/core_cm0.h **** /* SysTick Control / Status Register Definitions */
 457:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
ARM GAS  /tmp/cciZ31jV.s 			page 23


 458:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 459:Core/core_cm0.h **** 
 460:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 461:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 462:Core/core_cm0.h **** 
 463:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 464:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 465:Core/core_cm0.h **** 
 466:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 467:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 468:Core/core_cm0.h **** 
 469:Core/core_cm0.h **** /* SysTick Reload Register Definitions */
 470:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 471:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 472:Core/core_cm0.h **** 
 473:Core/core_cm0.h **** /* SysTick Current Register Definitions */
 474:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 475:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 476:Core/core_cm0.h **** 
 477:Core/core_cm0.h **** /* SysTick Calibration Register Definitions */
 478:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 479:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 480:Core/core_cm0.h **** 
 481:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 482:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 483:Core/core_cm0.h **** 
 484:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 485:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 486:Core/core_cm0.h **** 
 487:Core/core_cm0.h **** /*@} end of group CMSIS_SysTick */
 488:Core/core_cm0.h **** 
 489:Core/core_cm0.h **** 
 490:Core/core_cm0.h **** /**
 491:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 492:Core/core_cm0.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
 493:Core/core_cm0.h ****   \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ove
 494:Core/core_cm0.h ****             Therefore they are not covered by the Cortex-M0 header file.
 495:Core/core_cm0.h ****   @{
 496:Core/core_cm0.h ****  */
 497:Core/core_cm0.h **** /*@} end of group CMSIS_CoreDebug */
 498:Core/core_cm0.h **** 
 499:Core/core_cm0.h **** 
 500:Core/core_cm0.h **** /**
 501:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 502:Core/core_cm0.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
 503:Core/core_cm0.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 504:Core/core_cm0.h ****   @{
 505:Core/core_cm0.h ****  */
 506:Core/core_cm0.h **** 
 507:Core/core_cm0.h **** /**
 508:Core/core_cm0.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
 509:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 510:Core/core_cm0.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
 511:Core/core_cm0.h ****   \return           Masked and shifted value.
 512:Core/core_cm0.h **** */
 513:Core/core_cm0.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 514:Core/core_cm0.h **** 
ARM GAS  /tmp/cciZ31jV.s 			page 24


 515:Core/core_cm0.h **** /**
 516:Core/core_cm0.h ****   \brief     Mask and shift a register value to extract a bit filed value.
 517:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 518:Core/core_cm0.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
 519:Core/core_cm0.h ****   \return           Masked and shifted bit field value.
 520:Core/core_cm0.h **** */
 521:Core/core_cm0.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 522:Core/core_cm0.h **** 
 523:Core/core_cm0.h **** /*@} end of group CMSIS_core_bitfield */
 524:Core/core_cm0.h **** 
 525:Core/core_cm0.h **** 
 526:Core/core_cm0.h **** /**
 527:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 528:Core/core_cm0.h ****   \defgroup   CMSIS_core_base     Core Definitions
 529:Core/core_cm0.h ****   \brief      Definitions for base addresses, unions, and structures.
 530:Core/core_cm0.h ****   @{
 531:Core/core_cm0.h ****  */
 532:Core/core_cm0.h **** 
 533:Core/core_cm0.h **** /* Memory mapping of Core Hardware */
 534:Core/core_cm0.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
 535:Core/core_cm0.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 536:Core/core_cm0.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 537:Core/core_cm0.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
 538:Core/core_cm0.h **** 
 539:Core/core_cm0.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
 540:Core/core_cm0.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
 541:Core/core_cm0.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
 542:Core/core_cm0.h **** 
 543:Core/core_cm0.h **** 
 544:Core/core_cm0.h **** /*@} */
 545:Core/core_cm0.h **** 
 546:Core/core_cm0.h **** 
 547:Core/core_cm0.h **** 
 548:Core/core_cm0.h **** /*******************************************************************************
 549:Core/core_cm0.h ****  *                Hardware Abstraction Layer
 550:Core/core_cm0.h ****   Core Function Interface contains:
 551:Core/core_cm0.h ****   - Core NVIC Functions
 552:Core/core_cm0.h ****   - Core SysTick Functions
 553:Core/core_cm0.h ****   - Core Register Access Functions
 554:Core/core_cm0.h ****  ******************************************************************************/
 555:Core/core_cm0.h **** /**
 556:Core/core_cm0.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 557:Core/core_cm0.h **** */
 558:Core/core_cm0.h **** 
 559:Core/core_cm0.h **** 
 560:Core/core_cm0.h **** 
 561:Core/core_cm0.h **** /* ##########################   NVIC functions  #################################### */
 562:Core/core_cm0.h **** /**
 563:Core/core_cm0.h ****   \ingroup  CMSIS_Core_FunctionInterface
 564:Core/core_cm0.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
 565:Core/core_cm0.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
 566:Core/core_cm0.h ****   @{
 567:Core/core_cm0.h ****  */
 568:Core/core_cm0.h **** 
 569:Core/core_cm0.h **** #ifdef CMSIS_NVIC_VIRTUAL
 570:Core/core_cm0.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
 571:Core/core_cm0.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
ARM GAS  /tmp/cciZ31jV.s 			page 25


 572:Core/core_cm0.h ****   #endif
 573:Core/core_cm0.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 574:Core/core_cm0.h **** #else
 575:Core/core_cm0.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
 576:Core/core_cm0.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
 577:Core/core_cm0.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
 578:Core/core_cm0.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
 579:Core/core_cm0.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
 580:Core/core_cm0.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
 581:Core/core_cm0.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
 582:Core/core_cm0.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 583:Core/core_cm0.h **** /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
 584:Core/core_cm0.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
 585:Core/core_cm0.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
 586:Core/core_cm0.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
 587:Core/core_cm0.h **** #endif /* CMSIS_NVIC_VIRTUAL */
 588:Core/core_cm0.h **** 
 589:Core/core_cm0.h **** #ifdef CMSIS_VECTAB_VIRTUAL
 590:Core/core_cm0.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 591:Core/core_cm0.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
 592:Core/core_cm0.h ****   #endif
 593:Core/core_cm0.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 594:Core/core_cm0.h **** #else
 595:Core/core_cm0.h ****   #define NVIC_SetVector              __NVIC_SetVector
 596:Core/core_cm0.h ****   #define NVIC_GetVector              __NVIC_GetVector
 597:Core/core_cm0.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 598:Core/core_cm0.h **** 
 599:Core/core_cm0.h **** #define NVIC_USER_IRQ_OFFSET          16
 600:Core/core_cm0.h **** 
 601:Core/core_cm0.h **** 
 602:Core/core_cm0.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
 603:Core/core_cm0.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
 604:Core/core_cm0.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
 605:Core/core_cm0.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
 606:Core/core_cm0.h **** 
 607:Core/core_cm0.h **** 
 608:Core/core_cm0.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 609:Core/core_cm0.h **** /* The following MACROS handle generation of the register offset and byte masks */
 610:Core/core_cm0.h **** #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 611:Core/core_cm0.h **** #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 612:Core/core_cm0.h **** #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 613:Core/core_cm0.h **** 
 614:Core/core_cm0.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X)
 615:Core/core_cm0.h **** #define __NVIC_GetPriorityGrouping()  (0U)
 616:Core/core_cm0.h **** 
 617:Core/core_cm0.h **** /**
 618:Core/core_cm0.h ****   \brief   Enable Interrupt
 619:Core/core_cm0.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
 620:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 621:Core/core_cm0.h ****   \note    IRQn must not be negative.
 622:Core/core_cm0.h ****  */
 623:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 624:Core/core_cm0.h **** {
 625:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 626:Core/core_cm0.h ****   {
 627:Core/core_cm0.h ****     __COMPILER_BARRIER();
 628:Core/core_cm0.h ****     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
ARM GAS  /tmp/cciZ31jV.s 			page 26


 629:Core/core_cm0.h ****     __COMPILER_BARRIER();
 630:Core/core_cm0.h ****   }
 631:Core/core_cm0.h **** }
 632:Core/core_cm0.h **** 
 633:Core/core_cm0.h **** 
 634:Core/core_cm0.h **** /**
 635:Core/core_cm0.h ****   \brief   Get Interrupt Enable status
 636:Core/core_cm0.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
 637:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 638:Core/core_cm0.h ****   \return             0  Interrupt is not enabled.
 639:Core/core_cm0.h ****   \return             1  Interrupt is enabled.
 640:Core/core_cm0.h ****   \note    IRQn must not be negative.
 641:Core/core_cm0.h ****  */
 642:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 643:Core/core_cm0.h **** {
 644:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 645:Core/core_cm0.h ****   {
 646:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 647:Core/core_cm0.h ****   }
 648:Core/core_cm0.h ****   else
 649:Core/core_cm0.h ****   {
 650:Core/core_cm0.h ****     return(0U);
 651:Core/core_cm0.h ****   }
 652:Core/core_cm0.h **** }
 653:Core/core_cm0.h **** 
 654:Core/core_cm0.h **** 
 655:Core/core_cm0.h **** /**
 656:Core/core_cm0.h ****   \brief   Disable Interrupt
 657:Core/core_cm0.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
 658:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 659:Core/core_cm0.h ****   \note    IRQn must not be negative.
 660:Core/core_cm0.h ****  */
 661:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
 662:Core/core_cm0.h **** {
 663:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 664:Core/core_cm0.h ****   {
 665:Core/core_cm0.h ****     NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 666:Core/core_cm0.h ****     __DSB();
 667:Core/core_cm0.h ****     __ISB();
 668:Core/core_cm0.h ****   }
 669:Core/core_cm0.h **** }
 670:Core/core_cm0.h **** 
 671:Core/core_cm0.h **** 
 672:Core/core_cm0.h **** /**
 673:Core/core_cm0.h ****   \brief   Get Pending Interrupt
 674:Core/core_cm0.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
 675:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 676:Core/core_cm0.h ****   \return             0  Interrupt status is not pending.
 677:Core/core_cm0.h ****   \return             1  Interrupt status is pending.
 678:Core/core_cm0.h ****   \note    IRQn must not be negative.
 679:Core/core_cm0.h ****  */
 680:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 681:Core/core_cm0.h **** {
 682:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 683:Core/core_cm0.h ****   {
 684:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 685:Core/core_cm0.h ****   }
ARM GAS  /tmp/cciZ31jV.s 			page 27


 686:Core/core_cm0.h ****   else
 687:Core/core_cm0.h ****   {
 688:Core/core_cm0.h ****     return(0U);
 689:Core/core_cm0.h ****   }
 690:Core/core_cm0.h **** }
 691:Core/core_cm0.h **** 
 692:Core/core_cm0.h **** 
 693:Core/core_cm0.h **** /**
 694:Core/core_cm0.h ****   \brief   Set Pending Interrupt
 695:Core/core_cm0.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
 696:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 697:Core/core_cm0.h ****   \note    IRQn must not be negative.
 698:Core/core_cm0.h ****  */
 699:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 700:Core/core_cm0.h **** {
 701:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 702:Core/core_cm0.h ****   {
 703:Core/core_cm0.h ****     NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 704:Core/core_cm0.h ****   }
 705:Core/core_cm0.h **** }
 706:Core/core_cm0.h **** 
 707:Core/core_cm0.h **** 
 708:Core/core_cm0.h **** /**
 709:Core/core_cm0.h ****   \brief   Clear Pending Interrupt
 710:Core/core_cm0.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
 711:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 712:Core/core_cm0.h ****   \note    IRQn must not be negative.
 713:Core/core_cm0.h ****  */
 714:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 715:Core/core_cm0.h **** {
 716:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 717:Core/core_cm0.h ****   {
 718:Core/core_cm0.h ****     NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 719:Core/core_cm0.h ****   }
 720:Core/core_cm0.h **** }
 721:Core/core_cm0.h **** 
 722:Core/core_cm0.h **** 
 723:Core/core_cm0.h **** /**
 724:Core/core_cm0.h ****   \brief   Set Interrupt Priority
 725:Core/core_cm0.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
 726:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 727:Core/core_cm0.h ****            or negative to specify a processor exception.
 728:Core/core_cm0.h ****   \param [in]      IRQn  Interrupt number.
 729:Core/core_cm0.h ****   \param [in]  priority  Priority to set.
 730:Core/core_cm0.h ****   \note    The priority cannot be set for every processor exception.
 731:Core/core_cm0.h ****  */
 732:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 733:Core/core_cm0.h **** {
 734:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 735:Core/core_cm0.h ****   {
 736:Core/core_cm0.h ****     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))
 737:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 738:Core/core_cm0.h ****   }
 739:Core/core_cm0.h ****   else
 740:Core/core_cm0.h ****   {
 741:Core/core_cm0.h ****     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
 742:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
ARM GAS  /tmp/cciZ31jV.s 			page 28


 743:Core/core_cm0.h ****   }
 744:Core/core_cm0.h **** }
 745:Core/core_cm0.h **** 
 746:Core/core_cm0.h **** 
 747:Core/core_cm0.h **** /**
 748:Core/core_cm0.h ****   \brief   Get Interrupt Priority
 749:Core/core_cm0.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
 750:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 751:Core/core_cm0.h ****            or negative to specify a processor exception.
 752:Core/core_cm0.h ****   \param [in]   IRQn  Interrupt number.
 753:Core/core_cm0.h ****   \return             Interrupt Priority.
 754:Core/core_cm0.h ****                       Value is aligned automatically to the implemented priority bits of the microc
 755:Core/core_cm0.h ****  */
 756:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 757:Core/core_cm0.h **** {
 758:Core/core_cm0.h **** 
 759:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 760:Core/core_cm0.h ****   {
 761:Core/core_cm0.h ****     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 762:Core/core_cm0.h ****   }
 763:Core/core_cm0.h ****   else
 764:Core/core_cm0.h ****   {
 765:Core/core_cm0.h ****     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 766:Core/core_cm0.h ****   }
 767:Core/core_cm0.h **** }
 768:Core/core_cm0.h **** 
 769:Core/core_cm0.h **** 
 770:Core/core_cm0.h **** /**
 771:Core/core_cm0.h ****   \brief   Encode Priority
 772:Core/core_cm0.h ****   \details Encodes the priority for an interrupt with the given priority group,
 773:Core/core_cm0.h ****            preemptive priority value, and subpriority value.
 774:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 775:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
 776:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 777:Core/core_cm0.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
 778:Core/core_cm0.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
 779:Core/core_cm0.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
 780:Core/core_cm0.h ****  */
 781:Core/core_cm0.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
 782:Core/core_cm0.h **** {
 783:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 784:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 785:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 786:Core/core_cm0.h **** 
 787:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 788:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 789:Core/core_cm0.h **** 
 790:Core/core_cm0.h ****   return (
 791:Core/core_cm0.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 792:Core/core_cm0.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 793:Core/core_cm0.h ****          );
 794:Core/core_cm0.h **** }
 795:Core/core_cm0.h **** 
 796:Core/core_cm0.h **** 
 797:Core/core_cm0.h **** /**
 798:Core/core_cm0.h ****   \brief   Decode Priority
 799:Core/core_cm0.h ****   \details Decodes an interrupt priority value with a given priority group to
ARM GAS  /tmp/cciZ31jV.s 			page 29


 800:Core/core_cm0.h ****            preemptive priority value and subpriority value.
 801:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 802:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
 803:Core/core_cm0.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
 804:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 805:Core/core_cm0.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
 806:Core/core_cm0.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
 807:Core/core_cm0.h ****  */
 808:Core/core_cm0.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
 809:Core/core_cm0.h **** {
 810:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 811:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 812:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 813:Core/core_cm0.h **** 
 814:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 815:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 816:Core/core_cm0.h **** 
 817:Core/core_cm0.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
 818:Core/core_cm0.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 819:Core/core_cm0.h **** }
 820:Core/core_cm0.h **** 
 821:Core/core_cm0.h **** 
 822:Core/core_cm0.h **** 
 823:Core/core_cm0.h **** /**
 824:Core/core_cm0.h ****   \brief   Set Interrupt Vector
 825:Core/core_cm0.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
 826:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 827:Core/core_cm0.h ****            or negative to specify a processor exception.
 828:Core/core_cm0.h ****            Address 0 must be mapped to SRAM.
 829:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number
 830:Core/core_cm0.h ****   \param [in]   vector    Address of interrupt handler function
 831:Core/core_cm0.h ****  */
 832:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
 833:Core/core_cm0.h **** {
 834:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 835:Core/core_cm0.h ****   *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to ac
 836:Core/core_cm0.h ****   /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
 837:Core/core_cm0.h **** }
 838:Core/core_cm0.h **** 
 839:Core/core_cm0.h **** 
 840:Core/core_cm0.h **** /**
 841:Core/core_cm0.h ****   \brief   Get Interrupt Vector
 842:Core/core_cm0.h ****   \details Reads an interrupt vector from interrupt vector table.
 843:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 844:Core/core_cm0.h ****            or negative to specify a processor exception.
 845:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number.
 846:Core/core_cm0.h ****   \return                 Address of interrupt handler function
 847:Core/core_cm0.h ****  */
 848:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 849:Core/core_cm0.h **** {
 850:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 851:Core/core_cm0.h ****   return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to ac
 852:Core/core_cm0.h **** }
 853:Core/core_cm0.h **** 
 854:Core/core_cm0.h **** 
 855:Core/core_cm0.h **** /**
 856:Core/core_cm0.h ****   \brief   System Reset
ARM GAS  /tmp/cciZ31jV.s 			page 30


 857:Core/core_cm0.h ****   \details Initiates a system reset request to reset the MCU.
 858:Core/core_cm0.h ****  */
 859:Core/core_cm0.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 122              		.loc 2 859 34 view .LVU30
 123              	.LBB17:
 860:Core/core_cm0.h **** {
 861:Core/core_cm0.h ****   __DSB();                                                          /* Ensure all outstanding memor
 124              		.loc 2 861 3 view .LVU31
 125              	.LBB18:
 126              	.LBI18:
 127              		.file 3 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
ARM GAS  /tmp/cciZ31jV.s 			page 31


  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
ARM GAS  /tmp/cciZ31jV.s 			page 32


 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
ARM GAS  /tmp/cciZ31jV.s 			page 33


 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
ARM GAS  /tmp/cciZ31jV.s 			page 34


 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 128              		.loc 3 269 27 view .LVU32
 129              	.LBB19:
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 130              		.loc 3 271 3 view .LVU33
ARM GAS  /tmp/cciZ31jV.s 			page 35


 131              		.syntax divided
 132              	@ 271 "Core/cmsis_gcc.h" 1
 133 0058 BFF34F8F 		dsb 0xF
 134              	@ 0 "" 2
 135              		.thumb
 136              		.syntax unified
 137              	.LBE19:
 138              	.LBE18:
 862:Core/core_cm0.h ****                                                                        buffered write are completed
 863:Core/core_cm0.h ****   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 139              		.loc 2 863 3 view .LVU34
 140              		.loc 2 863 15 is_stmt 0 view .LVU35
 141 005c 084B     		ldr	r3, .L12+20
 142 005e 094A     		ldr	r2, .L12+24
 143 0060 DA60     		str	r2, [r3, #12]
 864:Core/core_cm0.h ****                  SCB_AIRCR_SYSRESETREQ_Msk);
 865:Core/core_cm0.h ****   __DSB();                                                          /* Ensure completion of memory 
 144              		.loc 2 865 3 is_stmt 1 view .LVU36
 145              	.LBB20:
 146              	.LBI20:
 269:Core/cmsis_gcc.h **** {
 147              		.loc 3 269 27 view .LVU37
 148              	.LBB21:
 149              		.loc 3 271 3 view .LVU38
 150              		.syntax divided
 151              	@ 271 "Core/cmsis_gcc.h" 1
 152 0062 BFF34F8F 		dsb 0xF
 153              	@ 0 "" 2
 154              		.thumb
 155              		.syntax unified
 156              	.L7:
 157              	.LBE21:
 158              	.LBE20:
 866:Core/core_cm0.h **** 
 867:Core/core_cm0.h ****   for(;;)                                                           /* wait until reset */
 159              		.loc 2 867 3 view .LVU39
 868:Core/core_cm0.h ****   {
 869:Core/core_cm0.h ****     __NOP();
 160              		.loc 2 869 5 discriminator 1 view .LVU40
 161              		.syntax divided
 162              	@ 869 "Core/core_cm0.h" 1
 163 0066 C046     		nop
 164              	@ 0 "" 2
 867:Core/core_cm0.h ****   {
 165              		.loc 2 867 3 view .LVU41
 166              		.thumb
 167              		.syntax unified
 168 0068 FDE7     		b	.L7
 169              	.L13:
 170 006a C046     		.align	2
 171              	.L12:
 172 006c 00000000 		.word	g_dji_handle
 173 0070 00000000 		.word	reset_flag
 174 0074 00000000 		.word	count.1
 175 0078 00000000 		.word	B11A1_DW
 176 007c 00000000 		.word	.LC4
 177 0080 00ED00E0 		.word	-536810240
ARM GAS  /tmp/cciZ31jV.s 			page 36


 178 0084 0400FA05 		.word	100270084
 179              	.LBE17:
 180              	.LBE16:
 181              		.cfi_endproc
 182              	.LFE63:
 184              		.section	.text.__protocol_on_message,"ax",%progbits
 185              		.align	1
 186              		.p2align 2,,3
 187              		.syntax unified
 188              		.code	16
 189              		.thumb_func
 191              	__protocol_on_message:
 192              	.LVL8:
 193              	.LFB62:
 561:User/protocol.c ****     CommandUpdate();
 194              		.loc 1 561 1 view -0
 195              		.cfi_startproc
 196              		@ args = 0, pretend = 0, frame = 24
 197              		@ frame_needed = 0, uses_anonymous_args = 0
 561:User/protocol.c ****     CommandUpdate();
 198              		.loc 1 561 1 is_stmt 0 view .LVU43
 199 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 200              	.LCFI2:
 201              		.cfi_def_cfa_offset 20
 202              		.cfi_offset 4, -20
 203              		.cfi_offset 5, -16
 204              		.cfi_offset 6, -12
 205              		.cfi_offset 7, -8
 206              		.cfi_offset 14, -4
 207 0002 CE46     		mov	lr, r9
 208 0004 4746     		mov	r7, r8
 209 0006 0C00     		movs	r4, r1
 210 0008 80B5     		push	{r7, lr}
 211              	.LCFI3:
 212              		.cfi_def_cfa_offset 28
 213              		.cfi_offset 8, -28
 214              		.cfi_offset 9, -24
 215 000a 87B0     		sub	sp, sp, #28
 216              	.LCFI4:
 217              		.cfi_def_cfa_offset 56
 561:User/protocol.c ****     CommandUpdate();
 218              		.loc 1 561 1 view .LVU44
 219 000c 0500     		movs	r5, r0
 562:User/protocol.c ****     switch (message->cmd)
 220              		.loc 1 562 5 is_stmt 1 view .LVU45
 221 000e FFF7FEFF 		bl	CommandUpdate
 222              	.LVL9:
 563:User/protocol.c ****     {
 223              		.loc 1 563 5 view .LVU46
 224 0012 2388     		ldrh	r3, [r4]
 225 0014 722B     		cmp	r3, #114
 226 0016 0FD8     		bhi	.L14
 227 0018 D54A     		ldr	r2, .L78
 228 001a 9B00     		lsls	r3, r3, #2
 229 001c D358     		ldr	r3, [r2, r3]
 230 001e 9F46     		mov	pc, r3
 231              		.section	.rodata.__protocol_on_message,"a",%progbits
ARM GAS  /tmp/cciZ31jV.s 			page 37


 232              		.align	2
 233              	.L17:
 234 0000 38000000 		.word	.L14
 235 0004 60000000 		.word	.L32
 236 0008 38000000 		.word	.L14
 237 000c 20000000 		.word	.L31
 238 0010 84000000 		.word	.L30
 239 0014 A2000000 		.word	.L29
 240 0018 DA000000 		.word	.L28
 241 001c 1C010000 		.word	.L27
 242 0020 38000000 		.word	.L14
 243 0024 38000000 		.word	.L14
 244 0028 38000000 		.word	.L14
 245 002c 38000000 		.word	.L14
 246 0030 38000000 		.word	.L14
 247 0034 38000000 		.word	.L14
 248 0038 38000000 		.word	.L14
 249 003c 38000000 		.word	.L14
 250 0040 38000000 		.word	.L14
 251 0044 38000000 		.word	.L14
 252 0048 3C010000 		.word	.L26
 253 004c 6A010000 		.word	.L25
 254 0050 38000000 		.word	.L14
 255 0054 EA010000 		.word	.L24
 256 0058 FC010000 		.word	.L23
 257 005c 22020000 		.word	.L22
 258 0060 38000000 		.word	.L14
 259 0064 38000000 		.word	.L14
 260 0068 38000000 		.word	.L14
 261 006c 38000000 		.word	.L14
 262 0070 38000000 		.word	.L14
 263 0074 38000000 		.word	.L14
 264 0078 38000000 		.word	.L14
 265 007c 38000000 		.word	.L14
 266 0080 38020000 		.word	.L21
 267 0084 C8020000 		.word	.L20
 268 0088 38000000 		.word	.L14
 269 008c 38000000 		.word	.L14
 270 0090 38000000 		.word	.L14
 271 0094 38000000 		.word	.L14
 272 0098 38000000 		.word	.L14
 273 009c 38000000 		.word	.L14
 274 00a0 38000000 		.word	.L14
 275 00a4 38000000 		.word	.L14
 276 00a8 38000000 		.word	.L14
 277 00ac 38000000 		.word	.L14
 278 00b0 38000000 		.word	.L14
 279 00b4 38000000 		.word	.L14
 280 00b8 38000000 		.word	.L14
 281 00bc 38000000 		.word	.L14
 282 00c0 38000000 		.word	.L14
 283 00c4 38000000 		.word	.L14
 284 00c8 38000000 		.word	.L14
 285 00cc 38000000 		.word	.L14
 286 00d0 38000000 		.word	.L14
 287 00d4 38000000 		.word	.L14
 288 00d8 38000000 		.word	.L14
ARM GAS  /tmp/cciZ31jV.s 			page 38


 289 00dc 38000000 		.word	.L14
 290 00e0 38000000 		.word	.L14
 291 00e4 38000000 		.word	.L14
 292 00e8 38000000 		.word	.L14
 293 00ec 38000000 		.word	.L14
 294 00f0 38000000 		.word	.L14
 295 00f4 38000000 		.word	.L14
 296 00f8 38000000 		.word	.L14
 297 00fc 38000000 		.word	.L14
 298 0100 38000000 		.word	.L14
 299 0104 38000000 		.word	.L14
 300 0108 38000000 		.word	.L14
 301 010c 38000000 		.word	.L14
 302 0110 38000000 		.word	.L14
 303 0114 38000000 		.word	.L14
 304 0118 38000000 		.word	.L14
 305 011c 38000000 		.word	.L14
 306 0120 38000000 		.word	.L14
 307 0124 38000000 		.word	.L14
 308 0128 38000000 		.word	.L14
 309 012c 38000000 		.word	.L14
 310 0130 38000000 		.word	.L14
 311 0134 38000000 		.word	.L14
 312 0138 38000000 		.word	.L14
 313 013c 38000000 		.word	.L14
 314 0140 38000000 		.word	.L14
 315 0144 38000000 		.word	.L14
 316 0148 38000000 		.word	.L14
 317 014c 38000000 		.word	.L14
 318 0150 38000000 		.word	.L14
 319 0154 38000000 		.word	.L14
 320 0158 38000000 		.word	.L14
 321 015c 38000000 		.word	.L14
 322 0160 38000000 		.word	.L14
 323 0164 38000000 		.word	.L14
 324 0168 38000000 		.word	.L14
 325 016c 38000000 		.word	.L14
 326 0170 38000000 		.word	.L14
 327 0174 38000000 		.word	.L14
 328 0178 38000000 		.word	.L14
 329 017c 38000000 		.word	.L14
 330 0180 38000000 		.word	.L14
 331 0184 38000000 		.word	.L14
 332 0188 38000000 		.word	.L14
 333 018c 38000000 		.word	.L14
 334 0190 38000000 		.word	.L14
 335 0194 38000000 		.word	.L14
 336 0198 38000000 		.word	.L14
 337 019c 38000000 		.word	.L14
 338 01a0 38000000 		.word	.L14
 339 01a4 38000000 		.word	.L14
 340 01a8 38000000 		.word	.L14
 341 01ac 38000000 		.word	.L14
 342 01b0 38000000 		.word	.L14
 343 01b4 38000000 		.word	.L14
 344 01b8 38000000 		.word	.L14
 345 01bc 38000000 		.word	.L14
ARM GAS  /tmp/cciZ31jV.s 			page 39


 346 01c0 48030000 		.word	.L19
 347 01c4 A8030000 		.word	.L18
 348 01c8 42000000 		.word	.L16
 349              		.section	.text.__protocol_on_message
 350              	.L31:
 570:User/protocol.c ****         break;
 351              		.loc 1 570 9 view .LVU47
 352              	.LVL10:
 353              	.LBB54:
 354              	.LBI54:
  91:User/protocol.c **** {
 355              		.loc 1 91 13 view .LVU48
 356              	.LBB55:
  93:User/protocol.c ****     if (message->len != sizeof(g_save.activate.sn))
 357              		.loc 1 93 5 view .LVU49
  94:User/protocol.c ****     {
 358              		.loc 1 94 5 view .LVU50
  94:User/protocol.c ****     {
 359              		.loc 1 94 8 is_stmt 0 view .LVU51
 360 0020 6388     		ldrh	r3, [r4, #2]
  96:User/protocol.c ****     }
 361              		.loc 1 96 14 view .LVU52
 362 0022 6E46     		mov	r6, sp
  94:User/protocol.c ****     {
 363              		.loc 1 94 8 view .LVU53
 364 0024 0E2B     		cmp	r3, #14
 365 0026 00D1     		bne	.LCB184
 366 0028 EAE1     		b	.L33	@long jump
 367              	.LCB184:
  96:User/protocol.c ****     }
 368              		.loc 1 96 9 is_stmt 1 view .LVU54
  96:User/protocol.c ****     }
 369              		.loc 1 96 14 is_stmt 0 view .LVU55
 370 002a 0123     		movs	r3, #1
 371 002c 3370     		strb	r3, [r6]
 372              	.LVL11:
 373              	.L39:
  96:User/protocol.c ****     }
 374              		.loc 1 96 14 view .LVU56
 375              	.LBE55:
 376              	.LBE54:
 377              	.LBB57:
 378              	.LBB58:
 256:User/protocol.c **** }
 379              		.loc 1 256 5 is_stmt 1 view .LVU57
 380 002e 0122     		movs	r2, #1
 381 0030 3100     		movs	r1, r6
 382 0032 2800     		movs	r0, r5
 383 0034 FFF7FEFF 		bl	dji_echo
 384              	.LVL12:
 385              	.L14:
 256:User/protocol.c **** }
 386              		.loc 1 256 5 is_stmt 0 view .LVU58
 387              	.LBE58:
 388              	.LBE57:
 636:User/protocol.c **** 
 389              		.loc 1 636 1 view .LVU59
ARM GAS  /tmp/cciZ31jV.s 			page 40


 390 0038 07B0     		add	sp, sp, #28
 391              		@ sp needed
 392              	.LVL13:
 636:User/protocol.c **** 
 393              		.loc 1 636 1 view .LVU60
 394 003a C0BC     		pop	{r6, r7}
 395 003c B946     		mov	r9, r7
 396 003e B046     		mov	r8, r6
 397 0040 F0BD     		pop	{r4, r5, r6, r7, pc}
 398              	.LVL14:
 399              	.L16:
 630:User/protocol.c ****         break;
 400              		.loc 1 630 9 is_stmt 1 view .LVU61
 401              	.LBB61:
 402              	.LBI61:
 541:User/protocol.c **** {
 403              		.loc 1 541 13 view .LVU62
 404              	.LBB62:
 544:User/protocol.c ****     {
 405              		.loc 1 544 5 view .LVU63
 547:User/protocol.c **** #pragma pack()
 406              		.loc 1 547 7 is_stmt 0 view .LVU64
 407 0042 6A46     		mov	r2, sp
 408 0044 0023     		movs	r3, #0
 409 0046 1370     		strb	r3, [r2]
 549:User/protocol.c ****     save_flag(0);
 410              		.loc 1 549 5 is_stmt 1 view .LVU65
 549:User/protocol.c ****     save_flag(0);
 411              		.loc 1 549 16 is_stmt 0 view .LVU66
 412 0048 0122     		movs	r2, #1
 413 004a CA4B     		ldr	r3, .L78+4
 550:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 414              		.loc 1 550 5 view .LVU67
 415 004c 0020     		movs	r0, #0
 549:User/protocol.c ****     save_flag(0);
 416              		.loc 1 549 16 view .LVU68
 417 004e 1A70     		strb	r2, [r3]
 550:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 418              		.loc 1 550 5 is_stmt 1 view .LVU69
 419 0050 FFF7FEFF 		bl	save_flag
 420              	.LVL15:
 551:User/protocol.c **** }
 421              		.loc 1 551 5 view .LVU70
 422 0054 0122     		movs	r2, #1
 423 0056 6946     		mov	r1, sp
 424 0058 2800     		movs	r0, r5
 425 005a FFF7FEFF 		bl	dji_echo
 426              	.LVL16:
 551:User/protocol.c **** }
 427              		.loc 1 551 5 is_stmt 0 view .LVU71
 428              	.LBE62:
 429              	.LBE61:
 631:User/protocol.c **** 
 430              		.loc 1 631 9 is_stmt 1 view .LVU72
 636:User/protocol.c **** 
 431              		.loc 1 636 1 is_stmt 0 view .LVU73
 432 005e EBE7     		b	.L14
ARM GAS  /tmp/cciZ31jV.s 			page 41


 433              	.L32:
 566:User/protocol.c ****         break;
 434              		.loc 1 566 9 is_stmt 1 view .LVU74
 435              	.LVL17:
 436              	.LBB63:
 437              	.LBI63:
  63:User/protocol.c **** {
 438              		.loc 1 63 13 view .LVU75
 439              	.LBB64:
  67:User/protocol.c ****     {
 440              		.loc 1 67 5 view .LVU76
  80:User/protocol.c ****     memcpy(&echo.loader, (uint8_t *)ADDR_VER_LD, sizeof(echo.loader));
 441              		.loc 1 80 5 view .LVU77
 442 0060 C54C     		ldr	r4, .L78+8
 443              	.LVL18:
  80:User/protocol.c ****     memcpy(&echo.loader, (uint8_t *)ADDR_VER_LD, sizeof(echo.loader));
 444              		.loc 1 80 5 is_stmt 0 view .LVU78
 445 0062 1022     		movs	r2, #16
 446 0064 C549     		ldr	r1, .L78+12
 447 0066 601C     		adds	r0, r4, #1
 448 0068 FFF7FEFF 		bl	memcpy
 449              	.LVL19:
  81:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 450              		.loc 1 81 5 is_stmt 1 view .LVU79
 451 006c 2000     		movs	r0, r4
 452 006e 0222     		movs	r2, #2
 453 0070 C349     		ldr	r1, .L78+16
 454 0072 1130     		adds	r0, r0, #17
 455 0074 FFF7FEFF 		bl	memcpy
 456              	.LVL20:
  82:User/protocol.c **** }
 457              		.loc 1 82 5 view .LVU80
 458 0078 1522     		movs	r2, #21
 459 007a 2100     		movs	r1, r4
 460 007c 2800     		movs	r0, r5
 461 007e FFF7FEFF 		bl	dji_echo
 462              	.LVL21:
  82:User/protocol.c **** }
 463              		.loc 1 82 5 is_stmt 0 view .LVU81
 464              	.LBE64:
 465              	.LBE63:
 567:User/protocol.c **** 
 466              		.loc 1 567 9 is_stmt 1 view .LVU82
 467              	.LBB66:
 468              	.LBB65:
  83:User/protocol.c **** 
 469              		.loc 1 83 1 is_stmt 0 view .LVU83
 470 0082 D9E7     		b	.L14
 471              	.LVL22:
 472              	.L30:
  83:User/protocol.c **** 
 473              		.loc 1 83 1 view .LVU84
 474              	.LBE65:
 475              	.LBE66:
 574:User/protocol.c ****         break;
 476              		.loc 1 574 9 is_stmt 1 view .LVU85
 477              	.LBB67:
ARM GAS  /tmp/cciZ31jV.s 			page 42


 478              	.LBI67:
 113:User/protocol.c **** {
 479              		.loc 1 113 13 view .LVU86
 480              	.LBB68:
 116:User/protocol.c ****     {
 481              		.loc 1 116 5 view .LVU87
 120:User/protocol.c **** #pragma pack()
 482              		.loc 1 120 7 is_stmt 0 view .LVU88
 483 0084 6A46     		mov	r2, sp
 484 0086 0023     		movs	r3, #0
 485 0088 1370     		strb	r3, [r2]
 122:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 486              		.loc 1 122 5 is_stmt 1 view .LVU89
 487 008a 6B46     		mov	r3, sp
 488 008c 0E22     		movs	r2, #14
 489 008e BD49     		ldr	r1, .L78+20
 490 0090 581C     		adds	r0, r3, #1
 491 0092 FFF7FEFF 		bl	memcpy
 492              	.LVL23:
 123:User/protocol.c **** }
 493              		.loc 1 123 5 view .LVU90
 494 0096 0F22     		movs	r2, #15
 495 0098 6946     		mov	r1, sp
 496 009a 2800     		movs	r0, r5
 497 009c FFF7FEFF 		bl	dji_echo
 498              	.LVL24:
 123:User/protocol.c **** }
 499              		.loc 1 123 5 is_stmt 0 view .LVU91
 500              	.LBE68:
 501              	.LBE67:
 575:User/protocol.c **** 
 502              		.loc 1 575 9 is_stmt 1 view .LVU92
 503              	.LBB70:
 504              	.LBB69:
 124:User/protocol.c **** 
 505              		.loc 1 124 1 is_stmt 0 view .LVU93
 506 00a0 CAE7     		b	.L14
 507              	.L29:
 124:User/protocol.c **** 
 508              		.loc 1 124 1 view .LVU94
 509              	.LBE69:
 510              	.LBE70:
 578:User/protocol.c ****         break;
 511              		.loc 1 578 9 is_stmt 1 view .LVU95
 512              	.LVL25:
 513              	.LBB71:
 514              	.LBI71:
 132:User/protocol.c **** {
 515              		.loc 1 132 13 view .LVU96
 516              	.LBB72:
 136:User/protocol.c ****     {
 517              		.loc 1 136 5 view .LVU97
 146:User/protocol.c **** #pragma pack()
 518              		.loc 1 146 7 is_stmt 0 view .LVU98
 519 00a2 6946     		mov	r1, sp
 146:User/protocol.c **** #pragma pack()
 520              		.loc 1 146 39 view .LVU99
ARM GAS  /tmp/cciZ31jV.s 			page 43


 521 00a4 B74B     		ldr	r3, .L78+20
 146:User/protocol.c **** #pragma pack()
 522              		.loc 1 146 7 view .LVU100
 523 00a6 9A7B     		ldrb	r2, [r3, #14]
 524 00a8 0A70     		strb	r2, [r1]
 149:User/protocol.c ****     echo.month = g_save.activate.month;
 525              		.loc 1 149 5 is_stmt 1 view .LVU101
 149:User/protocol.c ****     echo.month = g_save.activate.month;
 526              		.loc 1 149 15 is_stmt 0 view .LVU102
 527 00aa 187C     		ldrb	r0, [r3, #16]
 528 00ac 4870     		strb	r0, [r1, #1]
 529 00ae 587C     		ldrb	r0, [r3, #17]
 530 00b0 8870     		strb	r0, [r1, #2]
 150:User/protocol.c ****     echo.day = g_save.activate.day;
 531              		.loc 1 150 5 is_stmt 1 view .LVU103
 150:User/protocol.c ****     echo.day = g_save.activate.day;
 532              		.loc 1 150 16 is_stmt 0 view .LVU104
 533 00b2 9A7C     		ldrb	r2, [r3, #18]
 534 00b4 CA70     		strb	r2, [r1, #3]
 151:User/protocol.c ****     echo.hour = g_save.activate.hour;
 535              		.loc 1 151 5 is_stmt 1 view .LVU105
 151:User/protocol.c ****     echo.hour = g_save.activate.hour;
 536              		.loc 1 151 14 is_stmt 0 view .LVU106
 537 00b6 DA7C     		ldrb	r2, [r3, #19]
 538 00b8 0A71     		strb	r2, [r1, #4]
 152:User/protocol.c ****     echo.minute = g_save.activate.minute;
 539              		.loc 1 152 5 is_stmt 1 view .LVU107
 152:User/protocol.c ****     echo.minute = g_save.activate.minute;
 540              		.loc 1 152 15 is_stmt 0 view .LVU108
 541 00ba 1A7D     		ldrb	r2, [r3, #20]
 542 00bc 4A71     		strb	r2, [r1, #5]
 153:User/protocol.c ****     echo.second = g_save.activate.second;
 543              		.loc 1 153 5 is_stmt 1 view .LVU109
 153:User/protocol.c ****     echo.second = g_save.activate.second;
 544              		.loc 1 153 17 is_stmt 0 view .LVU110
 545 00be 5A7D     		ldrb	r2, [r3, #21]
 546 00c0 8A71     		strb	r2, [r1, #6]
 154:User/protocol.c ****     memcpy(echo.sn, g_save.activate.sn, sizeof(echo.sn));
 547              		.loc 1 154 5 is_stmt 1 view .LVU111
 154:User/protocol.c ****     memcpy(echo.sn, g_save.activate.sn, sizeof(echo.sn));
 548              		.loc 1 154 17 is_stmt 0 view .LVU112
 549 00c2 9A7D     		ldrb	r2, [r3, #22]
 550 00c4 CA71     		strb	r2, [r1, #7]
 155:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 551              		.loc 1 155 5 is_stmt 1 view .LVU113
 552 00c6 02AA     		add	r2, sp, #8
 553 00c8 51CB     		ldmia	r3!, {r0, r4, r6}
 554 00ca 51C2     		stmia	r2!, {r0, r4, r6}
 555              	.LVL26:
 155:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 556              		.loc 1 155 5 is_stmt 0 view .LVU114
 557 00cc 1B88     		ldrh	r3, [r3]
 156:User/protocol.c **** }
 558              		.loc 1 156 5 view .LVU115
 559 00ce 2800     		movs	r0, r5
 155:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 560              		.loc 1 155 5 view .LVU116
ARM GAS  /tmp/cciZ31jV.s 			page 44


 561 00d0 1380     		strh	r3, [r2]
 156:User/protocol.c **** }
 562              		.loc 1 156 5 is_stmt 1 view .LVU117
 563 00d2 1622     		movs	r2, #22
 564 00d4 FFF7FEFF 		bl	dji_echo
 565              	.LVL27:
 156:User/protocol.c **** }
 566              		.loc 1 156 5 is_stmt 0 view .LVU118
 567              	.LBE72:
 568              	.LBE71:
 579:User/protocol.c **** 
 569              		.loc 1 579 9 is_stmt 1 view .LVU119
 570              	.LBB74:
 571              	.LBB73:
 157:User/protocol.c **** 
 572              		.loc 1 157 1 is_stmt 0 view .LVU120
 573 00d8 AEE7     		b	.L14
 574              	.LVL28:
 575              	.L28:
 157:User/protocol.c **** 
 576              		.loc 1 157 1 view .LVU121
 577              	.LBE73:
 578              	.LBE74:
 582:User/protocol.c ****         break;
 579              		.loc 1 582 9 is_stmt 1 view .LVU122
 580              	.LBB75:
 581              	.LBI75:
 165:User/protocol.c **** {
 582              		.loc 1 165 13 view .LVU123
 583              	.LBB76:
 168:User/protocol.c ****     {
 584              		.loc 1 168 5 view .LVU124
 181:User/protocol.c ****     {
 585              		.loc 1 181 5 view .LVU125
 181:User/protocol.c ****     {
 586              		.loc 1 181 8 is_stmt 0 view .LVU126
 587 00da 6388     		ldrh	r3, [r4, #2]
 183:User/protocol.c ****         memcpy(&echo.year, message->data, 7);
 588              		.loc 1 183 19 view .LVU127
 589 00dc 6E46     		mov	r6, sp
 181:User/protocol.c ****     {
 590              		.loc 1 181 8 view .LVU128
 591 00de 072B     		cmp	r3, #7
 592 00e0 00D1     		bne	.LCB404
 593 00e2 97E1     		b	.L76	@long jump
 594              	.LCB404:
 197:User/protocol.c ****         echo.year = g_save.activate.year;
 595              		.loc 1 197 9 is_stmt 1 view .LVU129
 197:User/protocol.c ****         echo.year = g_save.activate.year;
 596              		.loc 1 197 19 is_stmt 0 view .LVU130
 597 00e4 0123     		movs	r3, #1
 598 00e6 3370     		strb	r3, [r6]
 198:User/protocol.c ****         echo.month = g_save.activate.month;
 599              		.loc 1 198 9 is_stmt 1 view .LVU131
 198:User/protocol.c ****         echo.month = g_save.activate.month;
 600              		.loc 1 198 36 is_stmt 0 view .LVU132
 601 00e8 A64B     		ldr	r3, .L78+20
ARM GAS  /tmp/cciZ31jV.s 			page 45


 198:User/protocol.c ****         echo.month = g_save.activate.month;
 602              		.loc 1 198 19 view .LVU133
 603 00ea 197C     		ldrb	r1, [r3, #16]
 604 00ec 7170     		strb	r1, [r6, #1]
 605 00ee 597C     		ldrb	r1, [r3, #17]
 606 00f0 B170     		strb	r1, [r6, #2]
 199:User/protocol.c ****         echo.day = g_save.activate.day;
 607              		.loc 1 199 9 is_stmt 1 view .LVU134
 199:User/protocol.c ****         echo.day = g_save.activate.day;
 608              		.loc 1 199 20 is_stmt 0 view .LVU135
 609 00f2 9A7C     		ldrb	r2, [r3, #18]
 610 00f4 F270     		strb	r2, [r6, #3]
 200:User/protocol.c ****         echo.hour = g_save.activate.hour;
 611              		.loc 1 200 9 is_stmt 1 view .LVU136
 200:User/protocol.c ****         echo.hour = g_save.activate.hour;
 612              		.loc 1 200 18 is_stmt 0 view .LVU137
 613 00f6 DA7C     		ldrb	r2, [r3, #19]
 614 00f8 3271     		strb	r2, [r6, #4]
 201:User/protocol.c ****         echo.minute = g_save.activate.minute;
 615              		.loc 1 201 9 is_stmt 1 view .LVU138
 201:User/protocol.c ****         echo.minute = g_save.activate.minute;
 616              		.loc 1 201 19 is_stmt 0 view .LVU139
 617 00fa 1A7D     		ldrb	r2, [r3, #20]
 618 00fc 7271     		strb	r2, [r6, #5]
 202:User/protocol.c ****         echo.second = g_save.activate.second;
 619              		.loc 1 202 9 is_stmt 1 view .LVU140
 202:User/protocol.c ****         echo.second = g_save.activate.second;
 620              		.loc 1 202 21 is_stmt 0 view .LVU141
 621 00fe 5A7D     		ldrb	r2, [r3, #21]
 622 0100 B271     		strb	r2, [r6, #6]
 203:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 623              		.loc 1 203 9 is_stmt 1 view .LVU142
 203:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 624              		.loc 1 203 21 is_stmt 0 view .LVU143
 625 0102 9A7D     		ldrb	r2, [r3, #22]
 626 0104 F271     		strb	r2, [r6, #7]
 204:User/protocol.c ****     }
 627              		.loc 1 204 9 is_stmt 1 view .LVU144
 628 0106 02AA     		add	r2, sp, #8
 629 0108 13CB     		ldmia	r3!, {r0, r1, r4}
 630 010a 13C2     		stmia	r2!, {r0, r1, r4}
 631              	.LVL29:
 204:User/protocol.c ****     }
 632              		.loc 1 204 9 is_stmt 0 view .LVU145
 633 010c 1B88     		ldrh	r3, [r3]
 634 010e 1380     		strh	r3, [r2]
 635              	.L36:
 207:User/protocol.c **** }
 636              		.loc 1 207 5 is_stmt 1 view .LVU146
 637 0110 1622     		movs	r2, #22
 638 0112 3100     		movs	r1, r6
 639 0114 2800     		movs	r0, r5
 640 0116 FFF7FEFF 		bl	dji_echo
 641              	.LVL30:
 207:User/protocol.c **** }
 642              		.loc 1 207 5 is_stmt 0 view .LVU147
 643              	.LBE76:
ARM GAS  /tmp/cciZ31jV.s 			page 46


 644              	.LBE75:
 583:User/protocol.c **** 
 645              		.loc 1 583 9 is_stmt 1 view .LVU148
 646              	.LBB79:
 647              	.LBB77:
 208:User/protocol.c **** 
 648              		.loc 1 208 1 is_stmt 0 view .LVU149
 649 011a 8DE7     		b	.L14
 650              	.LVL31:
 651              	.L27:
 208:User/protocol.c **** 
 652              		.loc 1 208 1 view .LVU150
 653              	.LBE77:
 654              	.LBE79:
 586:User/protocol.c ****         break;
 655              		.loc 1 586 9 is_stmt 1 view .LVU151
 656              	.LBB80:
 657              	.LBI80:
 216:User/protocol.c **** {
 658              		.loc 1 216 13 view .LVU152
 659              	.LBB81:
 219:User/protocol.c ****     g_save.activate.state = true;
 660              		.loc 1 219 5 view .LVU153
 219:User/protocol.c ****     g_save.activate.state = true;
 661              		.loc 1 219 13 is_stmt 0 view .LVU154
 662 011c 0023     		movs	r3, #0
 663 011e 6A46     		mov	r2, sp
 221:User/protocol.c ****     save_write();
 664              		.loc 1 221 5 view .LVU155
 665 0120 0021     		movs	r1, #0
 219:User/protocol.c ****     g_save.activate.state = true;
 666              		.loc 1 219 13 view .LVU156
 667 0122 1370     		strb	r3, [r2]
 220:User/protocol.c ****     memset(&g_save.activate, 0, sizeof(g_save.activate));
 668              		.loc 1 220 5 is_stmt 1 view .LVU157
 221:User/protocol.c ****     save_write();
 669              		.loc 1 221 5 view .LVU158
 670 0124 9748     		ldr	r0, .L78+20
 671 0126 1822     		movs	r2, #24
 672 0128 FFF7FEFF 		bl	memset
 673              	.LVL32:
 222:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 674              		.loc 1 222 5 view .LVU159
 675 012c FFF7FEFF 		bl	save_write
 676              	.LVL33:
 223:User/protocol.c **** }
 677              		.loc 1 223 5 view .LVU160
 678 0130 0122     		movs	r2, #1
 679 0132 6946     		mov	r1, sp
 680 0134 2800     		movs	r0, r5
 681 0136 FFF7FEFF 		bl	dji_echo
 682              	.LVL34:
 223:User/protocol.c **** }
 683              		.loc 1 223 5 is_stmt 0 view .LVU161
 684              	.LBE81:
 685              	.LBE80:
 587:User/protocol.c **** 
ARM GAS  /tmp/cciZ31jV.s 			page 47


 686              		.loc 1 587 9 is_stmt 1 view .LVU162
 687              	.LBB83:
 688              	.LBB82:
 224:User/protocol.c **** 
 689              		.loc 1 224 1 is_stmt 0 view .LVU163
 690 013a 7DE7     		b	.L14
 691              	.L26:
 224:User/protocol.c **** 
 692              		.loc 1 224 1 view .LVU164
 693              	.LBE82:
 694              	.LBE83:
 590:User/protocol.c ****         break;
 695              		.loc 1 590 9 is_stmt 1 view .LVU165
 696              	.LVL35:
 697              	.LBB84:
 698              	.LBI57:
 232:User/protocol.c **** {
 699              		.loc 1 232 13 view .LVU166
 700              	.LBB59:
 235:User/protocol.c **** 
 701              		.loc 1 235 5 view .LVU167
 237:User/protocol.c ****     {
 702              		.loc 1 237 5 view .LVU168
 237:User/protocol.c ****     {
 703              		.loc 1 237 8 is_stmt 0 view .LVU169
 704 013c 6388     		ldrh	r3, [r4, #2]
 705 013e 012B     		cmp	r3, #1
 706 0140 00D0     		beq	.LCB507
 707 0142 79E7     		b	.L14	@long jump
 708              	.LCB507:
 241:User/protocol.c ****     {
 709              		.loc 1 241 10 is_stmt 1 view .LVU170
 241:User/protocol.c ****     {
 710              		.loc 1 241 27 is_stmt 0 view .LVU171
 711 0144 6368     		ldr	r3, [r4, #4]
 712 0146 1B78     		ldrb	r3, [r3]
 241:User/protocol.c ****     {
 713              		.loc 1 241 13 view .LVU172
 714 0148 012B     		cmp	r3, #1
 715 014a 00D1     		bne	.LCB512
 716 014c F9E1     		b	.L77	@long jump
 717              	.LCB512:
 245:User/protocol.c ****     {
 718              		.loc 1 245 10 is_stmt 1 view .LVU173
 245:User/protocol.c ****     {
 719              		.loc 1 245 13 is_stmt 0 view .LVU174
 720 014e 022B     		cmp	r3, #2
 721 0150 00D0     		beq	.LCB515
 722 0152 71E7     		b	.L14	@long jump
 723              	.LCB515:
 247:User/protocol.c ****         Save.Flag = NoStoredInfo;
 724              		.loc 1 247 9 is_stmt 1 view .LVU175
 247:User/protocol.c ****         Save.Flag = NoStoredInfo;
 725              		.loc 1 247 14 is_stmt 0 view .LVU176
 726 0154 6E46     		mov	r6, sp
 248:User/protocol.c ****         B11A1_U.Control.Mode = CalibrationMode;
 727              		.loc 1 248 19 view .LVU177
ARM GAS  /tmp/cciZ31jV.s 			page 48


 728 0156 0022     		movs	r2, #0
 247:User/protocol.c ****         Save.Flag = NoStoredInfo;
 729              		.loc 1 247 28 view .LVU178
 730 0158 8B4B     		ldr	r3, .L78+24
 247:User/protocol.c ****         Save.Flag = NoStoredInfo;
 731              		.loc 1 247 14 view .LVU179
 732 015a 1B7B     		ldrb	r3, [r3, #12]
 733 015c 3370     		strb	r3, [r6]
 248:User/protocol.c ****         B11A1_U.Control.Mode = CalibrationMode;
 734              		.loc 1 248 9 is_stmt 1 view .LVU180
 248:User/protocol.c ****         B11A1_U.Control.Mode = CalibrationMode;
 735              		.loc 1 248 19 is_stmt 0 view .LVU181
 736 015e 8B4B     		ldr	r3, .L78+28
 737 0160 1A70     		strb	r2, [r3]
 249:User/protocol.c ****     }
 738              		.loc 1 249 9 is_stmt 1 view .LVU182
 249:User/protocol.c ****     }
 739              		.loc 1 249 30 is_stmt 0 view .LVU183
 740 0162 8B4B     		ldr	r3, .L78+32
 741 0164 013A     		subs	r2, r2, #1
 742 0166 5A61     		str	r2, [r3, #20]
 743 0168 61E7     		b	.L39
 744              	.LVL36:
 745              	.L25:
 249:User/protocol.c ****     }
 746              		.loc 1 249 30 view .LVU184
 747              	.LBE59:
 748              	.LBE84:
 594:User/protocol.c ****         break;
 749              		.loc 1 594 9 is_stmt 1 view .LVU185
 750              	.LBB85:
 751              	.LBI85:
 265:User/protocol.c **** {
 752              		.loc 1 265 13 view .LVU186
 753              	.LBB86:
 268:User/protocol.c ****     {
 754              		.loc 1 268 5 view .LVU187
 278:User/protocol.c **** #pragma pack()
 755              		.loc 1 278 7 is_stmt 0 view .LVU188
 756 016a 0F22     		movs	r2, #15
 757 016c 0021     		movs	r1, #0
 758 016e 6846     		mov	r0, sp
 759 0170 FFF7FEFF 		bl	memset
 760              	.LVL37:
 281:User/protocol.c ****     {
 761              		.loc 1 281 5 is_stmt 1 view .LVU189
 281:User/protocol.c ****     {
 762              		.loc 1 281 8 is_stmt 0 view .LVU190
 763 0174 6388     		ldrh	r3, [r4, #2]
 278:User/protocol.c **** #pragma pack()
 764              		.loc 1 278 7 view .LVU191
 765 0176 6E46     		mov	r6, sp
 281:User/protocol.c ****     {
 766              		.loc 1 281 8 view .LVU192
 767 0178 012B     		cmp	r3, #1
 768 017a 00D0     		beq	.LCB554
 769 017c 5CE7     		b	.L14	@long jump
ARM GAS  /tmp/cciZ31jV.s 			page 49


 770              	.LCB554:
 285:User/protocol.c ****     {
 771              		.loc 1 285 10 is_stmt 1 view .LVU193
 285:User/protocol.c ****     {
 772              		.loc 1 285 27 is_stmt 0 view .LVU194
 773 017e 6368     		ldr	r3, [r4, #4]
 774 0180 1B78     		ldrb	r3, [r3]
 285:User/protocol.c ****     {
 775              		.loc 1 285 13 view .LVU195
 776 0182 002B     		cmp	r3, #0
 777 0184 00D0     		beq	.LCB559
 778 0186 64E1     		b	.L41	@long jump
 779              	.LCB559:
 287:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 780              		.loc 1 287 9 is_stmt 1 view .LVU196
 287:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 781              		.loc 1 287 34 is_stmt 0 view .LVU197
 782 0188 7E4B     		ldr	r3, .L78+20
 287:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 783              		.loc 1 287 20 view .LVU198
 784 018a 1A7E     		ldrb	r2, [r3, #24]
 785 018c 3270     		strb	r2, [r6]
 288:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 786              		.loc 1 288 9 is_stmt 1 view .LVU199
 288:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 787              		.loc 1 288 25 is_stmt 0 view .LVU200
 788 018e 997E     		ldrb	r1, [r3, #26]
 292:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 789              		.loc 1 292 25 view .LVU201
 790 0190 DA8C     		ldrh	r2, [r3, #38]
 288:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 791              		.loc 1 288 25 view .LVU202
 792 0192 7170     		strb	r1, [r6, #1]
 793 0194 D97E     		ldrb	r1, [r3, #27]
 794 0196 B170     		strb	r1, [r6, #2]
 289:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 795              		.loc 1 289 9 is_stmt 1 view .LVU203
 289:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 796              		.loc 1 289 25 is_stmt 0 view .LVU204
 797 0198 997F     		ldrb	r1, [r3, #30]
 798 019a F170     		strb	r1, [r6, #3]
 799 019c D97F     		ldrb	r1, [r3, #31]
 800 019e 3171     		strb	r1, [r6, #4]
 290:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 801              		.loc 1 290 9 is_stmt 1 view .LVU205
 290:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 802              		.loc 1 290 25 is_stmt 0 view .LVU206
 803 01a0 197F     		ldrb	r1, [r3, #28]
 804 01a2 7171     		strb	r1, [r6, #5]
 805 01a4 597F     		ldrb	r1, [r3, #29]
 806 01a6 B171     		strb	r1, [r6, #6]
 291:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
 807              		.loc 1 291 9 is_stmt 1 view .LVU207
 291:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
 808              		.loc 1 291 25 is_stmt 0 view .LVU208
 809 01a8 2021     		movs	r1, #32
 810 01aa 595C     		ldrb	r1, [r3, r1]
ARM GAS  /tmp/cciZ31jV.s 			page 50


 811 01ac F171     		strb	r1, [r6, #7]
 812 01ae 2121     		movs	r1, #33
 813 01b0 595C     		ldrb	r1, [r3, r1]
 814 01b2 3172     		strb	r1, [r6, #8]
 292:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 815              		.loc 1 292 9 is_stmt 1 view .LVU209
 292:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 816              		.loc 1 292 25 is_stmt 0 view .LVU210
 817 01b4 0921     		movs	r1, #9
 818 01b6 6944     		add	r1, r1, sp
 819 01b8 0A70     		strb	r2, [r1]
 820 01ba 120A     		lsrs	r2, r2, #8
 821 01bc 4A70     		strb	r2, [r1, #1]
 293:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 822              		.loc 1 293 9 is_stmt 1 view .LVU211
 293:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 823              		.loc 1 293 29 is_stmt 0 view .LVU212
 824 01be 3021     		movs	r1, #48
 825 01c0 0B22     		movs	r2, #11
 826 01c2 595C     		ldrb	r1, [r3, r1]
 827 01c4 6A44     		add	r2, r2, sp
 828 01c6 1170     		strb	r1, [r2]
 829 01c8 3121     		movs	r1, #49
 830 01ca 595C     		ldrb	r1, [r3, r1]
 831 01cc 5170     		strb	r1, [r2, #1]
 294:User/protocol.c ****     }
 832              		.loc 1 294 9 is_stmt 1 view .LVU213
 294:User/protocol.c ****     }
 833              		.loc 1 294 29 is_stmt 0 view .LVU214
 834 01ce 3221     		movs	r1, #50
 835 01d0 0D22     		movs	r2, #13
 836 01d2 595C     		ldrb	r1, [r3, r1]
 837 01d4 6A44     		add	r2, r2, sp
 838 01d6 1170     		strb	r1, [r2]
 839 01d8 3321     		movs	r1, #51
 840 01da 5B5C     		ldrb	r3, [r3, r1]
 841 01dc 5370     		strb	r3, [r2, #1]
 842              	.L42:
 315:User/protocol.c **** }
 843              		.loc 1 315 5 is_stmt 1 view .LVU215
 844 01de 0F22     		movs	r2, #15
 845 01e0 3100     		movs	r1, r6
 846 01e2 2800     		movs	r0, r5
 847 01e4 FFF7FEFF 		bl	dji_echo
 848              	.LVL38:
 849 01e8 26E7     		b	.L14
 850              	.LVL39:
 851              	.L24:
 315:User/protocol.c **** }
 852              		.loc 1 315 5 is_stmt 0 view .LVU216
 853              	.LBE86:
 854              	.LBE85:
 598:User/protocol.c ****         break;
 855              		.loc 1 598 9 is_stmt 1 view .LVU217
 856              	.LBB88:
 857              	.LBI88:
 324:User/protocol.c **** {
ARM GAS  /tmp/cciZ31jV.s 			page 51


 858              		.loc 1 324 13 view .LVU218
 859              	.LBB89:
 326:User/protocol.c ****     dji_echo(self, &fault, sizeof(fault));
 860              		.loc 1 326 5 view .LVU219
 326:User/protocol.c ****     dji_echo(self, &fault, sizeof(fault));
 861              		.loc 1 326 21 is_stmt 0 view .LVU220
 862 01ea FFF7FEFF 		bl	motor_get_fault
 863              	.LVL40:
 326:User/protocol.c ****     dji_echo(self, &fault, sizeof(fault));
 864              		.loc 1 326 13 discriminator 1 view .LVU221
 865 01ee 6946     		mov	r1, sp
 327:User/protocol.c **** }
 866              		.loc 1 327 5 view .LVU222
 867 01f0 0122     		movs	r2, #1
 326:User/protocol.c ****     dji_echo(self, &fault, sizeof(fault));
 868              		.loc 1 326 13 discriminator 1 view .LVU223
 869 01f2 0870     		strb	r0, [r1]
 327:User/protocol.c **** }
 870              		.loc 1 327 5 is_stmt 1 view .LVU224
 871 01f4 2800     		movs	r0, r5
 872 01f6 FFF7FEFF 		bl	dji_echo
 873              	.LVL41:
 327:User/protocol.c **** }
 874              		.loc 1 327 5 is_stmt 0 view .LVU225
 875              	.LBE89:
 876              	.LBE88:
 599:User/protocol.c **** 
 877              		.loc 1 599 9 is_stmt 1 view .LVU226
 878              	.LBB91:
 879              	.LBB90:
 328:User/protocol.c **** 
 880              		.loc 1 328 1 is_stmt 0 view .LVU227
 881 01fa 1DE7     		b	.L14
 882              	.L23:
 328:User/protocol.c **** 
 883              		.loc 1 328 1 view .LVU228
 884              	.LBE90:
 885              	.LBE91:
 602:User/protocol.c ****         break;
 886              		.loc 1 602 9 is_stmt 1 view .LVU229
 887              	.LVL42:
 888              	.LBB92:
 889              	.LBI92:
 336:User/protocol.c **** {
 890              		.loc 1 336 13 view .LVU230
 891              	.LBB93:
 339:User/protocol.c ****     if (message->len < 1)
 892              		.loc 1 339 5 view .LVU231
 339:User/protocol.c ****     if (message->len < 1)
 893              		.loc 1 339 13 is_stmt 0 view .LVU232
 894 01fc 0123     		movs	r3, #1
 895 01fe 6A46     		mov	r2, sp
 896 0200 1370     		strb	r3, [r2]
 340:User/protocol.c ****         return;
 897              		.loc 1 340 5 is_stmt 1 view .LVU233
 340:User/protocol.c ****         return;
 898              		.loc 1 340 8 is_stmt 0 view .LVU234
ARM GAS  /tmp/cciZ31jV.s 			page 52


 899 0202 6388     		ldrh	r3, [r4, #2]
 900 0204 002B     		cmp	r3, #0
 901 0206 00D1     		bne	.LCB677
 902 0208 16E7     		b	.L14	@long jump
 903              	.LCB677:
 342:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 904              		.loc 1 342 5 is_stmt 1 view .LVU235
 342:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 905              		.loc 1 342 12 is_stmt 0 view .LVU236
 906 020a 6368     		ldr	r3, [r4, #4]
 907 020c 1878     		ldrb	r0, [r3]
 908 020e FFF7FEFF 		bl	motor_reset_fault
 909              	.LVL43:
 342:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 910              		.loc 1 342 10 discriminator 1 view .LVU237
 911 0212 6B46     		mov	r3, sp
 343:User/protocol.c **** }
 912              		.loc 1 343 5 view .LVU238
 913 0214 0122     		movs	r2, #1
 342:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 914              		.loc 1 342 10 discriminator 1 view .LVU239
 915 0216 1870     		strb	r0, [r3]
 343:User/protocol.c **** }
 916              		.loc 1 343 5 is_stmt 1 view .LVU240
 917 0218 6946     		mov	r1, sp
 918 021a 2800     		movs	r0, r5
 919 021c FFF7FEFF 		bl	dji_echo
 920              	.LVL44:
 921 0220 0AE7     		b	.L14
 922              	.LVL45:
 923              	.L22:
 343:User/protocol.c **** }
 924              		.loc 1 343 5 is_stmt 0 view .LVU241
 925              	.LBE93:
 926              	.LBE92:
 606:User/protocol.c ****         break;
 927              		.loc 1 606 9 is_stmt 1 view .LVU242
 928              	.LBB94:
 929              	.LBI94:
 352:User/protocol.c **** {
 930              		.loc 1 352 13 view .LVU243
 931              	.LBB95:
 358:User/protocol.c ****     memcpy(echo, (uint8_t *)UID_BASE_ADDR, sizeof(echo));
 932              		.loc 1 358 5 view .LVU244
 359:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 933              		.loc 1 359 5 view .LVU245
 934 0222 0C22     		movs	r2, #12
 935 0224 6846     		mov	r0, sp
 936 0226 5B49     		ldr	r1, .L78+36
 937 0228 FFF7FEFF 		bl	memcpy
 938              	.LVL46:
 360:User/protocol.c **** }
 939              		.loc 1 360 5 view .LVU246
 940 022c 0C22     		movs	r2, #12
 941 022e 6946     		mov	r1, sp
 942 0230 2800     		movs	r0, r5
 943 0232 FFF7FEFF 		bl	dji_echo
ARM GAS  /tmp/cciZ31jV.s 			page 53


 944              	.LVL47:
 360:User/protocol.c **** }
 945              		.loc 1 360 5 is_stmt 0 view .LVU247
 946              	.LBE95:
 947              	.LBE94:
 607:User/protocol.c **** 
 948              		.loc 1 607 9 is_stmt 1 view .LVU248
 949              	.LBB97:
 950              	.LBB96:
 361:User/protocol.c **** 
 951              		.loc 1 361 1 is_stmt 0 view .LVU249
 952 0236 FFE6     		b	.L14
 953              	.L21:
 361:User/protocol.c **** 
 954              		.loc 1 361 1 view .LVU250
 955              	.LBE96:
 956              	.LBE97:
 614:User/protocol.c ****         break;
 957              		.loc 1 614 9 is_stmt 1 view .LVU251
 958              	.LBB98:
 959              	.LBB99:
 402:User/protocol.c ****     {
 960              		.loc 1 402 8 is_stmt 0 view .LVU252
 961 0238 6388     		ldrh	r3, [r4, #2]
 962 023a 6768     		ldr	r7, [r4, #4]
 963              	.LVL48:
 402:User/protocol.c ****     {
 964              		.loc 1 402 8 view .LVU253
 965              	.LBE99:
 966              	.LBI98:
 380:User/protocol.c **** {
 967              		.loc 1 380 13 is_stmt 1 view .LVU254
 968              	.LBB100:
 384:User/protocol.c ****     {
 969              		.loc 1 384 5 view .LVU255
 389:User/protocol.c ****     {
 970              		.loc 1 389 5 view .LVU256
 402:User/protocol.c ****     {
 971              		.loc 1 402 5 view .LVU257
 402:User/protocol.c ****     {
 972              		.loc 1 402 8 is_stmt 0 view .LVU258
 973 023c 022B     		cmp	r3, #2
 974 023e 00D9     		bls	.LCB747
 975 0240 BBE0     		b	.L44	@long jump
 976              	.LCB747:
 404:User/protocol.c ****     }
 977              		.loc 1 404 9 is_stmt 1 view .LVU259
 404:User/protocol.c ****     }
 978              		.loc 1 404 30 is_stmt 0 view .LVU260
 979 0242 0022     		movs	r2, #0
 980 0244 0024     		movs	r4, #0
 981              	.LVL49:
 404:User/protocol.c ****     }
 982              		.loc 1 404 30 view .LVU261
 983 0246 524B     		ldr	r3, .L78+32
 984 0248 5A61     		str	r2, [r3, #20]
 985              	.L45:
ARM GAS  /tmp/cciZ31jV.s 			page 54


 427:User/protocol.c ****     echo.fault = motor_get_fault();
 986              		.loc 1 427 5 is_stmt 1 view .LVU262
 427:User/protocol.c ****     echo.fault = motor_get_fault();
 987              		.loc 1 427 16 is_stmt 0 view .LVU263
 988 024a 6E46     		mov	r6, sp
 989 024c 3470     		strb	r4, [r6]
 428:User/protocol.c ****     echo.target = recv->target;
 990              		.loc 1 428 5 is_stmt 1 view .LVU264
 428:User/protocol.c ****     echo.target = recv->target;
 991              		.loc 1 428 18 is_stmt 0 view .LVU265
 992 024e FFF7FEFF 		bl	motor_get_fault
 993              	.LVL50:
 428:User/protocol.c ****     echo.target = recv->target;
 994              		.loc 1 428 16 discriminator 1 view .LVU266
 995 0252 7070     		strb	r0, [r6, #1]
 429:User/protocol.c ****     echo.dc_voltage = SATURATION(B11A1_Y.Info.Udc, -32768, 32767);
 996              		.loc 1 429 5 is_stmt 1 view .LVU267
 429:User/protocol.c ****     echo.dc_voltage = SATURATION(B11A1_Y.Info.Udc, -32768, 32767);
 997              		.loc 1 429 23 is_stmt 0 view .LVU268
 998 0254 BB78     		ldrb	r3, [r7, #2]
 999 0256 7A78     		ldrb	r2, [r7, #1]
 1000 0258 1B02     		lsls	r3, r3, #8
 1001 025a 1343     		orrs	r3, r2
 429:User/protocol.c ****     echo.dc_voltage = SATURATION(B11A1_Y.Info.Udc, -32768, 32767);
 1002              		.loc 1 429 17 view .LVU269
 1003 025c 7380     		strh	r3, [r6, #2]
 430:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 1004              		.loc 1 430 5 is_stmt 1 view .LVU270
 430:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 1005              		.loc 1 430 23 is_stmt 0 view .LVU271
 1006 025e 4A4B     		ldr	r3, .L78+24
 430:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 1007              		.loc 1 430 23 discriminator 1 view .LVU272
 1008 0260 4D49     		ldr	r1, .L78+40
 1009 0262 9A69     		ldr	r2, [r3, #24]
 1010 0264 8A42     		cmp	r2, r1
 1011 0266 00DA     		bge	.L54
 1012 0268 0A00     		movs	r2, r1
 1013              	.L54:
 430:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 1014              		.loc 1 430 21 view .LVU273
 1015 026a 8021     		movs	r1, #128
 1016 026c 0902     		lsls	r1, r1, #8
 1017 026e 8A42     		cmp	r2, r1
 1018 0270 00DB     		blt	.L55
 1019 0272 4A4A     		ldr	r2, .L78+44
 1020              	.L55:
 430:User/protocol.c ****     echo.current = SATURATION(B11A1_Y.Info.Idq[1], -32768, 32767);
 1021              		.loc 1 430 21 discriminator 4 view .LVU274
 1022 0274 B280     		strh	r2, [r6, #4]
 431:User/protocol.c ****     echo.voltage = SATURATION(B11A1_Y.Info.Udq[1], -32768, 32767);
 1023              		.loc 1 431 5 is_stmt 1 view .LVU275
 431:User/protocol.c ****     echo.voltage = SATURATION(B11A1_Y.Info.Udq[1], -32768, 32767);
 1024              		.loc 1 431 20 is_stmt 0 discriminator 1 view .LVU276
 1025 0276 4849     		ldr	r1, .L78+40
 1026 0278 DA6A     		ldr	r2, [r3, #44]
 1027 027a 8A42     		cmp	r2, r1
ARM GAS  /tmp/cciZ31jV.s 			page 55


 1028 027c 00DA     		bge	.L56
 1029 027e 0A00     		movs	r2, r1
 1030              	.L56:
 431:User/protocol.c ****     echo.voltage = SATURATION(B11A1_Y.Info.Udq[1], -32768, 32767);
 1031              		.loc 1 431 18 view .LVU277
 1032 0280 8021     		movs	r1, #128
 1033 0282 0902     		lsls	r1, r1, #8
 1034 0284 8A42     		cmp	r2, r1
 1035 0286 00DB     		blt	.L57
 1036 0288 444A     		ldr	r2, .L78+44
 1037              	.L57:
 431:User/protocol.c ****     echo.voltage = SATURATION(B11A1_Y.Info.Udq[1], -32768, 32767);
 1038              		.loc 1 431 18 discriminator 4 view .LVU278
 1039 028a 7281     		strh	r2, [r6, #10]
 432:User/protocol.c ****     echo.velocity = SATURATION(B11A1_Y.Info.Velocity, -32768, 32767);
 1040              		.loc 1 432 5 is_stmt 1 view .LVU279
 432:User/protocol.c ****     echo.velocity = SATURATION(B11A1_Y.Info.Velocity, -32768, 32767);
 1041              		.loc 1 432 20 is_stmt 0 discriminator 1 view .LVU280
 1042 028c 4249     		ldr	r1, .L78+40
 1043 028e 5A6A     		ldr	r2, [r3, #36]
 1044 0290 8A42     		cmp	r2, r1
 1045 0292 00DA     		bge	.L58
 1046 0294 0A00     		movs	r2, r1
 1047              	.L58:
 432:User/protocol.c ****     echo.velocity = SATURATION(B11A1_Y.Info.Velocity, -32768, 32767);
 1048              		.loc 1 432 18 view .LVU281
 1049 0296 8021     		movs	r1, #128
 1050 0298 0902     		lsls	r1, r1, #8
 1051 029a 8A42     		cmp	r2, r1
 1052 029c 00DB     		blt	.L59
 1053 029e 3F4A     		ldr	r2, .L78+44
 1054              	.L59:
 432:User/protocol.c ****     echo.velocity = SATURATION(B11A1_Y.Info.Velocity, -32768, 32767);
 1055              		.loc 1 432 18 discriminator 4 view .LVU282
 1056 02a0 B281     		strh	r2, [r6, #12]
 433:User/protocol.c ****     echo.temp = B11A1_Y.Info.Temp;
 1057              		.loc 1 433 5 is_stmt 1 view .LVU283
 433:User/protocol.c ****     echo.temp = B11A1_Y.Info.Temp;
 1058              		.loc 1 433 21 is_stmt 0 discriminator 1 view .LVU284
 1059 02a2 3D49     		ldr	r1, .L78+40
 1060 02a4 1A6B     		ldr	r2, [r3, #48]
 1061 02a6 8A42     		cmp	r2, r1
 1062 02a8 00DA     		bge	.L60
 1063 02aa 0A00     		movs	r2, r1
 1064              	.L60:
 433:User/protocol.c ****     echo.temp = B11A1_Y.Info.Temp;
 1065              		.loc 1 433 19 view .LVU285
 1066 02ac 8021     		movs	r1, #128
 1067 02ae 0902     		lsls	r1, r1, #8
 1068 02b0 8A42     		cmp	r2, r1
 1069 02b2 00DB     		blt	.L61
 1070 02b4 394A     		ldr	r2, .L78+44
 1071              	.L61:
 434:User/protocol.c ****     // echo.temp = ADC_GetVTStemperature(INTERNALTEMPSENSOR, ADC_ReferenceVoltage_4V9)*100; // ADC_
 1072              		.loc 1 434 15 view .LVU286
 1073 02b6 9B68     		ldr	r3, [r3, #8]
 433:User/protocol.c ****     echo.temp = B11A1_Y.Info.Temp;
ARM GAS  /tmp/cciZ31jV.s 			page 56


 1074              		.loc 1 433 19 discriminator 4 view .LVU287
 1075 02b8 3281     		strh	r2, [r6, #8]
 434:User/protocol.c ****     // echo.temp = ADC_GetVTStemperature(INTERNALTEMPSENSOR, ADC_ReferenceVoltage_4V9)*100; // ADC_
 1076              		.loc 1 434 5 is_stmt 1 view .LVU288
 437:User/protocol.c **** }
 1077              		.loc 1 437 5 is_stmt 0 view .LVU289
 1078 02ba 3100     		movs	r1, r6
 1079 02bc 0E22     		movs	r2, #14
 1080 02be 2800     		movs	r0, r5
 434:User/protocol.c ****     // echo.temp = ADC_GetVTStemperature(INTERNALTEMPSENSOR, ADC_ReferenceVoltage_4V9)*100; // ADC_
 1081              		.loc 1 434 15 view .LVU290
 1082 02c0 F380     		strh	r3, [r6, #6]
 437:User/protocol.c **** }
 1083              		.loc 1 437 5 is_stmt 1 view .LVU291
 1084 02c2 FFF7FEFF 		bl	dji_echo
 1085              	.LVL51:
 437:User/protocol.c **** }
 1086              		.loc 1 437 5 is_stmt 0 view .LVU292
 1087              	.LBE100:
 1088              	.LBE98:
 615:User/protocol.c **** 
 1089              		.loc 1 615 9 is_stmt 1 view .LVU293
 1090              	.LBB104:
 1091              	.LBB101:
 438:User/protocol.c **** static void __protocol_0x21_echo(dji_t self, dji_message_t message)
 1092              		.loc 1 438 1 is_stmt 0 view .LVU294
 1093 02c6 B7E6     		b	.L14
 1094              	.LVL52:
 1095              	.L20:
 438:User/protocol.c **** static void __protocol_0x21_echo(dji_t self, dji_message_t message)
 1096              		.loc 1 438 1 view .LVU295
 1097              	.LBE101:
 1098              	.LBE104:
 618:User/protocol.c ****         break;
 1099              		.loc 1 618 9 is_stmt 1 view .LVU296
 1100 02c8 6388     		ldrh	r3, [r4, #2]
 1101              	.LBB105:
 1102              	.LBB106:
 455:User/protocol.c **** #pragma pack()
 1103              		.loc 1 455 7 is_stmt 0 view .LVU297
 1104 02ca 0D22     		movs	r2, #13
 1105 02cc 9846     		mov	r8, r3
 1106 02ce 0021     		movs	r1, #0
 1107 02d0 6846     		mov	r0, sp
 1108 02d2 6768     		ldr	r7, [r4, #4]
 1109              	.LVL53:
 455:User/protocol.c **** #pragma pack()
 1110              		.loc 1 455 7 view .LVU298
 1111              	.LBE106:
 1112              	.LBI105:
 439:User/protocol.c **** {
 1113              		.loc 1 439 13 is_stmt 1 view .LVU299
 1114              	.LBB107:
 442:User/protocol.c ****     {
 1115              		.loc 1 442 5 view .LVU300
 449:User/protocol.c ****     {
 1116              		.loc 1 449 5 view .LVU301
ARM GAS  /tmp/cciZ31jV.s 			page 57


 455:User/protocol.c **** #pragma pack()
 1117              		.loc 1 455 7 is_stmt 0 view .LVU302
 1118 02d4 FFF7FEFF 		bl	memset
 1119              	.LVL54:
 457:User/protocol.c ****     {
 1120              		.loc 1 457 5 is_stmt 1 view .LVU303
 457:User/protocol.c ****     {
 1121              		.loc 1 457 8 is_stmt 0 view .LVU304
 1122 02d8 4346     		mov	r3, r8
 455:User/protocol.c **** #pragma pack()
 1123              		.loc 1 455 7 view .LVU305
 1124 02da 6E46     		mov	r6, sp
 457:User/protocol.c ****     {
 1125              		.loc 1 457 8 view .LVU306
 1126 02dc 032B     		cmp	r3, #3
 1127 02de 2DD9     		bls	.L75
 462:User/protocol.c ****     {
 1128              		.loc 1 462 5 is_stmt 1 view .LVU307
 462:User/protocol.c ****     {
 1129              		.loc 1 462 17 is_stmt 0 view .LVU308
 1130 02e0 3C78     		ldrb	r4, [r7]
 1131              	.LVL55:
 462:User/protocol.c ****     {
 1132              		.loc 1 462 5 view .LVU309
 1133 02e2 012C     		cmp	r4, #1
 1134 02e4 00D1     		bne	.LCB891
 1135 02e6 E7E0     		b	.L63	@long jump
 1136              	.LCB891:
 1137 02e8 032C     		cmp	r4, #3
 1138 02ea 00D1     		bne	.LCB893
 1139 02ec EBE0     		b	.L64	@long jump
 1140              	.LCB893:
 1141 02ee 002C     		cmp	r4, #0
 1142 02f0 03D1     		bne	.L74
 466:User/protocol.c ****         B11A1_U.Control.ResetLPF = true;
 1143              		.loc 1 466 9 is_stmt 1 view .LVU310
 467:User/protocol.c ****         break;
 1144              		.loc 1 467 9 view .LVU311
 466:User/protocol.c ****         B11A1_U.Control.ResetLPF = true;
 1145              		.loc 1 466 33 is_stmt 0 view .LVU312
 1146 02f2 0222     		movs	r2, #2
 1147 02f4 264B     		ldr	r3, .L78+32
 1148 02f6 FF32     		adds	r2, r2, #255
 1149 02f8 1A82     		strh	r2, [r3, #16]
 1150              	.L74:
 468:User/protocol.c **** 
 1151              		.loc 1 468 9 is_stmt 1 view .LVU313
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1152              		.loc 1 489 50 is_stmt 0 view .LVU314
 1153 02fa 244B     		ldr	r3, .L78+28
 1154 02fc 5A69     		ldr	r2, [r3, #20]
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1155              		.loc 1 490 50 view .LVU315
 1156 02fe 9F69     		ldr	r7, [r3, #24]
 1157              	.LVL56:
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1158              		.loc 1 489 50 view .LVU316
ARM GAS  /tmp/cciZ31jV.s 			page 58


 1159 0300 9046     		mov	r8, r2
 1160              	.L66:
 488:User/protocol.c ****     echo.kp = (uint16_t)(Save.Info.VelocityConfig.Kp / 296068.517647058f);
 1161              		.loc 1 488 5 is_stmt 1 view .LVU317
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1162              		.loc 1 489 54 is_stmt 0 view .LVU318
 1163 0302 4046     		mov	r0, r8
 488:User/protocol.c ****     echo.kp = (uint16_t)(Save.Info.VelocityConfig.Kp / 296068.517647058f);
 1164              		.loc 1 488 16 view .LVU319
 1165 0304 3470     		strb	r4, [r6]
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1166              		.loc 1 489 5 is_stmt 1 view .LVU320
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1167              		.loc 1 489 54 is_stmt 0 view .LVU321
 1168 0306 FFF7FEFF 		bl	__aeabi_ui2f
 1169              	.LVL57:
 1170 030a 2549     		ldr	r1, .L78+48
 1171 030c FFF7FEFF 		bl	__aeabi_fmul
 1172              	.LVL58:
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1173              		.loc 1 489 15 view .LVU322
 1174 0310 FFF7FEFF 		bl	__aeabi_f2uiz
 1175              	.LVL59:
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1176              		.loc 1 489 13 view .LVU323
 1177 0314 6B46     		mov	r3, sp
 1178 0316 5A1C     		adds	r2, r3, #1
 1179 0318 83B2     		uxth	r3, r0
 1180 031a 1B0A     		lsrs	r3, r3, #8
 1181 031c 5370     		strb	r3, [r2, #1]
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1182              		.loc 1 490 5 is_stmt 1 view .LVU324
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1183              		.loc 1 489 13 is_stmt 0 view .LVU325
 1184 031e 1070     		strb	r0, [r2]
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1185              		.loc 1 490 54 view .LVU326
 1186 0320 3800     		movs	r0, r7
 1187 0322 FFF7FEFF 		bl	__aeabi_ui2f
 1188              	.LVL60:
 1189 0326 1F49     		ldr	r1, .L78+52
 1190 0328 FFF7FEFF 		bl	__aeabi_fmul
 1191              	.LVL61:
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1192              		.loc 1 490 15 view .LVU327
 1193 032c FFF7FEFF 		bl	__aeabi_f2uiz
 1194              	.LVL62:
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1195              		.loc 1 490 13 view .LVU328
 1196 0330 6B46     		mov	r3, sp
 1197 0332 DA1C     		adds	r2, r3, #3
 1198 0334 83B2     		uxth	r3, r0
 1199 0336 1B0A     		lsrs	r3, r3, #8
 1200 0338 5370     		strb	r3, [r2, #1]
 1201 033a 1070     		strb	r0, [r2]
 1202              	.L75:
 491:User/protocol.c **** }
ARM GAS  /tmp/cciZ31jV.s 			page 59


 1203              		.loc 1 491 5 is_stmt 1 view .LVU329
 1204 033c 0D22     		movs	r2, #13
 1205 033e 3100     		movs	r1, r6
 1206 0340 2800     		movs	r0, r5
 1207 0342 FFF7FEFF 		bl	dji_echo
 1208              	.LVL63:
 1209 0346 77E6     		b	.L14
 1210              	.LVL64:
 1211              	.L19:
 491:User/protocol.c **** }
 1212              		.loc 1 491 5 is_stmt 0 view .LVU330
 1213              	.LBE107:
 1214              	.LBE105:
 622:User/protocol.c ****         break;
 1215              		.loc 1 622 9 is_stmt 1 view .LVU331
 1216              	.LBB109:
 1217              	.LBI109:
 500:User/protocol.c **** {
 1218              		.loc 1 500 13 view .LVU332
 1219              	.LBB110:
 503:User/protocol.c ****     {
 1220              		.loc 1 503 5 view .LVU333
 510:User/protocol.c ****     {
 1221              		.loc 1 510 5 view .LVU334
 510:User/protocol.c ****     {
 1222              		.loc 1 510 9 is_stmt 0 view .LVU335
 1223 0348 6368     		ldr	r3, [r4, #4]
 510:User/protocol.c ****     {
 1224              		.loc 1 510 8 view .LVU336
 1225 034a C822     		movs	r2, #200
 1226 034c 1868     		ldr	r0, [r3]
 1227 034e 0023     		movs	r3, #0
 1228 0350 1C00     		movs	r4, r3
 1229              	.LVL65:
 510:User/protocol.c ****     {
 1230              		.loc 1 510 8 view .LVU337
 1231 0352 1202     		lsls	r2, r2, #8
 1232 0354 9042     		cmp	r0, r2
 1233 0356 5C41     		adcs	r4, r4, r3
 518:User/protocol.c **** 
 1234              		.loc 1 518 24 view .LVU338
 1235 0358 8022     		movs	r2, #128
 1236 035a 6946     		mov	r1, sp
 1237 035c 5242     		rsbs	r2, r2, #0
 1238 035e 4A70     		strb	r2, [r1, #1]
 520:User/protocol.c **** }
 1239              		.loc 1 520 5 view .LVU339
 1240 0360 2800     		movs	r0, r5
 1241 0362 0322     		movs	r2, #3
 1242 0364 0C70     		strb	r4, [r1]
 518:User/protocol.c **** 
 1243              		.loc 1 518 5 is_stmt 1 view .LVU340
 518:User/protocol.c **** 
 1244              		.loc 1 518 24 is_stmt 0 view .LVU341
 1245 0366 8B70     		strb	r3, [r1, #2]
 520:User/protocol.c **** }
 1246              		.loc 1 520 5 is_stmt 1 view .LVU342
ARM GAS  /tmp/cciZ31jV.s 			page 60


 1247 0368 FFF7FEFF 		bl	dji_echo
 1248              	.LVL66:
 520:User/protocol.c **** }
 1249              		.loc 1 520 5 is_stmt 0 view .LVU343
 1250              	.LBE110:
 1251              	.LBE109:
 623:User/protocol.c **** 
 1252              		.loc 1 623 9 is_stmt 1 view .LVU344
 1253              	.LBB112:
 1254              	.LBB111:
 521:User/protocol.c **** 
 1255              		.loc 1 521 1 is_stmt 0 view .LVU345
 1256 036c 64E6     		b	.L14
 1257              	.L79:
 1258 036e C046     		.align	2
 1259              	.L78:
 1260 0370 00000000 		.word	.L17
 1261 0374 00000000 		.word	reset_flag
 1262 0378 00000000 		.word	echo.0
 1263 037c 00F80008 		.word	134281216
 1264 0380 00080008 		.word	134219776
 1265 0384 00000000 		.word	g_save
 1266 0388 00000000 		.word	B11A1_Y
 1267 038c 00000000 		.word	Save
 1268 0390 00000000 		.word	B11A1_U
 1269 0394 B0F7FF1F 		.word	536868784
 1270 0398 0080FFFF 		.word	-32768
 1271 039c FF7F0000 		.word	32767
 1272 03a0 AAAA6236 		.word	912435882
 1273 03a4 AB5A5D3B 		.word	995973803
 1274              	.LVL67:
 1275              	.L18:
 521:User/protocol.c **** 
 1276              		.loc 1 521 1 view .LVU346
 1277              	.LBE111:
 1278              	.LBE112:
 626:User/protocol.c ****         break;
 1279              		.loc 1 626 9 is_stmt 1 view .LVU347
 1280              	.LBB113:
 1281              	.LBI113:
 529:User/protocol.c **** {
 1282              		.loc 1 529 13 view .LVU348
 1283              	.LBB114:
 532:User/protocol.c ****     {
 1284              		.loc 1 532 5 view .LVU349
 535:User/protocol.c **** #pragma pack()
 1285              		.loc 1 535 7 is_stmt 0 view .LVU350
 1286 03a8 6A46     		mov	r2, sp
 1287 03aa 0023     		movs	r3, #0
 538:User/protocol.c **** }
 1288              		.loc 1 538 5 view .LVU351
 1289 03ac 6946     		mov	r1, sp
 535:User/protocol.c **** #pragma pack()
 1290              		.loc 1 535 7 view .LVU352
 1291 03ae 1370     		strb	r3, [r2]
 538:User/protocol.c **** }
 1292              		.loc 1 538 5 is_stmt 1 view .LVU353
ARM GAS  /tmp/cciZ31jV.s 			page 61


 1293 03b0 2800     		movs	r0, r5
 1294 03b2 0122     		movs	r2, #1
 1295 03b4 FFF7FEFF 		bl	dji_echo
 1296              	.LVL68:
 538:User/protocol.c **** }
 1297              		.loc 1 538 5 is_stmt 0 view .LVU354
 1298              	.LBE114:
 1299              	.LBE113:
 627:User/protocol.c **** 
 1300              		.loc 1 627 9 is_stmt 1 view .LVU355
 1301              	.LBB116:
 1302              	.LBB115:
 539:User/protocol.c **** 
 1303              		.loc 1 539 1 is_stmt 0 view .LVU356
 1304 03b8 3EE6     		b	.L14
 1305              	.LVL69:
 1306              	.L44:
 539:User/protocol.c **** 
 1307              		.loc 1 539 1 view .LVU357
 1308              	.LBE115:
 1309              	.LBE116:
 1310              	.LBB117:
 1311              	.LBB102:
 408:User/protocol.c ****         switch (B11A1_U.Control.Mode)
 1312              		.loc 1 408 9 is_stmt 1 view .LVU358
 408:User/protocol.c ****         switch (B11A1_U.Control.Mode)
 1313              		.loc 1 408 36 is_stmt 0 view .LVU359
 1314 03ba 3C78     		ldrb	r4, [r7]
 1315              	.LVL70:
 408:User/protocol.c ****         switch (B11A1_U.Control.Mode)
 1316              		.loc 1 408 30 view .LVU360
 1317 03bc 7E4E     		ldr	r6, .L80
 408:User/protocol.c ****         switch (B11A1_U.Control.Mode)
 1318              		.loc 1 408 36 view .LVU361
 1319 03be 7461     		str	r4, [r6, #20]
 409:User/protocol.c ****         {
 1320              		.loc 1 409 9 is_stmt 1 view .LVU362
 1321 03c0 022C     		cmp	r4, #2
 1322 03c2 00D1     		bne	.LCB1071
 1323 03c4 D8E0     		b	.L46	@long jump
 1324              	.LCB1071:
 1325 03c6 032C     		cmp	r4, #3
 1326 03c8 00D1     		bne	.LCB1073
 1327 03ca BFE0     		b	.L47	@long jump
 1328              	.LCB1073:
 1329 03cc 012C     		cmp	r4, #1
 1330 03ce 00D0     		beq	.LCB1075
 1331 03d0 3BE7     		b	.L45	@long jump
 1332              	.LCB1075:
 414:User/protocol.c ****             break;
 1333              		.loc 1 414 13 view .LVU363
 414:User/protocol.c ****             break;
 1334              		.loc 1 414 44 is_stmt 0 view .LVU364
 1335 03d2 BB78     		ldrb	r3, [r7, #2]
 1336 03d4 7A78     		ldrb	r2, [r7, #1]
 1337 03d6 1B02     		lsls	r3, r3, #8
 1338 03d8 1343     		orrs	r3, r2
ARM GAS  /tmp/cciZ31jV.s 			page 62


 414:User/protocol.c ****             break;
 1339              		.loc 1 414 36 view .LVU365
 1340 03da 784A     		ldr	r2, .L80+4
 414:User/protocol.c ****             break;
 1341              		.loc 1 414 44 view .LVU366
 1342 03dc 1B04     		lsls	r3, r3, #16
 1343 03de 1B14     		asrs	r3, r3, #16
 414:User/protocol.c ****             break;
 1344              		.loc 1 414 36 view .LVU367
 1345 03e0 9342     		cmp	r3, r2
 1346 03e2 00DD     		ble	.LCB1086
 1347 03e4 E4E0     		b	.L71	@long jump
 1348              	.LCB1086:
 414:User/protocol.c ****             break;
 1349              		.loc 1 414 44 discriminator 1 view .LVU368
 1350 03e6 7649     		ldr	r1, .L80+8
 1351 03e8 1A1C     		adds	r2, r3, #0
 1352 03ea 8B42     		cmp	r3, r1
 1353 03ec 00DA     		bge	.L49
 1354 03ee 0A1C     		adds	r2, r1, #0
 1355              	.L49:
 414:User/protocol.c ****             break;
 1356              		.loc 1 414 44 discriminator 1 view .LVU369
 1357 03f0 12B2     		sxth	r2, r2
 414:User/protocol.c ****             break;
 1358              		.loc 1 414 89 discriminator 1 view .LVU370
 1359 03f2 7449     		ldr	r1, .L80+12
 414:User/protocol.c ****             break;
 1360              		.loc 1 414 82 discriminator 1 view .LVU371
 1361 03f4 D003     		lsls	r0, r2, #15
 414:User/protocol.c ****             break;
 1362              		.loc 1 414 89 discriminator 1 view .LVU372
 1363 03f6 FFF7FEFF 		bl	__aeabi_idiv
 1364              	.LVL71:
 414:User/protocol.c ****             break;
 1365              		.loc 1 414 36 discriminator 1 view .LVU373
 1366 03fa 00B2     		sxth	r0, r0
 414:User/protocol.c ****             break;
 1367              		.loc 1 414 36 discriminator 4 view .LVU374
 1368 03fc 7083     		strh	r0, [r6, #26]
 415:User/protocol.c ****         case CurrentMode:
 1369              		.loc 1 415 13 is_stmt 1 view .LVU375
 1370 03fe 24E7     		b	.L45
 1371              	.LVL72:
 1372              	.L33:
 415:User/protocol.c ****         case CurrentMode:
 1373              		.loc 1 415 13 is_stmt 0 view .LVU376
 1374              	.LBE102:
 1375              	.LBE117:
 1376              	.LBB118:
 1377              	.LBB56:
 100:User/protocol.c ****         memcpy(g_save.activate.sn, message->data, message->len);
 1378              		.loc 1 100 9 is_stmt 1 view .LVU377
 100:User/protocol.c ****         memcpy(g_save.activate.sn, message->data, message->len);
 1379              		.loc 1 100 14 is_stmt 0 view .LVU378
 1380 0400 0023     		movs	r3, #0
 101:User/protocol.c ****         save_write();
ARM GAS  /tmp/cciZ31jV.s 			page 63


 1381              		.loc 1 101 9 view .LVU379
 1382 0402 0E22     		movs	r2, #14
 101:User/protocol.c ****         save_write();
 1383              		.loc 1 101 43 view .LVU380
 1384 0404 6168     		ldr	r1, [r4, #4]
 100:User/protocol.c ****         memcpy(g_save.activate.sn, message->data, message->len);
 1385              		.loc 1 100 14 view .LVU381
 1386 0406 3370     		strb	r3, [r6]
 101:User/protocol.c ****         save_write();
 1387              		.loc 1 101 9 is_stmt 1 view .LVU382
 1388 0408 6F48     		ldr	r0, .L80+16
 1389 040a FFF7FEFF 		bl	memcpy
 1390              	.LVL73:
 102:User/protocol.c ****     }
 1391              		.loc 1 102 9 view .LVU383
 1392 040e FFF7FEFF 		bl	save_write
 1393              	.LVL74:
 104:User/protocol.c **** }
 1394              		.loc 1 104 5 view .LVU384
 1395 0412 0CE6     		b	.L39
 1396              	.LVL75:
 1397              	.L76:
 104:User/protocol.c **** }
 1398              		.loc 1 104 5 is_stmt 0 view .LVU385
 1399              	.LBE56:
 1400              	.LBE118:
 1401              	.LBB119:
 1402              	.LBB78:
 183:User/protocol.c ****         memcpy(&echo.year, message->data, 7);
 1403              		.loc 1 183 9 is_stmt 1 view .LVU386
 183:User/protocol.c ****         memcpy(&echo.year, message->data, 7);
 1404              		.loc 1 183 19 is_stmt 0 view .LVU387
 1405 0414 0027     		movs	r7, #0
 184:User/protocol.c ****         g_save.activate.state = false;
 1406              		.loc 1 184 9 view .LVU388
 1407 0416 6168     		ldr	r1, [r4, #4]
 1408 0418 0722     		movs	r2, #7
 183:User/protocol.c ****         memcpy(&echo.year, message->data, 7);
 1409              		.loc 1 183 19 view .LVU389
 1410 041a 3770     		strb	r7, [r6]
 184:User/protocol.c ****         g_save.activate.state = false;
 1411              		.loc 1 184 9 is_stmt 1 view .LVU390
 1412 041c 701C     		adds	r0, r6, #1
 1413 041e FFF7FEFF 		bl	memcpy
 1414              	.LVL76:
 185:User/protocol.c ****         g_save.activate.year = echo.year;
 1415              		.loc 1 185 9 view .LVU391
 185:User/protocol.c ****         g_save.activate.year = echo.year;
 1416              		.loc 1 185 31 is_stmt 0 view .LVU392
 1417 0422 694B     		ldr	r3, .L80+16
 1418 0424 9F73     		strb	r7, [r3, #14]
 186:User/protocol.c ****         g_save.activate.month = echo.month;
 1419              		.loc 1 186 9 is_stmt 1 view .LVU393
 186:User/protocol.c ****         g_save.activate.month = echo.month;
 1420              		.loc 1 186 36 is_stmt 0 view .LVU394
 1421 0426 009A     		ldr	r2, [sp]
 1422 0428 1202     		lsls	r2, r2, #8
ARM GAS  /tmp/cciZ31jV.s 			page 64


 1423 042a 120C     		lsrs	r2, r2, #16
 186:User/protocol.c ****         g_save.activate.month = echo.month;
 1424              		.loc 1 186 30 view .LVU395
 1425 042c 1A82     		strh	r2, [r3, #16]
 187:User/protocol.c ****         g_save.activate.day = echo.day;
 1426              		.loc 1 187 9 is_stmt 1 view .LVU396
 187:User/protocol.c ****         g_save.activate.day = echo.day;
 1427              		.loc 1 187 31 is_stmt 0 view .LVU397
 1428 042e F278     		ldrb	r2, [r6, #3]
 1429 0430 9A74     		strb	r2, [r3, #18]
 188:User/protocol.c ****         g_save.activate.hour = echo.hour;
 1430              		.loc 1 188 9 is_stmt 1 view .LVU398
 188:User/protocol.c ****         g_save.activate.hour = echo.hour;
 1431              		.loc 1 188 29 is_stmt 0 view .LVU399
 1432 0432 3279     		ldrb	r2, [r6, #4]
 1433 0434 DA74     		strb	r2, [r3, #19]
 189:User/protocol.c ****         g_save.activate.minute = echo.minute;
 1434              		.loc 1 189 9 is_stmt 1 view .LVU400
 189:User/protocol.c ****         g_save.activate.minute = echo.minute;
 1435              		.loc 1 189 30 is_stmt 0 view .LVU401
 1436 0436 7279     		ldrb	r2, [r6, #5]
 1437 0438 1A75     		strb	r2, [r3, #20]
 190:User/protocol.c ****         g_save.activate.second = echo.second;
 1438              		.loc 1 190 9 is_stmt 1 view .LVU402
 190:User/protocol.c ****         g_save.activate.second = echo.second;
 1439              		.loc 1 190 32 is_stmt 0 view .LVU403
 1440 043a B279     		ldrb	r2, [r6, #6]
 1441 043c 5A75     		strb	r2, [r3, #21]
 191:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 1442              		.loc 1 191 9 is_stmt 1 view .LVU404
 191:User/protocol.c ****         memcpy(echo.sn, g_save.activate.sn, sizeof(g_save.activate.sn));
 1443              		.loc 1 191 32 is_stmt 0 view .LVU405
 1444 043e F279     		ldrb	r2, [r6, #7]
 1445 0440 9A75     		strb	r2, [r3, #22]
 192:User/protocol.c ****         save_write();
 1446              		.loc 1 192 9 is_stmt 1 view .LVU406
 1447 0442 02AA     		add	r2, sp, #8
 1448 0444 13CB     		ldmia	r3!, {r0, r1, r4}
 1449 0446 13C2     		stmia	r2!, {r0, r1, r4}
 1450              	.LVL77:
 192:User/protocol.c ****         save_write();
 1451              		.loc 1 192 9 is_stmt 0 view .LVU407
 1452 0448 1B88     		ldrh	r3, [r3]
 1453 044a 1380     		strh	r3, [r2]
 193:User/protocol.c ****     }
 1454              		.loc 1 193 9 is_stmt 1 view .LVU408
 1455 044c FFF7FEFF 		bl	save_write
 1456              	.LVL78:
 1457 0450 5EE6     		b	.L36
 1458              	.LVL79:
 1459              	.L41:
 193:User/protocol.c ****     }
 1460              		.loc 1 193 9 is_stmt 0 view .LVU409
 1461              	.LBE78:
 1462              	.LBE119:
 1463              	.LBB120:
 1464              	.LBB87:
ARM GAS  /tmp/cciZ31jV.s 			page 65


 296:User/protocol.c ****     {
 1465              		.loc 1 296 10 is_stmt 1 view .LVU410
 296:User/protocol.c ****     {
 1466              		.loc 1 296 13 is_stmt 0 view .LVU411
 1467 0452 012B     		cmp	r3, #1
 1468 0454 00D0     		beq	.LCB1199
 1469 0456 EFE5     		b	.L14	@long jump
 1470              	.LCB1199:
 298:User/protocol.c ****         g_save.motor.state = false;
 1471              		.loc 1 298 9 is_stmt 1 view .LVU412
 298:User/protocol.c ****         g_save.motor.state = false;
 1472              		.loc 1 298 19 is_stmt 0 view .LVU413
 1473 0458 0022     		movs	r2, #0
 1474 045a 5C4B     		ldr	r3, .L80+20
 1475 045c 1A70     		strb	r2, [r3]
 299:User/protocol.c ****         echo.state = g_save.motor.state;
 1476              		.loc 1 299 9 is_stmt 1 view .LVU414
 299:User/protocol.c ****         echo.state = g_save.motor.state;
 1477              		.loc 1 299 28 is_stmt 0 view .LVU415
 1478 045e 5A4B     		ldr	r3, .L80+16
 301:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 1479              		.loc 1 301 25 view .LVU416
 1480 0460 997E     		ldrb	r1, [r3, #26]
 299:User/protocol.c ****         echo.state = g_save.motor.state;
 1481              		.loc 1 299 28 view .LVU417
 1482 0462 1A76     		strb	r2, [r3, #24]
 300:User/protocol.c ****         echo.hall_a_max = g_save.motor.hall_a_max;
 1483              		.loc 1 300 9 is_stmt 1 view .LVU418
 301:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 1484              		.loc 1 301 9 view .LVU419
 301:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 1485              		.loc 1 301 25 is_stmt 0 view .LVU420
 1486 0464 7170     		strb	r1, [r6, #1]
 1487 0466 D97E     		ldrb	r1, [r3, #27]
 305:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 1488              		.loc 1 305 25 view .LVU421
 1489 0468 DA8C     		ldrh	r2, [r3, #38]
 301:User/protocol.c ****         echo.hall_a_min = g_save.motor.hall_a_min;
 1490              		.loc 1 301 25 view .LVU422
 1491 046a B170     		strb	r1, [r6, #2]
 302:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 1492              		.loc 1 302 9 is_stmt 1 view .LVU423
 302:User/protocol.c ****         echo.hall_b_max = g_save.motor.hall_b_max;
 1493              		.loc 1 302 25 is_stmt 0 view .LVU424
 1494 046c 997F     		ldrb	r1, [r3, #30]
 1495 046e F170     		strb	r1, [r6, #3]
 1496 0470 D97F     		ldrb	r1, [r3, #31]
 1497 0472 3171     		strb	r1, [r6, #4]
 303:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 1498              		.loc 1 303 9 is_stmt 1 view .LVU425
 303:User/protocol.c ****         echo.hall_b_min = g_save.motor.hall_b_min;
 1499              		.loc 1 303 25 is_stmt 0 view .LVU426
 1500 0474 197F     		ldrb	r1, [r3, #28]
 1501 0476 7171     		strb	r1, [r6, #5]
 1502 0478 597F     		ldrb	r1, [r3, #29]
 1503 047a B171     		strb	r1, [r6, #6]
 304:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
ARM GAS  /tmp/cciZ31jV.s 			page 66


 1504              		.loc 1 304 9 is_stmt 1 view .LVU427
 304:User/protocol.c ****         echo.angle_bias = g_save.motor.angle_offset >> 16;
 1505              		.loc 1 304 25 is_stmt 0 view .LVU428
 1506 047c 2021     		movs	r1, #32
 1507 047e 595C     		ldrb	r1, [r3, r1]
 1508 0480 F171     		strb	r1, [r6, #7]
 1509 0482 2121     		movs	r1, #33
 1510 0484 595C     		ldrb	r1, [r3, r1]
 1511 0486 3172     		strb	r1, [r6, #8]
 305:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 1512              		.loc 1 305 9 is_stmt 1 view .LVU429
 305:User/protocol.c ****         echo.current_a_bias = g_save.motor.current_a_adc_zero;
 1513              		.loc 1 305 25 is_stmt 0 view .LVU430
 1514 0488 0921     		movs	r1, #9
 1515 048a 6944     		add	r1, r1, sp
 1516 048c 0A70     		strb	r2, [r1]
 1517 048e 120A     		lsrs	r2, r2, #8
 1518 0490 4A70     		strb	r2, [r1, #1]
 306:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 1519              		.loc 1 306 9 is_stmt 1 view .LVU431
 306:User/protocol.c ****         echo.current_b_bias = g_save.motor.current_b_adc_zero;
 1520              		.loc 1 306 29 is_stmt 0 view .LVU432
 1521 0492 3021     		movs	r1, #48
 1522 0494 0B22     		movs	r2, #11
 1523 0496 595C     		ldrb	r1, [r3, r1]
 1524 0498 6A44     		add	r2, r2, sp
 1525 049a 1170     		strb	r1, [r2]
 1526 049c 3121     		movs	r1, #49
 1527 049e 595C     		ldrb	r1, [r3, r1]
 1528 04a0 5170     		strb	r1, [r2, #1]
 307:User/protocol.c ****         save_write();
 1529              		.loc 1 307 9 is_stmt 1 view .LVU433
 307:User/protocol.c ****         save_write();
 1530              		.loc 1 307 29 is_stmt 0 view .LVU434
 1531 04a2 3221     		movs	r1, #50
 1532 04a4 0D22     		movs	r2, #13
 1533 04a6 595C     		ldrb	r1, [r3, r1]
 1534 04a8 6A44     		add	r2, r2, sp
 1535 04aa 1170     		strb	r1, [r2]
 1536 04ac 3321     		movs	r1, #51
 1537 04ae 5B5C     		ldrb	r3, [r3, r1]
 1538 04b0 5370     		strb	r3, [r2, #1]
 308:User/protocol.c ****     }
 1539              		.loc 1 308 9 is_stmt 1 view .LVU435
 1540 04b2 FFF7FEFF 		bl	save_write
 1541              	.LVL80:
 1542 04b6 92E6     		b	.L42
 1543              	.LVL81:
 1544              	.L63:
 308:User/protocol.c ****     }
 1545              		.loc 1 308 9 is_stmt 0 view .LVU436
 1546              	.LBE87:
 1547              	.LBE120:
 1548              	.LBB121:
 1549              	.LBB108:
 471:User/protocol.c ****         break;
 1550              		.loc 1 471 9 is_stmt 1 view .LVU437
ARM GAS  /tmp/cciZ31jV.s 			page 67


 471:User/protocol.c ****         break;
 1551              		.loc 1 471 33 is_stmt 0 view .LVU438
 1552 04b8 3F4B     		ldr	r3, .L80
 1553 04ba 1C74     		strb	r4, [r3, #16]
 472:User/protocol.c **** 
 1554              		.loc 1 472 9 is_stmt 1 view .LVU439
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1555              		.loc 1 489 50 is_stmt 0 view .LVU440
 1556 04bc 434B     		ldr	r3, .L80+20
 1557 04be 5A69     		ldr	r2, [r3, #20]
 490:User/protocol.c ****     dji_echo(self, &echo, sizeof(echo));
 1558              		.loc 1 490 50 view .LVU441
 1559 04c0 9F69     		ldr	r7, [r3, #24]
 1560              	.LVL82:
 489:User/protocol.c ****     echo.ki = (uint16_t)(Save.Info.VelocityConfig.Ki / 296.068517647058f);
 1561              		.loc 1 489 50 view .LVU442
 1562 04c2 9046     		mov	r8, r2
 472:User/protocol.c **** 
 1563              		.loc 1 472 9 view .LVU443
 1564 04c4 1DE7     		b	.L66
 1565              	.LVL83:
 1566              	.L64:
 480:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 1567              		.loc 1 480 9 is_stmt 1 view .LVU444
 480:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 1568              		.loc 1 480 39 is_stmt 0 view .LVU445
 1569 04c6 B878     		ldrb	r0, [r7, #2]
 1570 04c8 7B78     		ldrb	r3, [r7, #1]
 1571 04ca 0002     		lsls	r0, r0, #8
 1572 04cc 1843     		orrs	r0, r3
 1573 04ce FFF7FEFF 		bl	__aeabi_i2f
 1574              	.LVL84:
 1575 04d2 3F49     		ldr	r1, .L80+24
 1576 04d4 FFF7FEFF 		bl	__aeabi_fmul
 1577              	.LVL85:
 1578 04d8 0021     		movs	r1, #0
 1579 04da 8046     		mov	r8, r0
 1580 04dc FFF7FEFF 		bl	__aeabi_fcmpge
 1581              	.LVL86:
 1582 04e0 0028     		cmp	r0, #0
 1583 04e2 01D1     		bne	.L67
 1584 04e4 0023     		movs	r3, #0
 1585 04e6 9846     		mov	r8, r3
 1586              	.L67:
 480:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 1587              		.loc 1 480 39 view .LVU446
 1588 04e8 4046     		mov	r0, r8
 1589 04ea 3A49     		ldr	r1, .L80+28
 1590 04ec FFF7FEFF 		bl	__aeabi_fcmple
 1591              	.LVL87:
 1592 04f0 0028     		cmp	r0, #0
 1593 04f2 01D1     		bne	.L68
 1594 04f4 374B     		ldr	r3, .L80+28
 1595 04f6 9846     		mov	r8, r3
 1596              	.L68:
 480:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 1597              		.loc 1 480 37 view .LVU447
ARM GAS  /tmp/cciZ31jV.s 			page 68


 1598 04f8 4046     		mov	r0, r8
 1599 04fa FFF7FEFF 		bl	__aeabi_f2uiz
 1600              	.LVL88:
 1601 04fe 334B     		ldr	r3, .L80+20
 1602 0500 8046     		mov	r8, r0
 1603 0502 5861     		str	r0, [r3, #20]
 481:User/protocol.c ****         break;
 1604              		.loc 1 481 9 is_stmt 1 view .LVU448
 481:User/protocol.c ****         break;
 1605              		.loc 1 481 39 is_stmt 0 view .LVU449
 1606 0504 3879     		ldrb	r0, [r7, #4]
 480:User/protocol.c ****         Save.Info.VelocityConfig.Ki = SATURATION((recv->ki * 29.6068517647058f), 0, FLOAT_TO_Q(10.0
 1607              		.loc 1 480 37 view .LVU450
 1608 0506 9946     		mov	r9, r3
 481:User/protocol.c ****         break;
 1609              		.loc 1 481 39 view .LVU451
 1610 0508 FB78     		ldrb	r3, [r7, #3]
 1611 050a 0002     		lsls	r0, r0, #8
 1612 050c 1843     		orrs	r0, r3
 1613 050e FFF7FEFF 		bl	__aeabi_i2f
 1614              	.LVL89:
 1615 0512 3149     		ldr	r1, .L80+32
 1616 0514 FFF7FEFF 		bl	__aeabi_fmul
 1617              	.LVL90:
 1618 0518 0021     		movs	r1, #0
 1619 051a 071C     		adds	r7, r0, #0
 1620              	.LVL91:
 481:User/protocol.c ****         break;
 1621              		.loc 1 481 39 view .LVU452
 1622 051c FFF7FEFF 		bl	__aeabi_fcmpge
 1623              	.LVL92:
 1624 0520 0028     		cmp	r0, #0
 1625 0522 00D1     		bne	.L69
 1626 0524 0027     		movs	r7, #0
 1627              	.L69:
 1628 0526 2D49     		ldr	r1, .L80+36
 1629 0528 381C     		adds	r0, r7, #0
 1630 052a FFF7FEFF 		bl	__aeabi_fcmple
 1631              	.LVL93:
 1632 052e 0028     		cmp	r0, #0
 1633 0530 00D1     		bne	.L70
 1634 0532 2A4F     		ldr	r7, .L80+36
 1635              	.L70:
 481:User/protocol.c ****         break;
 1636              		.loc 1 481 37 view .LVU453
 1637 0534 381C     		adds	r0, r7, #0
 1638 0536 FFF7FEFF 		bl	__aeabi_f2uiz
 1639              	.LVL94:
 1640 053a 4B46     		mov	r3, r9
 1641 053c 0700     		movs	r7, r0
 1642 053e 9861     		str	r0, [r3, #24]
 482:User/protocol.c **** 
 1643              		.loc 1 482 9 is_stmt 1 view .LVU454
 1644 0540 DFE6     		b	.L66
 1645              	.LVL95:
 1646              	.L77:
 482:User/protocol.c **** 
ARM GAS  /tmp/cciZ31jV.s 			page 69


 1647              		.loc 1 482 9 is_stmt 0 view .LVU455
 1648              	.LBE108:
 1649              	.LBE121:
 1650              	.LBB122:
 1651              	.LBB60:
 243:User/protocol.c ****     }
 1652              		.loc 1 243 9 is_stmt 1 view .LVU456
 243:User/protocol.c ****     }
 1653              		.loc 1 243 14 is_stmt 0 view .LVU457
 1654 0542 6E46     		mov	r6, sp
 243:User/protocol.c ****     }
 1655              		.loc 1 243 28 view .LVU458
 1656 0544 264B     		ldr	r3, .L80+40
 243:User/protocol.c ****     }
 1657              		.loc 1 243 14 view .LVU459
 1658 0546 1B7B     		ldrb	r3, [r3, #12]
 1659 0548 3370     		strb	r3, [r6]
 1660 054a 70E5     		b	.L39
 1661              	.LVL96:
 1662              	.L47:
 243:User/protocol.c ****     }
 1663              		.loc 1 243 14 view .LVU460
 1664              	.LBE60:
 1665              	.LBE122:
 1666              	.LBB123:
 1667              	.LBB103:
 420:User/protocol.c ****             break;
 1668              		.loc 1 420 13 is_stmt 1 view .LVU461
 420:User/protocol.c ****             break;
 1669              		.loc 1 420 46 is_stmt 0 view .LVU462
 1670 054c BB78     		ldrb	r3, [r7, #2]
 1671 054e 7A78     		ldrb	r2, [r7, #1]
 1672 0550 1B02     		lsls	r3, r3, #8
 1673 0552 1343     		orrs	r3, r2
 420:User/protocol.c ****             break;
 1674              		.loc 1 420 38 view .LVU463
 1675 0554 234A     		ldr	r2, .L80+44
 420:User/protocol.c ****             break;
 1676              		.loc 1 420 46 view .LVU464
 1677 0556 1B04     		lsls	r3, r3, #16
 1678 0558 1B14     		asrs	r3, r3, #16
 420:User/protocol.c ****             break;
 1679              		.loc 1 420 38 view .LVU465
 1680 055a 9342     		cmp	r3, r2
 1681 055c 25DC     		bgt	.L73
 420:User/protocol.c ****             break;
 1682              		.loc 1 420 46 discriminator 1 view .LVU466
 1683 055e 2249     		ldr	r1, .L80+48
 1684 0560 1A1C     		adds	r2, r3, #0
 1685 0562 8B42     		cmp	r3, r1
 1686 0564 00DA     		bge	.L53
 1687 0566 0A1C     		adds	r2, r1, #0
 1688              	.L53:
 420:User/protocol.c ****             break;
 1689              		.loc 1 420 46 discriminator 1 view .LVU467
 1690 0568 12B2     		sxth	r2, r2
 420:User/protocol.c ****             break;
ARM GAS  /tmp/cciZ31jV.s 			page 70


 1691              		.loc 1 420 93 discriminator 1 view .LVU468
 1692 056a 2049     		ldr	r1, .L80+52
 420:User/protocol.c ****             break;
 1693              		.loc 1 420 86 discriminator 1 view .LVU469
 1694 056c D003     		lsls	r0, r2, #15
 420:User/protocol.c ****             break;
 1695              		.loc 1 420 93 discriminator 1 view .LVU470
 1696 056e FFF7FEFF 		bl	__aeabi_idiv
 1697              	.LVL97:
 420:User/protocol.c ****             break;
 1698              		.loc 1 420 38 discriminator 1 view .LVU471
 1699 0572 00B2     		sxth	r0, r0
 420:User/protocol.c ****             break;
 1700              		.loc 1 420 38 discriminator 4 view .LVU472
 1701 0574 3084     		strh	r0, [r6, #32]
 421:User/protocol.c ****         case PositionMode:
 1702              		.loc 1 421 13 is_stmt 1 view .LVU473
 1703 0576 68E6     		b	.L45
 1704              	.L46:
 417:User/protocol.c ****             break;
 1705              		.loc 1 417 13 view .LVU474
 417:User/protocol.c ****             break;
 1706              		.loc 1 417 44 is_stmt 0 view .LVU475
 1707 0578 BB78     		ldrb	r3, [r7, #2]
 1708 057a 7A78     		ldrb	r2, [r7, #1]
 1709 057c 1B02     		lsls	r3, r3, #8
 1710 057e 1343     		orrs	r3, r2
 417:User/protocol.c ****             break;
 1711              		.loc 1 417 36 view .LVU476
 1712 0580 1B4A     		ldr	r2, .L80+56
 417:User/protocol.c ****             break;
 1713              		.loc 1 417 44 view .LVU477
 1714 0582 1B04     		lsls	r3, r3, #16
 1715 0584 1B14     		asrs	r3, r3, #16
 417:User/protocol.c ****             break;
 1716              		.loc 1 417 36 view .LVU478
 1717 0586 9342     		cmp	r3, r2
 1718 0588 0CDC     		bgt	.L72
 417:User/protocol.c ****             break;
 1719              		.loc 1 417 44 discriminator 1 view .LVU479
 1720 058a 1A49     		ldr	r1, .L80+60
 1721 058c 1A1C     		adds	r2, r3, #0
 1722 058e 8B42     		cmp	r3, r1
 1723 0590 00DA     		bge	.L51
 1724 0592 0A1C     		adds	r2, r1, #0
 1725              	.L51:
 417:User/protocol.c ****             break;
 1726              		.loc 1 417 44 discriminator 1 view .LVU480
 1727 0594 12B2     		sxth	r2, r2
 417:User/protocol.c ****             break;
 1728              		.loc 1 417 89 discriminator 1 view .LVU481
 1729 0596 1849     		ldr	r1, .L80+64
 417:User/protocol.c ****             break;
 1730              		.loc 1 417 82 discriminator 1 view .LVU482
 1731 0598 D003     		lsls	r0, r2, #15
 417:User/protocol.c ****             break;
 1732              		.loc 1 417 89 discriminator 1 view .LVU483
ARM GAS  /tmp/cciZ31jV.s 			page 71


 1733 059a FFF7FEFF 		bl	__aeabi_idiv
 1734              	.LVL98:
 417:User/protocol.c ****             break;
 1735              		.loc 1 417 36 discriminator 1 view .LVU484
 1736 059e 00B2     		sxth	r0, r0
 417:User/protocol.c ****             break;
 1737              		.loc 1 417 36 discriminator 4 view .LVU485
 1738 05a0 F083     		strh	r0, [r6, #30]
 418:User/protocol.c ****         case VelocityMode:
 1739              		.loc 1 418 13 is_stmt 1 view .LVU486
 1740 05a2 52E6     		b	.L45
 1741              	.L72:
 417:User/protocol.c ****             break;
 1742              		.loc 1 417 36 is_stmt 0 discriminator 2 view .LVU487
 1743 05a4 1548     		ldr	r0, .L80+68
 417:User/protocol.c ****             break;
 1744              		.loc 1 417 36 discriminator 4 view .LVU488
 1745 05a6 F083     		strh	r0, [r6, #30]
 418:User/protocol.c ****         case VelocityMode:
 1746              		.loc 1 418 13 is_stmt 1 view .LVU489
 1747 05a8 4FE6     		b	.L45
 1748              	.L73:
 420:User/protocol.c ****             break;
 1749              		.loc 1 420 38 is_stmt 0 discriminator 2 view .LVU490
 1750 05aa 1548     		ldr	r0, .L80+72
 420:User/protocol.c ****             break;
 1751              		.loc 1 420 38 discriminator 4 view .LVU491
 1752 05ac 3084     		strh	r0, [r6, #32]
 421:User/protocol.c ****         case PositionMode:
 1753              		.loc 1 421 13 is_stmt 1 view .LVU492
 1754 05ae 4CE6     		b	.L45
 1755              	.L71:
 414:User/protocol.c ****             break;
 1756              		.loc 1 414 36 is_stmt 0 discriminator 2 view .LVU493
 1757 05b0 1448     		ldr	r0, .L80+76
 414:User/protocol.c ****             break;
 1758              		.loc 1 414 36 discriminator 4 view .LVU494
 1759 05b2 7083     		strh	r0, [r6, #26]
 415:User/protocol.c ****         case CurrentMode:
 1760              		.loc 1 415 13 is_stmt 1 view .LVU495
 1761 05b4 49E6     		b	.L45
 1762              	.L81:
 1763 05b6 C046     		.align	2
 1764              	.L80:
 1765 05b8 00000000 		.word	B11A1_U
 1766 05bc 26230000 		.word	8998
 1767 05c0 D8DCFFFF 		.word	-9000
 1768 05c4 28230000 		.word	9000
 1769 05c8 00000000 		.word	g_save
 1770 05cc 00000000 		.word	Save
 1771 05d0 B44DE746 		.word	1189563828
 1772 05d4 0000A04D 		.word	1302331392
 1773 05d8 D5DAEC41 		.word	1106041557
 1774 05dc 0000204D 		.word	1293942784
 1775 05e0 00000000 		.word	B11A1_Y
 1776 05e4 2E750000 		.word	29998
 1777 05e8 D08AFFFF 		.word	-30000
ARM GAS  /tmp/cciZ31jV.s 			page 72


 1778 05ec 30750000 		.word	30000
 1779 05f0 92110000 		.word	4498
 1780 05f4 6CEEFFFF 		.word	-4500
 1781 05f8 94110000 		.word	4500
 1782 05fc F87F0000 		.word	32760
 1783 0600 FE7F0000 		.word	32766
 1784 0604 FC7F0000 		.word	32764
 1785              	.LBE103:
 1786              	.LBE123:
 1787              		.cfi_endproc
 1788              	.LFE62:
 1790              		.section	.text.protocol_init,"ax",%progbits
 1791              		.align	1
 1792              		.p2align 2,,3
 1793              		.global	protocol_init
 1794              		.syntax unified
 1795              		.code	16
 1796              		.thumb_func
 1798              	protocol_init:
 1799              	.LFB64:
 668:User/protocol.c **** 
 669:User/protocol.c **** /**
 670:User/protocol.c ****  * @brief 初始化DJI通信模块
 671:User/protocol.c ****  * @note 配置DJI设备参数，注册回调函数和周期任务
 672:User/protocol.c ****  */
 673:User/protocol.c **** void protocol_init(void)
 674:User/protocol.c **** {
 1800              		.loc 1 674 1 view -0
 1801              		.cfi_startproc
 1802              		@ args = 0, pretend = 0, frame = 0
 1803              		@ frame_needed = 0, uses_anonymous_args = 0
 675:User/protocol.c ****     dji_init(&g_dji_handle, 1); // 初始化DJI设备，类型为2，ID为1
 1804              		.loc 1 675 5 view .LVU497
 674:User/protocol.c ****     dji_init(&g_dji_handle, 1); // 初始化DJI设备，类型为2，ID为1
 1805              		.loc 1 674 1 is_stmt 0 view .LVU498
 1806 0000 10B5     		push	{r4, lr}
 1807              	.LCFI5:
 1808              		.cfi_def_cfa_offset 8
 1809              		.cfi_offset 4, -8
 1810              		.cfi_offset 14, -4
 1811              		.loc 1 675 5 view .LVU499
 1812 0002 094C     		ldr	r4, .L83
 1813 0004 0121     		movs	r1, #1
 676:User/protocol.c **** #if !GPIO_TEST
 677:User/protocol.c ****     dji_set_on_send(&g_dji_handle, uart_send); // 设置发送回调函数为uart_send
 678:User/protocol.c **** #endif
 679:User/protocol.c ****     dji_set_on_message(&g_dji_handle, __protocol_on_message);
 680:User/protocol.c **** 
 681:User/protocol.c ****     task_cycle_register(&g_task_handle, __protocol_on_step, 1);
 682:User/protocol.c **** }
 1814              		.loc 1 682 1 view .LVU500
 1815              		@ sp needed
 675:User/protocol.c **** #if !GPIO_TEST
 1816              		.loc 1 675 5 view .LVU501
 1817 0006 2000     		movs	r0, r4
 1818 0008 FFF7FEFF 		bl	dji_init
 1819              	.LVL99:
ARM GAS  /tmp/cciZ31jV.s 			page 73


 677:User/protocol.c **** #endif
 1820              		.loc 1 677 5 is_stmt 1 view .LVU502
 1821 000c 2000     		movs	r0, r4
 1822 000e 0749     		ldr	r1, .L83+4
 1823 0010 FFF7FEFF 		bl	dji_set_on_send
 1824              	.LVL100:
 679:User/protocol.c **** 
 1825              		.loc 1 679 5 view .LVU503
 1826 0014 2000     		movs	r0, r4
 1827 0016 0649     		ldr	r1, .L83+8
 1828 0018 FFF7FEFF 		bl	dji_set_on_message
 1829              	.LVL101:
 681:User/protocol.c **** }
 1830              		.loc 1 681 5 view .LVU504
 1831 001c 0122     		movs	r2, #1
 1832 001e 0549     		ldr	r1, .L83+12
 1833 0020 0548     		ldr	r0, .L83+16
 1834 0022 FFF7FEFF 		bl	task_cycle_register
 1835              	.LVL102:
 1836              		.loc 1 682 1 is_stmt 0 view .LVU505
 1837 0026 10BD     		pop	{r4, pc}
 1838              	.L84:
 1839              		.align	2
 1840              	.L83:
 1841 0028 00000000 		.word	g_dji_handle
 1842 002c 00000000 		.word	uart_send
 1843 0030 00000000 		.word	__protocol_on_message
 1844 0034 00000000 		.word	__protocol_on_step
 1845 0038 00000000 		.word	g_task_handle
 1846              		.cfi_endproc
 1847              	.LFE64:
 1849              		.section	.data.echo.0,"aw"
 1850              		.align	2
 1853              	echo.0:
 1854 0000 00       		.byte	0
 1855 0001 00000000 		.space	18
 1855      00000000 
 1855      00000000 
 1855      00000000 
 1855      0000
 1856 0013 000D     		.2byte	3328
 1857              		.section	.bss.count.1,"aw",%nobits
 1858              		.align	2
 1861              	count.1:
 1862 0000 00000000 		.space	4
 1863              		.section	.bss.reset_flag,"aw",%nobits
 1866              	reset_flag:
 1867 0000 00       		.space	1
 1868              		.text
 1869              	.Letext0:
 1870              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 1871              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 1872              		.file 6 "Component/dji/dji_define.h"
 1873              		.file 7 "Component/task/task_define.h"
 1874              		.file 8 "User/global.h"
 1875              		.file 9 "Component/chart/B11A1.h"
 1876              		.file 10 "Library/inc/lcm32f06x.h"
ARM GAS  /tmp/cciZ31jV.s 			page 74


 1877              		.file 11 "User/motor.h"
 1878              		.file 12 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/string.h"
 1879              		.file 13 "Component/dji/dji.h"
 1880              		.file 14 "Hardware/uart.h"
 1881              		.file 15 "Component/task/task.h"
 1882              		.file 16 "<built-in>"
ARM GAS  /tmp/cciZ31jV.s 			page 75


DEFINED SYMBOLS
                            *ABS*:00000000 protocol.c
     /tmp/cciZ31jV.s:17     .rodata.__protocol_on_step.str1.4:00000000 $d
     /tmp/cciZ31jV.s:21     .text.__protocol_on_step:00000000 $t
     /tmp/cciZ31jV.s:27     .text.__protocol_on_step:00000000 __protocol_on_step
     /tmp/cciZ31jV.s:172    .text.__protocol_on_step:0000006c $d
     /tmp/cciZ31jV.s:1866   .bss.reset_flag:00000000 reset_flag
     /tmp/cciZ31jV.s:1861   .bss.count.1:00000000 count.1
     /tmp/cciZ31jV.s:185    .text.__protocol_on_message:00000000 $t
     /tmp/cciZ31jV.s:191    .text.__protocol_on_message:00000000 __protocol_on_message
     /tmp/cciZ31jV.s:232    .rodata.__protocol_on_message:00000000 $d
     /tmp/cciZ31jV.s:1260   .text.__protocol_on_message:00000370 $d
     /tmp/cciZ31jV.s:1853   .data.echo.0:00000000 echo.0
     /tmp/cciZ31jV.s:1286   .text.__protocol_on_message:000003a8 $t
     /tmp/cciZ31jV.s:1765   .text.__protocol_on_message:000005b8 $d
     /tmp/cciZ31jV.s:1791   .text.protocol_init:00000000 $t
     /tmp/cciZ31jV.s:1798   .text.protocol_init:00000000 protocol_init
     /tmp/cciZ31jV.s:1841   .text.protocol_init:00000028 $d
     /tmp/cciZ31jV.s:1850   .data.echo.0:00000000 $d
     /tmp/cciZ31jV.s:1858   .bss.count.1:00000000 $d
     /tmp/cciZ31jV.s:1867   .bss.reset_flag:00000000 $d

UNDEFINED SYMBOLS
uart_recv
dji_on_recv
uart_available
uart_send_end
uart_printf
dji_on_step
g_dji_handle
B11A1_DW
CommandUpdate
dji_echo
save_flag
memcpy
memset
save_write
motor_get_fault
motor_reset_fault
__aeabi_ui2f
__aeabi_fmul
__aeabi_f2uiz
g_save
B11A1_Y
Save
B11A1_U
__aeabi_idiv
__aeabi_i2f
__aeabi_fcmpge
__aeabi_fcmple
dji_init
dji_set_on_send
dji_set_on_message
task_cycle_register
uart_send
g_task_handle
