ARM GAS  /tmp/cctKAvId.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_exti.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Library/src/lcm32f06x_exti.c"
  16              		.section	.text.EXTI_DeInit,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	EXTI_DeInit
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	EXTI_DeInit:
  25              	.LFB45:
   1:Library/src/lcm32f06x_exti.c **** /**
   2:Library/src/lcm32f06x_exti.c ****   ******************************************************************************
   3:Library/src/lcm32f06x_exti.c ****   * @file    lcm32f06x_exti.c
   4:Library/src/lcm32f06x_exti.c ****   * @author  System R&D Team
   5:Library/src/lcm32f06x_exti.c ****   * @version V2.0.2
   6:Library/src/lcm32f06x_exti.c ****   * @date    10-April-2025
   7:Library/src/lcm32f06x_exti.c ****   * @brief   This file provides all the EXTI firmware functions.
   8:Library/src/lcm32f06x_exti.c ****   ******************************************************************************
   9:Library/src/lcm32f06x_exti.c ****   * @attention
  10:Library/src/lcm32f06x_exti.c ****   *
  11:Library/src/lcm32f06x_exti.c ****   * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  12:Library/src/lcm32f06x_exti.c ****   * All rights reserved.
  13:Library/src/lcm32f06x_exti.c ****   *
  14:Library/src/lcm32f06x_exti.c ****   * This software is licensed under terms that can be found in the LICENSE file
  15:Library/src/lcm32f06x_exti.c ****   * in the root directory of this software component.
  16:Library/src/lcm32f06x_exti.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  17:Library/src/lcm32f06x_exti.c ****   *
  18:Library/src/lcm32f06x_exti.c ****   ******************************************************************************
  19:Library/src/lcm32f06x_exti.c ****   */
  20:Library/src/lcm32f06x_exti.c **** /* Includes ------------------------------------------------------------------*/
  21:Library/src/lcm32f06x_exti.c **** #include "lcm32f06x_exti.h"
  22:Library/src/lcm32f06x_exti.c **** 
  23:Library/src/lcm32f06x_exti.c **** 
  24:Library/src/lcm32f06x_exti.c **** #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
  25:Library/src/lcm32f06x_exti.c **** 
  26:Library/src/lcm32f06x_exti.c **** /**
  27:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_DeInit
  28:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Deinitializes EXTI peripheral registers to their default reset values.
  29:Library/src/lcm32f06x_exti.c ****   *         CN: 将 EXTI 外设寄存器初始化为其默认重置值
  30:Library/src/lcm32f06x_exti.c ****   * @param  None
  31:Library/src/lcm32f06x_exti.c ****   * @retval None
  32:Library/src/lcm32f06x_exti.c ****   */
  33:Library/src/lcm32f06x_exti.c **** void EXTI_DeInit(void)
ARM GAS  /tmp/cctKAvId.s 			page 2


  34:Library/src/lcm32f06x_exti.c **** {
  26              		.loc 1 34 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 0
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  30              		@ link register save eliminated.
  35:Library/src/lcm32f06x_exti.c ****   EXTI->IMR = 0x00000000;
  31              		.loc 1 35 3 view .LVU1
  32              		.loc 1 35 13 is_stmt 0 view .LVU2
  33 0000 0022     		movs	r2, #0
  36:Library/src/lcm32f06x_exti.c ****   EXTI->EMR = 0x00000000;
  37:Library/src/lcm32f06x_exti.c ****   EXTI->RTSR = 0x00000000;
  38:Library/src/lcm32f06x_exti.c ****   EXTI->FTSR = 0x00000000;
  39:Library/src/lcm32f06x_exti.c ****   EXTI->PR = 0x01FFFFFF;
  40:Library/src/lcm32f06x_exti.c **** }
  34              		.loc 1 40 1 view .LVU3
  35              		@ sp needed
  35:Library/src/lcm32f06x_exti.c ****   EXTI->IMR = 0x00000000;
  36              		.loc 1 35 13 view .LVU4
  37 0002 044B     		ldr	r3, .L3
  38 0004 1A60     		str	r2, [r3]
  36:Library/src/lcm32f06x_exti.c ****   EXTI->EMR = 0x00000000;
  39              		.loc 1 36 3 is_stmt 1 view .LVU5
  36:Library/src/lcm32f06x_exti.c ****   EXTI->EMR = 0x00000000;
  40              		.loc 1 36 13 is_stmt 0 view .LVU6
  41 0006 5A60     		str	r2, [r3, #4]
  37:Library/src/lcm32f06x_exti.c ****   EXTI->FTSR = 0x00000000;
  42              		.loc 1 37 3 is_stmt 1 view .LVU7
  37:Library/src/lcm32f06x_exti.c ****   EXTI->FTSR = 0x00000000;
  43              		.loc 1 37 14 is_stmt 0 view .LVU8
  44 0008 9A60     		str	r2, [r3, #8]
  38:Library/src/lcm32f06x_exti.c ****   EXTI->PR = 0x01FFFFFF;
  45              		.loc 1 38 3 is_stmt 1 view .LVU9
  38:Library/src/lcm32f06x_exti.c ****   EXTI->PR = 0x01FFFFFF;
  46              		.loc 1 38 14 is_stmt 0 view .LVU10
  47 000a DA60     		str	r2, [r3, #12]
  39:Library/src/lcm32f06x_exti.c **** }
  48              		.loc 1 39 3 is_stmt 1 view .LVU11
  39:Library/src/lcm32f06x_exti.c **** }
  49              		.loc 1 39 12 is_stmt 0 view .LVU12
  50 000c 024A     		ldr	r2, .L3+4
  51 000e 5A61     		str	r2, [r3, #20]
  52              		.loc 1 40 1 view .LVU13
  53 0010 7047     		bx	lr
  54              	.L4:
  55 0012 C046     		.align	2
  56              	.L3:
  57 0014 00100140 		.word	1073811456
  58 0018 FFFFFF01 		.word	33554431
  59              		.cfi_endproc
  60              	.LFE45:
  62              		.section	.text.EXTI_Init,"ax",%progbits
  63              		.align	1
  64              		.p2align 2,,3
  65              		.global	EXTI_Init
  66              		.syntax unified
  67              		.code	16
ARM GAS  /tmp/cctKAvId.s 			page 3


  68              		.thumb_func
  70              	EXTI_Init:
  71              	.LVL0:
  72              	.LFB46:
  41:Library/src/lcm32f06x_exti.c **** 
  42:Library/src/lcm32f06x_exti.c **** 
  43:Library/src/lcm32f06x_exti.c **** /**
  44:Library/src/lcm32f06x_exti.c ****   * @name EXTI_Init
  45:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Initializes the EXTI according to the specified
  46:Library/src/lcm32f06x_exti.c ****   *             parameters in the EXTI_InitTypeDef.
  47:Library/src/lcm32f06x_exti.c ****   *         CN: 根据EXTI_InitTypeDef中指定的参数初始化EXTI。
  48:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_InitStruct: 
  49:Library/src/lcm32f06x_exti.c ****   *         EN: pointer to a EXTI_InitTypeDef structure that contains the
  50:Library/src/lcm32f06x_exti.c ****   *             configuration information for the specified EXTI peripheral.
  51:Library/src/lcm32f06x_exti.c ****   *         CN: 指向EXTI_InitTypeDef结构的指针，该结构包含指定EXTI外围设备的配置信息。
  52:Library/src/lcm32f06x_exti.c ****   * @retval None
  53:Library/src/lcm32f06x_exti.c ****   */
  54:Library/src/lcm32f06x_exti.c **** void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
  55:Library/src/lcm32f06x_exti.c **** {
  73              		.loc 1 55 1 is_stmt 1 view -0
  74              		.cfi_startproc
  75              		@ args = 0, pretend = 0, frame = 0
  76              		@ frame_needed = 0, uses_anonymous_args = 0
  56:Library/src/lcm32f06x_exti.c ****   uint32_t tmp = 0;
  77              		.loc 1 56 3 view .LVU15
  57:Library/src/lcm32f06x_exti.c **** 
  58:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
  59:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
  78              		.loc 1 59 3 view .LVU16
  60:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
  79              		.loc 1 60 3 view .LVU17
  61:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
  80              		.loc 1 61 3 view .LVU18
  62:Library/src/lcm32f06x_exti.c ****   assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
  81              		.loc 1 62 3 view .LVU19
  63:Library/src/lcm32f06x_exti.c **** 
  64:Library/src/lcm32f06x_exti.c ****   tmp = (uint32_t)EXTI_BASE;
  82              		.loc 1 64 3 view .LVU20
  65:Library/src/lcm32f06x_exti.c **** 
  66:Library/src/lcm32f06x_exti.c ****   if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
  83              		.loc 1 66 3 view .LVU21
  67:Library/src/lcm32f06x_exti.c ****   {
  68:Library/src/lcm32f06x_exti.c ****     /* Clear EXTI line configuration */
  69:Library/src/lcm32f06x_exti.c ****     EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
  70:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
  71:Library/src/lcm32f06x_exti.c **** 
  72:Library/src/lcm32f06x_exti.c ****     tmp += EXTI_InitStruct->EXTI_Mode;
  84              		.loc 1 72 9 is_stmt 0 view .LVU22
  85 0000 174B     		ldr	r3, .L10
  55:Library/src/lcm32f06x_exti.c ****   uint32_t tmp = 0;
  86              		.loc 1 55 1 view .LVU23
  87 0002 30B5     		push	{r4, r5, lr}
  88              	.LCFI0:
  89              		.cfi_def_cfa_offset 12
  90              		.cfi_offset 4, -12
  91              		.cfi_offset 5, -8
  92              		.cfi_offset 14, -4
ARM GAS  /tmp/cctKAvId.s 			page 4


  93              		.loc 1 72 9 view .LVU24
  94 0004 9C46     		mov	ip, r3
  95              		.loc 1 72 27 view .LVU25
  96 0006 0279     		ldrb	r2, [r0, #4]
  69:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
  97              		.loc 1 69 34 view .LVU26
  98 0008 0468     		ldr	r4, [r0]
  66:Library/src/lcm32f06x_exti.c ****   {
  99              		.loc 1 66 6 view .LVU27
 100 000a 8379     		ldrb	r3, [r0, #6]
  69:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 101              		.loc 1 69 18 view .LVU28
 102 000c E143     		mvns	r1, r4
 103              		.loc 1 72 9 view .LVU29
 104 000e 6244     		add	r2, r2, ip
  66:Library/src/lcm32f06x_exti.c ****   {
 105              		.loc 1 66 6 view .LVU30
 106 0010 002B     		cmp	r3, #0
 107 0012 1AD0     		beq	.L6
  69:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 108              		.loc 1 69 5 is_stmt 1 view .LVU31
  69:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 109              		.loc 1 69 9 is_stmt 0 view .LVU32
 110 0014 6346     		mov	r3, ip
 111 0016 1D68     		ldr	r5, [r3]
  69:Library/src/lcm32f06x_exti.c ****     EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
 112              		.loc 1 69 15 view .LVU33
 113 0018 0D40     		ands	r5, r1
 114 001a 1D60     		str	r5, [r3]
  70:Library/src/lcm32f06x_exti.c **** 
 115              		.loc 1 70 5 is_stmt 1 view .LVU34
  70:Library/src/lcm32f06x_exti.c **** 
 116              		.loc 1 70 9 is_stmt 0 view .LVU35
 117 001c 5D68     		ldr	r5, [r3, #4]
  70:Library/src/lcm32f06x_exti.c **** 
 118              		.loc 1 70 15 view .LVU36
 119 001e 2940     		ands	r1, r5
 120 0020 5960     		str	r1, [r3, #4]
 121              		.loc 1 72 5 is_stmt 1 view .LVU37
 122              	.LVL1:
  73:Library/src/lcm32f06x_exti.c **** 
  74:Library/src/lcm32f06x_exti.c ****     *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
 123              		.loc 1 74 5 view .LVU38
 124 0022 1168     		ldr	r1, [r2]
 125              		.loc 1 74 27 is_stmt 0 view .LVU39
 126 0024 2143     		orrs	r1, r4
 127 0026 1160     		str	r1, [r2]
 128              	.LVL2:
  75:Library/src/lcm32f06x_exti.c **** 
  76:Library/src/lcm32f06x_exti.c ****     /* Clear Rising Falling edge configuration */
  77:Library/src/lcm32f06x_exti.c ****     EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
 129              		.loc 1 77 5 is_stmt 1 view .LVU40
 130              		.loc 1 77 9 is_stmt 0 view .LVU41
 131 0028 9968     		ldr	r1, [r3, #8]
 132              		.loc 1 77 35 view .LVU42
 133 002a 0268     		ldr	r2, [r0]
 134              		.loc 1 77 16 view .LVU43
ARM GAS  /tmp/cctKAvId.s 			page 5


 135 002c 9143     		bics	r1, r2
 136 002e 9960     		str	r1, [r3, #8]
  78:Library/src/lcm32f06x_exti.c ****     EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
 137              		.loc 1 78 5 is_stmt 1 view .LVU44
 138              		.loc 1 78 9 is_stmt 0 view .LVU45
 139 0030 D968     		ldr	r1, [r3, #12]
 140              		.loc 1 78 16 view .LVU46
 141 0032 9143     		bics	r1, r2
 142 0034 D960     		str	r1, [r3, #12]
  79:Library/src/lcm32f06x_exti.c **** 
  80:Library/src/lcm32f06x_exti.c ****     /* Select the trigger for the selected external interrupts */
  81:Library/src/lcm32f06x_exti.c ****     if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
 143              		.loc 1 81 5 is_stmt 1 view .LVU47
 144              		.loc 1 81 24 is_stmt 0 view .LVU48
 145 0036 4179     		ldrb	r1, [r0, #5]
 146              		.loc 1 81 8 view .LVU49
 147 0038 1029     		cmp	r1, #16
 148 003a 0AD0     		beq	.L9
  82:Library/src/lcm32f06x_exti.c ****     {
  83:Library/src/lcm32f06x_exti.c ****       /* Rising Falling edge */
  84:Library/src/lcm32f06x_exti.c ****       EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
  85:Library/src/lcm32f06x_exti.c ****       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
  86:Library/src/lcm32f06x_exti.c ****     }
  87:Library/src/lcm32f06x_exti.c ****     else
  88:Library/src/lcm32f06x_exti.c ****     {
  89:Library/src/lcm32f06x_exti.c ****       tmp = (uint32_t)EXTI_BASE;
 149              		.loc 1 89 7 is_stmt 1 view .LVU50
 150              	.LVL3:
  90:Library/src/lcm32f06x_exti.c ****       tmp += EXTI_InitStruct->EXTI_Trigger;
 151              		.loc 1 90 7 view .LVU51
  91:Library/src/lcm32f06x_exti.c **** 
  92:Library/src/lcm32f06x_exti.c ****       *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
 152              		.loc 1 92 7 view .LVU52
  90:Library/src/lcm32f06x_exti.c ****       tmp += EXTI_InitStruct->EXTI_Trigger;
 153              		.loc 1 90 11 is_stmt 0 view .LVU53
 154 003c 084B     		ldr	r3, .L10
 155 003e 9C46     		mov	ip, r3
 156 0040 6144     		add	r1, r1, ip
 157              	.LVL4:
 158              		.loc 1 92 7 view .LVU54
 159 0042 0B68     		ldr	r3, [r1]
 160              		.loc 1 92 29 view .LVU55
 161 0044 1A43     		orrs	r2, r3
 162 0046 0A60     		str	r2, [r1]
 163 0048 02E0     		b	.L5
 164              	.LVL5:
 165              	.L6:
  93:Library/src/lcm32f06x_exti.c ****     }
  94:Library/src/lcm32f06x_exti.c ****   }
  95:Library/src/lcm32f06x_exti.c ****   else
  96:Library/src/lcm32f06x_exti.c ****   {
  97:Library/src/lcm32f06x_exti.c ****     tmp += EXTI_InitStruct->EXTI_Mode;
 166              		.loc 1 97 5 is_stmt 1 view .LVU56
  98:Library/src/lcm32f06x_exti.c **** 
  99:Library/src/lcm32f06x_exti.c ****     /* Disable the selected external lines */
 100:Library/src/lcm32f06x_exti.c ****     *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
 167              		.loc 1 100 5 view .LVU57
ARM GAS  /tmp/cctKAvId.s 			page 6


 168 004a 1368     		ldr	r3, [r2]
 169              		.loc 1 100 27 is_stmt 0 view .LVU58
 170 004c 1940     		ands	r1, r3
 171 004e 1160     		str	r1, [r2]
 172              	.LVL6:
 173              	.L5:
 101:Library/src/lcm32f06x_exti.c ****   }
 102:Library/src/lcm32f06x_exti.c **** }
 174              		.loc 1 102 1 view .LVU59
 175              		@ sp needed
 176 0050 30BD     		pop	{r4, r5, pc}
 177              	.LVL7:
 178              	.L9:
  84:Library/src/lcm32f06x_exti.c ****       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
 179              		.loc 1 84 7 is_stmt 1 view .LVU60
  84:Library/src/lcm32f06x_exti.c ****       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
 180              		.loc 1 84 11 is_stmt 0 view .LVU61
 181 0052 9968     		ldr	r1, [r3, #8]
  84:Library/src/lcm32f06x_exti.c ****       EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
 182              		.loc 1 84 18 view .LVU62
 183 0054 1143     		orrs	r1, r2
 184 0056 9960     		str	r1, [r3, #8]
  85:Library/src/lcm32f06x_exti.c ****     }
 185              		.loc 1 85 7 is_stmt 1 view .LVU63
  85:Library/src/lcm32f06x_exti.c ****     }
 186              		.loc 1 85 11 is_stmt 0 view .LVU64
 187 0058 D968     		ldr	r1, [r3, #12]
  85:Library/src/lcm32f06x_exti.c ****     }
 188              		.loc 1 85 18 view .LVU65
 189 005a 0A43     		orrs	r2, r1
 190 005c DA60     		str	r2, [r3, #12]
 191 005e F7E7     		b	.L5
 192              	.L11:
 193              		.align	2
 194              	.L10:
 195 0060 00100140 		.word	1073811456
 196              		.cfi_endproc
 197              	.LFE46:
 199              		.section	.text.EXTI_StructInit,"ax",%progbits
 200              		.align	1
 201              		.p2align 2,,3
 202              		.global	EXTI_StructInit
 203              		.syntax unified
 204              		.code	16
 205              		.thumb_func
 207              	EXTI_StructInit:
 208              	.LVL8:
 209              	.LFB47:
 103:Library/src/lcm32f06x_exti.c **** 
 104:Library/src/lcm32f06x_exti.c **** /**
 105:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_StructInit
 106:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Fills each EXTI_InitStruct member with its default value.
 107:Library/src/lcm32f06x_exti.c ****   *         CN: 用默认值填充每个 EXTI_InitStruct 成员。
 108:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_InitStruct:
 109:Library/src/lcm32f06x_exti.c ****   *         EN: pointer to a EXTI_InitTypeDef structure that contains the 
 110:Library/src/lcm32f06x_exti.c ****   *             configuration information for the specified EXTI peripheral.
 111:Library/src/lcm32f06x_exti.c ****   *         CN: 指向 EXTI_InitTypeDef 结构的指针，该结构包含指定 EXTI 外设的配置信息。
ARM GAS  /tmp/cctKAvId.s 			page 7


 112:Library/src/lcm32f06x_exti.c ****   * @retval None
 113:Library/src/lcm32f06x_exti.c ****   */
 114:Library/src/lcm32f06x_exti.c **** void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
 115:Library/src/lcm32f06x_exti.c **** {
 210              		.loc 1 115 1 is_stmt 1 view -0
 211              		.cfi_startproc
 212              		@ args = 0, pretend = 0, frame = 0
 213              		@ frame_needed = 0, uses_anonymous_args = 0
 214              		@ link register save eliminated.
 116:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
 215              		.loc 1 116 3 view .LVU67
 117:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 216              		.loc 1 117 30 is_stmt 0 view .LVU68
 217 0000 C022     		movs	r2, #192
 118:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
 119:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_LineCmd = DISABLE;
 120:Library/src/lcm32f06x_exti.c **** }
 218              		.loc 1 120 1 view .LVU69
 219              		@ sp needed
 116:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 220              		.loc 1 116 30 view .LVU70
 221 0002 0023     		movs	r3, #0
 117:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 222              		.loc 1 117 30 view .LVU71
 223 0004 1201     		lsls	r2, r2, #4
 116:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 224              		.loc 1 116 30 view .LVU72
 225 0006 0360     		str	r3, [r0]
 117:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 226              		.loc 1 117 3 is_stmt 1 view .LVU73
 118:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
 227              		.loc 1 118 3 view .LVU74
 117:Library/src/lcm32f06x_exti.c ****   EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
 228              		.loc 1 117 30 is_stmt 0 view .LVU75
 229 0008 8280     		strh	r2, [r0, #4]
 119:Library/src/lcm32f06x_exti.c **** }
 230              		.loc 1 119 3 is_stmt 1 view .LVU76
 119:Library/src/lcm32f06x_exti.c **** }
 231              		.loc 1 119 33 is_stmt 0 view .LVU77
 232 000a 8371     		strb	r3, [r0, #6]
 233              		.loc 1 120 1 view .LVU78
 234 000c 7047     		bx	lr
 235              		.cfi_endproc
 236              	.LFE47:
 238 000e C046     		.section	.text.EXTI_GenerateSWInterrupt,"ax",%progbits
 239              		.align	1
 240              		.p2align 2,,3
 241              		.global	EXTI_GenerateSWInterrupt
 242              		.syntax unified
 243              		.code	16
 244              		.thumb_func
 246              	EXTI_GenerateSWInterrupt:
 247              	.LVL9:
 248              	.LFB48:
 121:Library/src/lcm32f06x_exti.c **** 
 122:Library/src/lcm32f06x_exti.c **** /**
 123:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_GenerateSWInterrupt
ARM GAS  /tmp/cctKAvId.s 			page 8


 124:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Generates a Software interrupt.
 125:Library/src/lcm32f06x_exti.c ****   *         CN: 生成软件中断。
 126:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 127:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 128:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 129:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 130:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 131:Library/src/lcm32f06x_exti.c ****   * @retval None
 132:Library/src/lcm32f06x_exti.c ****   */
 133:Library/src/lcm32f06x_exti.c **** void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
 134:Library/src/lcm32f06x_exti.c **** {
 249              		.loc 1 134 1 is_stmt 1 view -0
 250              		.cfi_startproc
 251              		@ args = 0, pretend = 0, frame = 0
 252              		@ frame_needed = 0, uses_anonymous_args = 0
 253              		@ link register save eliminated.
 135:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 136:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_LINE(EXTI_Line));
 254              		.loc 1 136 3 view .LVU80
 137:Library/src/lcm32f06x_exti.c **** 
 138:Library/src/lcm32f06x_exti.c ****   EXTI->SWIER |= EXTI_Line;
 255              		.loc 1 138 3 view .LVU81
 256              		.loc 1 138 7 is_stmt 0 view .LVU82
 257 0000 024A     		ldr	r2, .L14
 139:Library/src/lcm32f06x_exti.c **** }
 258              		.loc 1 139 1 view .LVU83
 259              		@ sp needed
 138:Library/src/lcm32f06x_exti.c **** }
 260              		.loc 1 138 7 view .LVU84
 261 0002 1369     		ldr	r3, [r2, #16]
 138:Library/src/lcm32f06x_exti.c **** }
 262              		.loc 1 138 15 view .LVU85
 263 0004 0343     		orrs	r3, r0
 264 0006 1361     		str	r3, [r2, #16]
 265              		.loc 1 139 1 view .LVU86
 266 0008 7047     		bx	lr
 267              	.L15:
 268 000a C046     		.align	2
 269              	.L14:
 270 000c 00100140 		.word	1073811456
 271              		.cfi_endproc
 272              	.LFE48:
 274              		.section	.text.EXTI_GetFlagStatus,"ax",%progbits
 275              		.align	1
 276              		.p2align 2,,3
 277              		.global	EXTI_GetFlagStatus
 278              		.syntax unified
 279              		.code	16
 280              		.thumb_func
 282              	EXTI_GetFlagStatus:
 283              	.LVL10:
 284              	.LFB49:
 140:Library/src/lcm32f06x_exti.c **** 
 141:Library/src/lcm32f06x_exti.c **** /**
 142:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_GetFlagStatus
 143:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Checks whether the specified EXTI line flag is set or not.
 144:Library/src/lcm32f06x_exti.c ****   *         CN: 检查是否设置了指定的EXTI线标志。
ARM GAS  /tmp/cctKAvId.s 			page 9


 145:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 146:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 147:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 148:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 149:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 150:Library/src/lcm32f06x_exti.c ****   * @retval FlagStatus
 151:Library/src/lcm32f06x_exti.c ****   */
 152:Library/src/lcm32f06x_exti.c **** FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
 153:Library/src/lcm32f06x_exti.c **** {
 285              		.loc 1 153 1 is_stmt 1 view -0
 286              		.cfi_startproc
 287              		@ args = 0, pretend = 0, frame = 0
 288              		@ frame_needed = 0, uses_anonymous_args = 0
 289              		@ link register save eliminated.
 154:Library/src/lcm32f06x_exti.c ****   FlagStatus bitstatus = RESET;
 290              		.loc 1 154 3 view .LVU88
 155:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 156:Library/src/lcm32f06x_exti.c ****   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
 291              		.loc 1 156 3 view .LVU89
 157:Library/src/lcm32f06x_exti.c **** 
 158:Library/src/lcm32f06x_exti.c ****   if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
 292              		.loc 1 158 3 view .LVU90
 293              		.loc 1 158 12 is_stmt 0 view .LVU91
 294 0000 034B     		ldr	r3, .L17
 159:Library/src/lcm32f06x_exti.c ****   {
 160:Library/src/lcm32f06x_exti.c ****     bitstatus = SET;
 161:Library/src/lcm32f06x_exti.c ****   }
 162:Library/src/lcm32f06x_exti.c ****   else
 163:Library/src/lcm32f06x_exti.c ****   {
 164:Library/src/lcm32f06x_exti.c ****     bitstatus = RESET;
 165:Library/src/lcm32f06x_exti.c ****   }
 166:Library/src/lcm32f06x_exti.c ****   return bitstatus;
 167:Library/src/lcm32f06x_exti.c **** }
 295              		.loc 1 167 1 view .LVU92
 296              		@ sp needed
 158:Library/src/lcm32f06x_exti.c ****   {
 297              		.loc 1 158 12 view .LVU93
 298 0002 5B69     		ldr	r3, [r3, #20]
 299              	.LVL11:
 166:Library/src/lcm32f06x_exti.c **** }
 300              		.loc 1 166 3 is_stmt 1 view .LVU94
 158:Library/src/lcm32f06x_exti.c ****   {
 301              		.loc 1 158 17 is_stmt 0 view .LVU95
 302 0004 1840     		ands	r0, r3
 303              	.LVL12:
 158:Library/src/lcm32f06x_exti.c ****   {
 304              		.loc 1 158 6 view .LVU96
 305 0006 431E     		subs	r3, r0, #1
 306 0008 9841     		sbcs	r0, r0, r3
 307              	.LVL13:
 166:Library/src/lcm32f06x_exti.c **** }
 308              		.loc 1 166 10 discriminator 1 view .LVU97
 309 000a C0B2     		uxtb	r0, r0
 310              		.loc 1 167 1 view .LVU98
 311 000c 7047     		bx	lr
 312              	.L18:
 313 000e C046     		.align	2
ARM GAS  /tmp/cctKAvId.s 			page 10


 314              	.L17:
 315 0010 00100140 		.word	1073811456
 316              		.cfi_endproc
 317              	.LFE49:
 319              		.section	.text.EXTI_ClearFlag,"ax",%progbits
 320              		.align	1
 321              		.p2align 2,,3
 322              		.global	EXTI_ClearFlag
 323              		.syntax unified
 324              		.code	16
 325              		.thumb_func
 327              	EXTI_ClearFlag:
 328              	.LVL14:
 329              	.LFB50:
 168:Library/src/lcm32f06x_exti.c **** 
 169:Library/src/lcm32f06x_exti.c **** /**
 170:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_ClearFlag
 171:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Clears the EXTI's line pending flags.
 172:Library/src/lcm32f06x_exti.c ****   *         CN: 清除EXTI 线挂起标志。
 173:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 174:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 175:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 176:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 177:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 178:Library/src/lcm32f06x_exti.c ****   * @retval None
 179:Library/src/lcm32f06x_exti.c ****   */
 180:Library/src/lcm32f06x_exti.c **** void EXTI_ClearFlag(uint32_t EXTI_Line)
 181:Library/src/lcm32f06x_exti.c **** {
 330              		.loc 1 181 1 is_stmt 1 view -0
 331              		.cfi_startproc
 332              		@ args = 0, pretend = 0, frame = 0
 333              		@ frame_needed = 0, uses_anonymous_args = 0
 334              		@ link register save eliminated.
 182:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 183:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_LINE(EXTI_Line));
 335              		.loc 1 183 3 view .LVU100
 184:Library/src/lcm32f06x_exti.c **** 
 185:Library/src/lcm32f06x_exti.c ****   EXTI->PR = EXTI_Line;
 336              		.loc 1 185 3 view .LVU101
 337              		.loc 1 185 12 is_stmt 0 view .LVU102
 338 0000 014B     		ldr	r3, .L20
 186:Library/src/lcm32f06x_exti.c **** }
 339              		.loc 1 186 1 view .LVU103
 340              		@ sp needed
 185:Library/src/lcm32f06x_exti.c **** }
 341              		.loc 1 185 12 view .LVU104
 342 0002 5861     		str	r0, [r3, #20]
 343              		.loc 1 186 1 view .LVU105
 344 0004 7047     		bx	lr
 345              	.L21:
 346 0006 C046     		.align	2
 347              	.L20:
 348 0008 00100140 		.word	1073811456
 349              		.cfi_endproc
 350              	.LFE50:
 352              		.section	.text.EXTI_GetITStatus,"ax",%progbits
 353              		.align	1
ARM GAS  /tmp/cctKAvId.s 			page 11


 354              		.p2align 2,,3
 355              		.global	EXTI_GetITStatus
 356              		.syntax unified
 357              		.code	16
 358              		.thumb_func
 360              	EXTI_GetITStatus:
 361              	.LVL15:
 362              	.LFB51:
 187:Library/src/lcm32f06x_exti.c **** 
 188:Library/src/lcm32f06x_exti.c **** /**
 189:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_GetITStatus
 190:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Obtain the interrupt status of EXTI lines.
 191:Library/src/lcm32f06x_exti.c ****   *         CN: 获取EXTI 线的中断状态。
 192:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 193:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 194:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 195:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 196:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 197:Library/src/lcm32f06x_exti.c ****   * @retval ITStatus
 198:Library/src/lcm32f06x_exti.c ****   */
 199:Library/src/lcm32f06x_exti.c **** ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
 200:Library/src/lcm32f06x_exti.c **** {
 363              		.loc 1 200 1 is_stmt 1 view -0
 364              		.cfi_startproc
 365              		@ args = 0, pretend = 0, frame = 0
 366              		@ frame_needed = 0, uses_anonymous_args = 0
 367              		@ link register save eliminated.
 201:Library/src/lcm32f06x_exti.c ****   ITStatus bitstatus = RESET;
 368              		.loc 1 201 3 view .LVU107
 202:Library/src/lcm32f06x_exti.c ****   uint32_t enablestatus = 0;
 369              		.loc 1 202 3 view .LVU108
 203:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 204:Library/src/lcm32f06x_exti.c ****   assert_param(IS_GET_EXTI_LINE(EXTI_Line));
 370              		.loc 1 204 3 view .LVU109
 205:Library/src/lcm32f06x_exti.c **** 
 206:Library/src/lcm32f06x_exti.c ****   enablestatus = EXTI->IMR & EXTI_Line;
 371              		.loc 1 206 3 view .LVU110
 200:Library/src/lcm32f06x_exti.c ****   ITStatus bitstatus = RESET;
 372              		.loc 1 200 1 is_stmt 0 view .LVU111
 373 0000 0300     		movs	r3, r0
 374              		.loc 1 206 22 view .LVU112
 375 0002 054A     		ldr	r2, .L26
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 208:Library/src/lcm32f06x_exti.c ****   {
 209:Library/src/lcm32f06x_exti.c ****     bitstatus = SET;
 210:Library/src/lcm32f06x_exti.c ****   }
 211:Library/src/lcm32f06x_exti.c ****   else
 212:Library/src/lcm32f06x_exti.c ****   {
 213:Library/src/lcm32f06x_exti.c ****     bitstatus = RESET;
 376              		.loc 1 213 15 view .LVU113
 377 0004 0020     		movs	r0, #0
 378              	.LVL16:
 206:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 379              		.loc 1 206 22 view .LVU114
 380 0006 1168     		ldr	r1, [r2]
 381              	.LVL17:
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
ARM GAS  /tmp/cctKAvId.s 			page 12


 382              		.loc 1 207 3 is_stmt 1 view .LVU115
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 383              		.loc 1 207 13 is_stmt 0 view .LVU116
 384 0008 5269     		ldr	r2, [r2, #20]
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 385              		.loc 1 207 6 view .LVU117
 386 000a 1342     		tst	r3, r2
 387 000c 03D0     		beq	.L23
 206:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 388              		.loc 1 206 16 view .LVU118
 389 000e 0B40     		ands	r3, r1
 390              	.LVL18:
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 391              		.loc 1 207 51 discriminator 1 view .LVU119
 392 0010 5A1E     		subs	r2, r3, #1
 393 0012 9341     		sbcs	r3, r3, r2
 394              	.LVL19:
 207:Library/src/lcm32f06x_exti.c ****   if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
 395              		.loc 1 207 51 discriminator 1 view .LVU120
 396 0014 D8B2     		uxtb	r0, r3
 397              	.L23:
 398              	.LVL20:
 214:Library/src/lcm32f06x_exti.c ****   }
 215:Library/src/lcm32f06x_exti.c ****   return bitstatus;
 399              		.loc 1 215 3 is_stmt 1 view .LVU121
 216:Library/src/lcm32f06x_exti.c **** }
 400              		.loc 1 216 1 is_stmt 0 view .LVU122
 401              		@ sp needed
 402 0016 7047     		bx	lr
 403              	.L27:
 404              		.align	2
 405              	.L26:
 406 0018 00100140 		.word	1073811456
 407              		.cfi_endproc
 408              	.LFE51:
 410              		.section	.text.EXTI_ClearITPendingBit,"ax",%progbits
 411              		.align	1
 412              		.p2align 2,,3
 413              		.global	EXTI_ClearITPendingBit
 414              		.syntax unified
 415              		.code	16
 416              		.thumb_func
 418              	EXTI_ClearITPendingBit:
 419              	.LFB56:
 420              		.cfi_startproc
 217:Library/src/lcm32f06x_exti.c **** 
 218:Library/src/lcm32f06x_exti.c **** /**
 219:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_ClearITPendingBit
 220:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Clears the EXTI's line pending bits.
 221:Library/src/lcm32f06x_exti.c ****   *         CN: 清除EXTI的行挂起位。
 222:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 223:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 224:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 225:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 226:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 227:Library/src/lcm32f06x_exti.c ****   * @retval ITStatus
 228:Library/src/lcm32f06x_exti.c ****   */
ARM GAS  /tmp/cctKAvId.s 			page 13


 229:Library/src/lcm32f06x_exti.c **** void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
 421              		.loc 1 229 6 is_stmt 1 view -0
 422              		@ args = 0, pretend = 0, frame = 0
 423              		@ frame_needed = 0, uses_anonymous_args = 0
 424              		@ link register save eliminated.
 425 0000 014B     		ldr	r3, .L29
 426              		@ sp needed
 427 0002 5861     		str	r0, [r3, #20]
 428 0004 7047     		bx	lr
 429              	.L30:
 430 0006 C046     		.align	2
 431              	.L29:
 432 0008 00100140 		.word	1073811456
 433              		.cfi_endproc
 434              	.LFE56:
 436              		.section	.text.EXTI_ConnectTo,"ax",%progbits
 437              		.align	1
 438              		.p2align 2,,3
 439              		.global	EXTI_ConnectTo
 440              		.syntax unified
 441              		.code	16
 442              		.thumb_func
 444              	EXTI_ConnectTo:
 445              	.LVL21:
 446              	.LFB53:
 230:Library/src/lcm32f06x_exti.c **** {
 231:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 232:Library/src/lcm32f06x_exti.c ****   assert_param(IS_EXTI_LINE(EXTI_Line));
 233:Library/src/lcm32f06x_exti.c **** 
 234:Library/src/lcm32f06x_exti.c ****   EXTI->PR = EXTI_Line;
 235:Library/src/lcm32f06x_exti.c **** }
 236:Library/src/lcm32f06x_exti.c **** 
 237:Library/src/lcm32f06x_exti.c **** /**
 238:Library/src/lcm32f06x_exti.c ****   * @name   EXTI_ConnectTo
 239:Library/src/lcm32f06x_exti.c ****   * @brief  EN: GPIO optional interrupt line.
 240:Library/src/lcm32f06x_exti.c ****   *         CN: GPIO可选连中断线上。
 241:Library/src/lcm32f06x_exti.c ****   * @param  GPIOx:
 242:Library/src/lcm32f06x_exti.c ****   *         EN: where x can be A or B to select the GPIO peripheral.
 243:Library/src/lcm32f06x_exti.c ****   *         CN: x 可以是 A 或 B 以选择 GPIO 外设
 244:Library/src/lcm32f06x_exti.c ****   * @param  EXTI_Line:
 245:Library/src/lcm32f06x_exti.c ****   *         EN: specifies the EXTI lines to be enabled or disabled.
 246:Library/src/lcm32f06x_exti.c ****   *             This parameter can be any combination of EXTI_Linex where x can be (0..23).
 247:Library/src/lcm32f06x_exti.c ****   *         CN: 指定要启用或禁用的EXTI线。
 248:Library/src/lcm32f06x_exti.c ****   *             此参数可以是EXTI_Linex的任意组合，其中x可以是（0..23）。
 249:Library/src/lcm32f06x_exti.c ****   * @retval ITStatus
 250:Library/src/lcm32f06x_exti.c ****   */
 251:Library/src/lcm32f06x_exti.c **** void EXTI_ConnectTo(GPIO_TypeDef *GPIOx, uint32_t EXTI_Line)
 252:Library/src/lcm32f06x_exti.c **** {
 447              		.loc 1 252 1 view -0
 448              		.cfi_startproc
 449              		@ args = 0, pretend = 0, frame = 0
 450              		@ frame_needed = 0, uses_anonymous_args = 0
 253:Library/src/lcm32f06x_exti.c ****   unsigned int tmpreg = 0, tmpreg1 = 0, tmpFlag;
 451              		.loc 1 253 3 view .LVU125
 254:Library/src/lcm32f06x_exti.c ****   unsigned char i, setValue;
 452              		.loc 1 254 3 view .LVU126
 255:Library/src/lcm32f06x_exti.c ****   unsigned char tmpLine;
ARM GAS  /tmp/cctKAvId.s 			page 14


 453              		.loc 1 255 3 view .LVU127
 256:Library/src/lcm32f06x_exti.c ****   tmpreg = SYSCTRL->EXTI_CFG0;
 454              		.loc 1 256 3 view .LVU128
 252:Library/src/lcm32f06x_exti.c ****   unsigned int tmpreg = 0, tmpreg1 = 0, tmpFlag;
 455              		.loc 1 252 1 is_stmt 0 view .LVU129
 456 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 457              	.LCFI1:
 458              		.cfi_def_cfa_offset 20
 459              		.cfi_offset 4, -20
 460              		.cfi_offset 5, -16
 461              		.cfi_offset 6, -12
 462              		.cfi_offset 7, -8
 463              		.cfi_offset 14, -4
 464 0002 5746     		mov	r7, r10
 465 0004 4E46     		mov	r6, r9
 466 0006 4546     		mov	r5, r8
 467 0008 DE46     		mov	lr, fp
 468              		.loc 1 256 10 view .LVU130
 469 000a 2D4B     		ldr	r3, .L42
 252:Library/src/lcm32f06x_exti.c ****   unsigned int tmpreg = 0, tmpreg1 = 0, tmpFlag;
 470              		.loc 1 252 1 view .LVU131
 471 000c E0B5     		push	{r5, r6, r7, lr}
 472              	.LCFI2:
 473              		.cfi_def_cfa_offset 36
 474              		.cfi_offset 8, -36
 475              		.cfi_offset 9, -32
 476              		.cfi_offset 10, -28
 477              		.cfi_offset 11, -24
 478              		.loc 1 256 10 view .LVU132
 479 000e 9C46     		mov	ip, r3
 480 0010 9D69     		ldr	r5, [r3, #24]
 481              	.LVL22:
 257:Library/src/lcm32f06x_exti.c ****   tmpreg1 = SYSCTRL->EXTI_CFG1;
 482              		.loc 1 257 3 is_stmt 1 view .LVU133
 483              		.loc 1 257 11 is_stmt 0 view .LVU134
 484 0012 DE69     		ldr	r6, [r3, #28]
 485              	.LVL23:
 258:Library/src/lcm32f06x_exti.c ****   if (GPIOx == GPIOA)
 486              		.loc 1 258 3 is_stmt 1 view .LVU135
 259:Library/src/lcm32f06x_exti.c ****     setValue = 0;
 487              		.loc 1 259 5 view .LVU136
 260:Library/src/lcm32f06x_exti.c ****   if (GPIOx == GPIOB)
 488              		.loc 1 260 3 view .LVU137
 489              		.loc 1 260 6 is_stmt 0 view .LVU138
 490 0014 2B4B     		ldr	r3, .L42+4
 261:Library/src/lcm32f06x_exti.c ****     setValue = 1;
 262:Library/src/lcm32f06x_exti.c ****   tmpLine = 0;
 263:Library/src/lcm32f06x_exti.c ****   for (i = 0; i < 16; i++)
 264:Library/src/lcm32f06x_exti.c ****   {
 265:Library/src/lcm32f06x_exti.c ****     tmpFlag = EXTI_Line & (1 << i);
 491              		.loc 1 265 30 view .LVU139
 492 0016 0122     		movs	r2, #1
 260:Library/src/lcm32f06x_exti.c ****   if (GPIOx == GPIOB)
 493              		.loc 1 260 6 view .LVU140
 494 0018 9846     		mov	r8, r3
 495 001a 4044     		add	r0, r0, r8
 496              	.LVL24:
ARM GAS  /tmp/cctKAvId.s 			page 15


 260:Library/src/lcm32f06x_exti.c ****   if (GPIOx == GPIOB)
 497              		.loc 1 260 6 view .LVU141
 498 001c 4342     		rsbs	r3, r0, #0
 499 001e 5841     		adcs	r0, r0, r3
 500              	.LVL25:
 501              		.loc 1 265 30 view .LVU142
 502 0020 9046     		mov	r8, r2
 266:Library/src/lcm32f06x_exti.c ****     tmpLine++;
 267:Library/src/lcm32f06x_exti.c ****     if (tmpFlag)
 268:Library/src/lcm32f06x_exti.c ****     {
 269:Library/src/lcm32f06x_exti.c ****       if (tmpLine <= 8)
 270:Library/src/lcm32f06x_exti.c ****       {
 271:Library/src/lcm32f06x_exti.c ****         tmpreg &= ~((7) << (4 * (tmpLine - 1)));
 272:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 273:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 274:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 275:Library/src/lcm32f06x_exti.c ****         __dekey();
 276:Library/src/lcm32f06x_exti.c ****       }
 277:Library/src/lcm32f06x_exti.c ****       else
 278:Library/src/lcm32f06x_exti.c ****       {
 279:Library/src/lcm32f06x_exti.c ****         tmpreg1 &= ~((7) << (4 * (tmpLine - 9)));
 503              		.loc 1 279 26 view .LVU143
 504 0022 0632     		adds	r2, r2, #6
 505 0024 9346     		mov	fp, r2
 280:Library/src/lcm32f06x_exti.c ****         tmpreg1 |= setValue << (4 * (tmpLine - 9));
 281:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 506              		.loc 1 281 9 discriminator 3 view .LVU144
 507 0026 284A     		ldr	r2, .L42+8
 260:Library/src/lcm32f06x_exti.c ****     setValue = 1;
 508              		.loc 1 260 6 view .LVU145
 509 0028 C3B2     		uxtb	r3, r0
 510 002a 2020     		movs	r0, #32
 511 002c 9946     		mov	r9, r3
 512              	.LVL26:
 262:Library/src/lcm32f06x_exti.c ****   for (i = 0; i < 16; i++)
 513              		.loc 1 262 3 is_stmt 1 view .LVU146
 263:Library/src/lcm32f06x_exti.c ****   {
 514              		.loc 1 263 3 view .LVU147
 263:Library/src/lcm32f06x_exti.c ****   {
 515              		.loc 1 263 17 discriminator 1 view .LVU148
 516              		.loc 1 281 9 is_stmt 0 discriminator 3 view .LVU149
 517 002e 9246     		mov	r10, r2
 260:Library/src/lcm32f06x_exti.c ****     setValue = 1;
 518              		.loc 1 260 6 view .LVU150
 519 0030 0023     		movs	r3, #0
 520              		.loc 1 281 9 discriminator 3 view .LVU151
 521 0032 264F     		ldr	r7, .L42+12
 260:Library/src/lcm32f06x_exti.c ****     setValue = 1;
 522              		.loc 1 260 6 view .LVU152
 523 0034 4042     		rsbs	r0, r0, #0
 524              	.LVL27:
 525              	.L36:
 265:Library/src/lcm32f06x_exti.c ****     tmpLine++;
 526              		.loc 1 265 5 is_stmt 1 view .LVU153
 266:Library/src/lcm32f06x_exti.c ****     if (tmpFlag)
 527              		.loc 1 266 5 view .LVU154
 267:Library/src/lcm32f06x_exti.c ****     {
ARM GAS  /tmp/cctKAvId.s 			page 16


 528              		.loc 1 267 5 view .LVU155
 267:Library/src/lcm32f06x_exti.c ****     {
 529              		.loc 1 267 8 is_stmt 0 view .LVU156
 530 0036 4246     		mov	r2, r8
 531 0038 9A40     		lsls	r2, r2, r3
 532 003a 5C1C     		adds	r4, r3, #1
 533 003c 1142     		tst	r1, r2
 534 003e 1DD0     		beq	.L32
 535              	.LVL28:
 536              	.L40:
 269:Library/src/lcm32f06x_exti.c ****       {
 537              		.loc 1 269 7 is_stmt 1 view .LVU157
 269:Library/src/lcm32f06x_exti.c ****       {
 538              		.loc 1 269 10 is_stmt 0 view .LVU158
 539 0040 E2B2     		uxtb	r2, r4
 540 0042 082A     		cmp	r2, #8
 541 0044 24D8     		bhi	.L33
 271:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 542              		.loc 1 271 9 is_stmt 1 view .LVU159
 271:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 543              		.loc 1 271 25 is_stmt 0 view .LVU160
 544 0046 5A46     		mov	r2, fp
 271:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 545              		.loc 1 271 31 view .LVU161
 546 0048 9B00     		lsls	r3, r3, #2
 547              	.LVL29:
 271:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 548              		.loc 1 271 25 view .LVU162
 549 004a 9A40     		lsls	r2, r2, r3
 271:Library/src/lcm32f06x_exti.c ****         tmpreg |= setValue << (4 * (tmpLine - 1));
 550              		.loc 1 271 16 view .LVU163
 551 004c 9543     		bics	r5, r2
 552              	.LVL30:
 272:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 553              		.loc 1 272 9 is_stmt 1 view .LVU164
 272:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 554              		.loc 1 272 28 is_stmt 0 view .LVU165
 555 004e 4A46     		mov	r2, r9
 556 0050 9A40     		lsls	r2, r2, r3
 272:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 557              		.loc 1 272 16 view .LVU166
 558 0052 1543     		orrs	r5, r2
 559              	.LVL31:
 273:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 560              		.loc 1 273 9 is_stmt 1 view .LVU167
 561              	.LBB18:
 562              	.LBI18:
 563              		.file 2 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
ARM GAS  /tmp/cctKAvId.s 			page 17


  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cctKAvId.s 			page 18


  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cctKAvId.s 			page 19


 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cctKAvId.s 			page 20


 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
ARM GAS  /tmp/cctKAvId.s 			page 21


 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 564              		.loc 2 258 27 view .LVU168
 565              	.LBB19:
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 566              		.loc 2 260 3 view .LVU169
 567              		.syntax divided
 568              	@ 260 "Core/cmsis_gcc.h" 1
 569 0054 BFF36F8F 		isb 0xF
 570              	@ 0 "" 2
 571              		.thumb
 572              		.syntax unified
 573              	.LBE19:
 574              	.LBE18:
 273:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 575              		.loc 1 273 9 discriminator 1 view .LVU170
 576              	.LBB20:
 577              	.LBI20:
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cctKAvId.s 			page 22


 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cctKAvId.s 			page 23


 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
ARM GAS  /tmp/cctKAvId.s 			page 24


 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
ARM GAS  /tmp/cctKAvId.s 			page 25


 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
ARM GAS  /tmp/cctKAvId.s 			page 26


 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
ARM GAS  /tmp/cctKAvId.s 			page 27


 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cctKAvId.s 			page 28


 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cctKAvId.s 			page 29


 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
ARM GAS  /tmp/cctKAvId.s 			page 30


 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
ARM GAS  /tmp/cctKAvId.s 			page 31


 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cctKAvId.s 			page 32


 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cctKAvId.s 			page 33


 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 963:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cctKAvId.s 			page 34


 964:Core/cmsis_gcc.h **** 
 965:Core/cmsis_gcc.h **** 
 966:Core/cmsis_gcc.h **** /**
 967:Core/cmsis_gcc.h ****   \brief   Get Control Register
 968:Core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 969:Core/cmsis_gcc.h ****   \return               Control Register value
 970:Core/cmsis_gcc.h ****  */
 971:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 972:Core/cmsis_gcc.h **** {
 973:Core/cmsis_gcc.h ****   uint32_t result;
 974:Core/cmsis_gcc.h **** 
 975:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 976:Core/cmsis_gcc.h ****   return(result);
 977:Core/cmsis_gcc.h **** }
 978:Core/cmsis_gcc.h **** 
 979:Core/cmsis_gcc.h **** 
 980:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 981:Core/cmsis_gcc.h **** /**
 982:Core/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 983:Core/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 984:Core/cmsis_gcc.h ****   \return               non-secure Control Register value
 985:Core/cmsis_gcc.h ****  */
 986:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 987:Core/cmsis_gcc.h **** {
 988:Core/cmsis_gcc.h ****   uint32_t result;
 989:Core/cmsis_gcc.h **** 
 990:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 991:Core/cmsis_gcc.h ****   return(result);
 992:Core/cmsis_gcc.h **** }
 993:Core/cmsis_gcc.h **** #endif
 994:Core/cmsis_gcc.h **** 
 995:Core/cmsis_gcc.h **** 
 996:Core/cmsis_gcc.h **** /**
 997:Core/cmsis_gcc.h ****   \brief   Set Control Register
 998:Core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 999:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1000:Core/cmsis_gcc.h ****  */
1001:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1002:Core/cmsis_gcc.h **** {
1003:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1004:Core/cmsis_gcc.h ****   __ISB();
1005:Core/cmsis_gcc.h **** }
1006:Core/cmsis_gcc.h **** 
1007:Core/cmsis_gcc.h **** 
1008:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1009:Core/cmsis_gcc.h **** /**
1010:Core/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
1011:Core/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
1012:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1013:Core/cmsis_gcc.h ****  */
1014:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1015:Core/cmsis_gcc.h **** {
1016:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1017:Core/cmsis_gcc.h ****   __ISB();
1018:Core/cmsis_gcc.h **** }
1019:Core/cmsis_gcc.h **** #endif
1020:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cctKAvId.s 			page 35


1021:Core/cmsis_gcc.h **** 
1022:Core/cmsis_gcc.h **** /**
1023:Core/cmsis_gcc.h ****   \brief   Get IPSR Register
1024:Core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
1025:Core/cmsis_gcc.h ****   \return               IPSR Register value
1026:Core/cmsis_gcc.h ****  */
1027:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1028:Core/cmsis_gcc.h **** {
1029:Core/cmsis_gcc.h ****   uint32_t result;
1030:Core/cmsis_gcc.h **** 
1031:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1032:Core/cmsis_gcc.h ****   return(result);
1033:Core/cmsis_gcc.h **** }
1034:Core/cmsis_gcc.h **** 
1035:Core/cmsis_gcc.h **** 
1036:Core/cmsis_gcc.h **** /**
1037:Core/cmsis_gcc.h ****   \brief   Get APSR Register
1038:Core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
1039:Core/cmsis_gcc.h ****   \return               APSR Register value
1040:Core/cmsis_gcc.h ****  */
1041:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1042:Core/cmsis_gcc.h **** {
1043:Core/cmsis_gcc.h ****   uint32_t result;
1044:Core/cmsis_gcc.h **** 
1045:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1046:Core/cmsis_gcc.h ****   return(result);
1047:Core/cmsis_gcc.h **** }
1048:Core/cmsis_gcc.h **** 
1049:Core/cmsis_gcc.h **** 
1050:Core/cmsis_gcc.h **** /**
1051:Core/cmsis_gcc.h ****   \brief   Get xPSR Register
1052:Core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
1053:Core/cmsis_gcc.h ****   \return               xPSR Register value
1054:Core/cmsis_gcc.h ****  */
1055:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1056:Core/cmsis_gcc.h **** {
1057:Core/cmsis_gcc.h ****   uint32_t result;
1058:Core/cmsis_gcc.h **** 
1059:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1060:Core/cmsis_gcc.h ****   return(result);
1061:Core/cmsis_gcc.h **** }
1062:Core/cmsis_gcc.h **** 
1063:Core/cmsis_gcc.h **** 
1064:Core/cmsis_gcc.h **** /**
1065:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
1066:Core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
1067:Core/cmsis_gcc.h ****   \return               PSP Register value
1068:Core/cmsis_gcc.h ****  */
1069:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1070:Core/cmsis_gcc.h **** {
1071:Core/cmsis_gcc.h ****   uint32_t result;
1072:Core/cmsis_gcc.h **** 
1073:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
1074:Core/cmsis_gcc.h ****   return(result);
1075:Core/cmsis_gcc.h **** }
1076:Core/cmsis_gcc.h **** 
1077:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cctKAvId.s 			page 36


1078:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1079:Core/cmsis_gcc.h **** /**
1080:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
1081:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
1082:Core/cmsis_gcc.h ****   \return               PSP Register value
1083:Core/cmsis_gcc.h ****  */
1084:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1085:Core/cmsis_gcc.h **** {
1086:Core/cmsis_gcc.h ****   uint32_t result;
1087:Core/cmsis_gcc.h **** 
1088:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
1089:Core/cmsis_gcc.h ****   return(result);
1090:Core/cmsis_gcc.h **** }
1091:Core/cmsis_gcc.h **** #endif
1092:Core/cmsis_gcc.h **** 
1093:Core/cmsis_gcc.h **** 
1094:Core/cmsis_gcc.h **** /**
1095:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
1096:Core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
1097:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1098:Core/cmsis_gcc.h ****  */
1099:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1100:Core/cmsis_gcc.h **** {
1101:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1102:Core/cmsis_gcc.h **** }
1103:Core/cmsis_gcc.h **** 
1104:Core/cmsis_gcc.h **** 
1105:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1106:Core/cmsis_gcc.h **** /**
1107:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
1108:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
1109:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1110:Core/cmsis_gcc.h ****  */
1111:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1112:Core/cmsis_gcc.h **** {
1113:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1114:Core/cmsis_gcc.h **** }
1115:Core/cmsis_gcc.h **** #endif
1116:Core/cmsis_gcc.h **** 
1117:Core/cmsis_gcc.h **** 
1118:Core/cmsis_gcc.h **** /**
1119:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
1120:Core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
1121:Core/cmsis_gcc.h ****   \return               MSP Register value
1122:Core/cmsis_gcc.h ****  */
1123:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1124:Core/cmsis_gcc.h **** {
1125:Core/cmsis_gcc.h ****   uint32_t result;
1126:Core/cmsis_gcc.h **** 
1127:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
1128:Core/cmsis_gcc.h ****   return(result);
1129:Core/cmsis_gcc.h **** }
1130:Core/cmsis_gcc.h **** 
1131:Core/cmsis_gcc.h **** 
1132:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1133:Core/cmsis_gcc.h **** /**
1134:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
ARM GAS  /tmp/cctKAvId.s 			page 37


1135:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
1136:Core/cmsis_gcc.h ****   \return               MSP Register value
1137:Core/cmsis_gcc.h ****  */
1138:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1139:Core/cmsis_gcc.h **** {
1140:Core/cmsis_gcc.h ****   uint32_t result;
1141:Core/cmsis_gcc.h **** 
1142:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1143:Core/cmsis_gcc.h ****   return(result);
1144:Core/cmsis_gcc.h **** }
1145:Core/cmsis_gcc.h **** #endif
1146:Core/cmsis_gcc.h **** 
1147:Core/cmsis_gcc.h **** 
1148:Core/cmsis_gcc.h **** /**
1149:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
1150:Core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
1151:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1152:Core/cmsis_gcc.h ****  */
1153:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1154:Core/cmsis_gcc.h **** {
1155:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1156:Core/cmsis_gcc.h **** }
1157:Core/cmsis_gcc.h **** 
1158:Core/cmsis_gcc.h **** 
1159:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1160:Core/cmsis_gcc.h **** /**
1161:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
1162:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1163:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1164:Core/cmsis_gcc.h ****  */
1165:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1166:Core/cmsis_gcc.h **** {
1167:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1168:Core/cmsis_gcc.h **** }
1169:Core/cmsis_gcc.h **** #endif
1170:Core/cmsis_gcc.h **** 
1171:Core/cmsis_gcc.h **** 
1172:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1173:Core/cmsis_gcc.h **** /**
1174:Core/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
1175:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1176:Core/cmsis_gcc.h ****   \return               SP Register value
1177:Core/cmsis_gcc.h ****  */
1178:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1179:Core/cmsis_gcc.h **** {
1180:Core/cmsis_gcc.h ****   uint32_t result;
1181:Core/cmsis_gcc.h **** 
1182:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1183:Core/cmsis_gcc.h ****   return(result);
1184:Core/cmsis_gcc.h **** }
1185:Core/cmsis_gcc.h **** 
1186:Core/cmsis_gcc.h **** 
1187:Core/cmsis_gcc.h **** /**
1188:Core/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
1189:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1190:Core/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
1191:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cctKAvId.s 			page 38


1192:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1193:Core/cmsis_gcc.h **** {
1194:Core/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1195:Core/cmsis_gcc.h **** }
1196:Core/cmsis_gcc.h **** #endif
1197:Core/cmsis_gcc.h **** 
1198:Core/cmsis_gcc.h **** 
1199:Core/cmsis_gcc.h **** /**
1200:Core/cmsis_gcc.h ****   \brief   Get Priority Mask
1201:Core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202:Core/cmsis_gcc.h ****   \return               Priority Mask value
1203:Core/cmsis_gcc.h ****  */
1204:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 578              		.loc 2 1204 31 view .LVU171
 579              	.LBB21:
1205:Core/cmsis_gcc.h **** {
1206:Core/cmsis_gcc.h ****   uint32_t result;
 580              		.loc 2 1206 3 view .LVU172
1207:Core/cmsis_gcc.h **** 
1208:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
 581              		.loc 2 1208 3 view .LVU173
 582              		.syntax divided
 583              	@ 1208 "Core/cmsis_gcc.h" 1
 584 0058 EFF31083 		MRS r3, primask
 585              	@ 0 "" 2
 586              	.LVL32:
1209:Core/cmsis_gcc.h ****   return(result);
 587              		.loc 2 1209 3 view .LVU174
 588              		.loc 2 1209 3 is_stmt 0 view .LVU175
 589              		.thumb
 590              		.syntax unified
 591              	.LBE21:
 592              	.LBE20:
 273:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 593              		.loc 1 273 9 is_stmt 1 discriminator 2 view .LVU176
 594              	.LBB22:
 595              	.LBI22:
 960:Core/cmsis_gcc.h **** {
 596              		.loc 2 960 27 view .LVU177
 597              	.LBB23:
 962:Core/cmsis_gcc.h **** }
 598              		.loc 2 962 3 view .LVU178
 599              		.syntax divided
 600              	@ 962 "Core/cmsis_gcc.h" 1
 601 005c 72B6     		cpsid i
 602              	@ 0 "" 2
 603              		.thumb
 604              		.syntax unified
 605              	.LBE23:
 606              	.LBE22:
 273:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 607              		.loc 1 273 9 discriminator 3 view .LVU179
 608 005e 5346     		mov	r3, r10
 609 0060 3B60     		str	r3, [r7]
 273:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG0 |= tmpreg;
 610              		.loc 1 273 25 discriminator 3 view .LVU180
 274:Library/src/lcm32f06x_exti.c ****         __dekey();
ARM GAS  /tmp/cctKAvId.s 			page 39


 611              		.loc 1 274 9 view .LVU181
 274:Library/src/lcm32f06x_exti.c ****         __dekey();
 612              		.loc 1 274 16 is_stmt 0 view .LVU182
 613 0062 6346     		mov	r3, ip
 274:Library/src/lcm32f06x_exti.c ****         __dekey();
 614              		.loc 1 274 28 view .LVU183
 615 0064 6246     		mov	r2, ip
 274:Library/src/lcm32f06x_exti.c ****         __dekey();
 616              		.loc 1 274 16 view .LVU184
 617 0066 9B69     		ldr	r3, [r3, #24]
 274:Library/src/lcm32f06x_exti.c ****         __dekey();
 618              		.loc 1 274 28 view .LVU185
 619 0068 2B43     		orrs	r3, r5
 620 006a 9361     		str	r3, [r2, #24]
 275:Library/src/lcm32f06x_exti.c ****       }
 621              		.loc 1 275 9 is_stmt 1 view .LVU186
 622              	.LBB24:
 623              	.LBI24:
 949:Core/cmsis_gcc.h **** {
 624              		.loc 2 949 27 view .LVU187
 625              	.LBB25:
 951:Core/cmsis_gcc.h **** }
 626              		.loc 2 951 3 view .LVU188
 627              		.syntax divided
 628              	@ 951 "Core/cmsis_gcc.h" 1
 629 006c 62B6     		cpsie i
 630              	@ 0 "" 2
 631              		.thumb
 632              		.syntax unified
 633              	.LBE25:
 634              	.LBE24:
 275:Library/src/lcm32f06x_exti.c ****       }
 635              		.loc 1 275 18 discriminator 1 view .LVU189
 263:Library/src/lcm32f06x_exti.c ****   {
 636              		.loc 1 263 17 discriminator 1 view .LVU190
 637 006e 2300     		movs	r3, r4
 267:Library/src/lcm32f06x_exti.c ****     {
 638              		.loc 1 267 8 is_stmt 0 view .LVU191
 639 0070 4246     		mov	r2, r8
 640 0072 9A40     		lsls	r2, r2, r3
 263:Library/src/lcm32f06x_exti.c ****   {
 641              		.loc 1 263 17 discriminator 1 view .LVU192
 642 0074 0430     		adds	r0, r0, #4
 643              	.LVL33:
 265:Library/src/lcm32f06x_exti.c ****     tmpLine++;
 644              		.loc 1 265 5 is_stmt 1 view .LVU193
 266:Library/src/lcm32f06x_exti.c ****     if (tmpFlag)
 645              		.loc 1 266 5 view .LVU194
 267:Library/src/lcm32f06x_exti.c ****     {
 646              		.loc 1 267 5 view .LVU195
 647 0076 5C1C     		adds	r4, r3, #1
 267:Library/src/lcm32f06x_exti.c ****     {
 648              		.loc 1 267 8 is_stmt 0 view .LVU196
 649 0078 1142     		tst	r1, r2
 650 007a E1D1     		bne	.L40
 651              	.LVL34:
 652              	.L32:
ARM GAS  /tmp/cctKAvId.s 			page 40


 263:Library/src/lcm32f06x_exti.c ****   {
 653              		.loc 1 263 17 is_stmt 1 discriminator 1 view .LVU197
 654 007c 2300     		movs	r3, r4
 655 007e 0430     		adds	r0, r0, #4
 656 0080 102C     		cmp	r4, #16
 657 0082 D8D1     		bne	.L36
 658              	.L41:
 282:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 283:Library/src/lcm32f06x_exti.c ****         __dekey();
 284:Library/src/lcm32f06x_exti.c ****       }
 285:Library/src/lcm32f06x_exti.c ****     }
 286:Library/src/lcm32f06x_exti.c ****   }
 287:Library/src/lcm32f06x_exti.c **** }
 659              		.loc 1 287 1 is_stmt 0 view .LVU198
 660              		@ sp needed
 661              	.LVL35:
 662              	.LVL36:
 663              	.LVL37:
 664              		.loc 1 287 1 view .LVU199
 665 0084 F0BC     		pop	{r4, r5, r6, r7}
 666 0086 BB46     		mov	fp, r7
 667 0088 B246     		mov	r10, r6
 668 008a A946     		mov	r9, r5
 669 008c A046     		mov	r8, r4
 670 008e F0BD     		pop	{r4, r5, r6, r7, pc}
 671              	.LVL38:
 672              	.L33:
 279:Library/src/lcm32f06x_exti.c ****         tmpreg1 |= setValue << (4 * (tmpLine - 9));
 673              		.loc 1 279 9 is_stmt 1 view .LVU200
 279:Library/src/lcm32f06x_exti.c ****         tmpreg1 |= setValue << (4 * (tmpLine - 9));
 674              		.loc 1 279 26 is_stmt 0 view .LVU201
 675 0090 5B46     		mov	r3, fp
 676              	.LVL39:
 279:Library/src/lcm32f06x_exti.c ****         tmpreg1 |= setValue << (4 * (tmpLine - 9));
 677              		.loc 1 279 26 view .LVU202
 678 0092 8340     		lsls	r3, r3, r0
 279:Library/src/lcm32f06x_exti.c ****         tmpreg1 |= setValue << (4 * (tmpLine - 9));
 679              		.loc 1 279 17 view .LVU203
 680 0094 9E43     		bics	r6, r3
 681              	.LVL40:
 280:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 682              		.loc 1 280 9 is_stmt 1 view .LVU204
 280:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 683              		.loc 1 280 29 is_stmt 0 view .LVU205
 684 0096 4B46     		mov	r3, r9
 685 0098 8340     		lsls	r3, r3, r0
 280:Library/src/lcm32f06x_exti.c ****         sysctrl_access();
 686              		.loc 1 280 17 view .LVU206
 687 009a 1E43     		orrs	r6, r3
 688              	.LVL41:
 281:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 689              		.loc 1 281 9 is_stmt 1 view .LVU207
 690              	.LBB26:
 691              	.LBI26:
 258:Core/cmsis_gcc.h **** {
 692              		.loc 2 258 27 view .LVU208
 693              	.LBB27:
ARM GAS  /tmp/cctKAvId.s 			page 41


 260:Core/cmsis_gcc.h **** }
 694              		.loc 2 260 3 view .LVU209
 695              		.syntax divided
 696              	@ 260 "Core/cmsis_gcc.h" 1
 697 009c BFF36F8F 		isb 0xF
 698              	@ 0 "" 2
 699              		.thumb
 700              		.syntax unified
 701              	.LBE27:
 702              	.LBE26:
 281:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 703              		.loc 1 281 9 discriminator 1 view .LVU210
 704              	.LBB28:
 705              	.LBI28:
1204:Core/cmsis_gcc.h **** {
 706              		.loc 2 1204 31 view .LVU211
 707              	.LBB29:
1206:Core/cmsis_gcc.h **** 
 708              		.loc 2 1206 3 view .LVU212
1208:Core/cmsis_gcc.h ****   return(result);
 709              		.loc 2 1208 3 view .LVU213
 710              		.syntax divided
 711              	@ 1208 "Core/cmsis_gcc.h" 1
 712 00a0 EFF31083 		MRS r3, primask
 713              	@ 0 "" 2
 714              	.LVL42:
 715              		.loc 2 1209 3 view .LVU214
 716              		.loc 2 1209 3 is_stmt 0 view .LVU215
 717              		.thumb
 718              		.syntax unified
 719              	.LBE29:
 720              	.LBE28:
 281:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 721              		.loc 1 281 9 is_stmt 1 discriminator 2 view .LVU216
 722              	.LBB30:
 723              	.LBI30:
 960:Core/cmsis_gcc.h **** {
 724              		.loc 2 960 27 view .LVU217
 725              	.LBB31:
 962:Core/cmsis_gcc.h **** }
 726              		.loc 2 962 3 view .LVU218
 727              		.syntax divided
 728              	@ 962 "Core/cmsis_gcc.h" 1
 729 00a4 72B6     		cpsid i
 730              	@ 0 "" 2
 731              		.thumb
 732              		.syntax unified
 733              	.LBE31:
 734              	.LBE30:
 281:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 735              		.loc 1 281 9 discriminator 3 view .LVU219
 736 00a6 5346     		mov	r3, r10
 737 00a8 3B60     		str	r3, [r7]
 281:Library/src/lcm32f06x_exti.c ****         SYSCTRL->EXTI_CFG1 |= tmpreg1;
 738              		.loc 1 281 25 discriminator 3 view .LVU220
 282:Library/src/lcm32f06x_exti.c ****         __dekey();
 739              		.loc 1 282 9 view .LVU221
ARM GAS  /tmp/cctKAvId.s 			page 42


 282:Library/src/lcm32f06x_exti.c ****         __dekey();
 740              		.loc 1 282 16 is_stmt 0 view .LVU222
 741 00aa 6346     		mov	r3, ip
 282:Library/src/lcm32f06x_exti.c ****         __dekey();
 742              		.loc 1 282 28 view .LVU223
 743 00ac 6246     		mov	r2, ip
 282:Library/src/lcm32f06x_exti.c ****         __dekey();
 744              		.loc 1 282 16 view .LVU224
 745 00ae DB69     		ldr	r3, [r3, #28]
 282:Library/src/lcm32f06x_exti.c ****         __dekey();
 746              		.loc 1 282 28 view .LVU225
 747 00b0 3343     		orrs	r3, r6
 748 00b2 D361     		str	r3, [r2, #28]
 283:Library/src/lcm32f06x_exti.c ****       }
 749              		.loc 1 283 9 is_stmt 1 view .LVU226
 750              	.LBB32:
 751              	.LBI32:
 949:Core/cmsis_gcc.h **** {
 752              		.loc 2 949 27 view .LVU227
 753              	.LBB33:
 951:Core/cmsis_gcc.h **** }
 754              		.loc 2 951 3 view .LVU228
 755              		.syntax divided
 756              	@ 951 "Core/cmsis_gcc.h" 1
 757 00b4 62B6     		cpsie i
 758              	@ 0 "" 2
 951:Core/cmsis_gcc.h **** }
 759              		.loc 2 951 3 is_stmt 0 view .LVU229
 760              		.thumb
 761              		.syntax unified
 762              	.LBE33:
 763              	.LBE32:
 263:Library/src/lcm32f06x_exti.c ****   {
 764              		.loc 1 263 17 is_stmt 1 discriminator 1 view .LVU230
 765 00b6 2300     		movs	r3, r4
 766 00b8 0430     		adds	r0, r0, #4
 767 00ba 102C     		cmp	r4, #16
 768 00bc BBD1     		bne	.L36
 263:Library/src/lcm32f06x_exti.c ****   {
 769              		.loc 1 263 17 is_stmt 0 discriminator 1 view .LVU231
 770 00be E1E7     		b	.L41
 771              	.L43:
 772              		.align	2
 773              	.L42:
 774 00c0 00700048 		.word	1207988224
 775 00c4 00FEFFB7 		.word	-1207960064
 776 00c8 9A65FA05 		.word	100296090
 777 00cc 7C700048 		.word	1207988348
 778              		.cfi_endproc
 779              	.LFE53:
 781              		.section	.text.NVIC_Init,"ax",%progbits
 782              		.align	1
 783              		.p2align 2,,3
 784              		.global	NVIC_Init
 785              		.syntax unified
 786              		.code	16
 787              		.thumb_func
ARM GAS  /tmp/cctKAvId.s 			page 43


 789              	NVIC_Init:
 790              	.LVL43:
 791              	.LFB54:
 288:Library/src/lcm32f06x_exti.c **** 
 289:Library/src/lcm32f06x_exti.c **** /**
 290:Library/src/lcm32f06x_exti.c ****   * @name   NVIC_Init
 291:Library/src/lcm32f06x_exti.c ****   * @brief  EN: Initializes the NVIC peripheral according to the specified parameters in the NVIC_I
 292:Library/src/lcm32f06x_exti.c ****   *         CN: 根据NVIC_InitStruct中的指定参数初始化NVIC外围设备。
 293:Library/src/lcm32f06x_exti.c ****   * @param  NVIC_InitStruct: 
 294:Library/src/lcm32f06x_exti.c ****   *         EN: pointer to a NVIC_InitTypeDef structure that contains the configuration information
 295:Library/src/lcm32f06x_exti.c ****   *         CN: 指向NVIC_InitTypeDef结构的指针，该结构包含指定NVIC外围设备的配置信息。
 296:Library/src/lcm32f06x_exti.c ****   * @retval None
 297:Library/src/lcm32f06x_exti.c ****   */
 298:Library/src/lcm32f06x_exti.c **** void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
 299:Library/src/lcm32f06x_exti.c **** {
 792              		.loc 1 299 1 is_stmt 1 view -0
 793              		.cfi_startproc
 794              		@ args = 0, pretend = 0, frame = 0
 795              		@ frame_needed = 0, uses_anonymous_args = 0
 300:Library/src/lcm32f06x_exti.c ****   uint32_t tmppriority = 0x00;
 796              		.loc 1 300 3 view .LVU233
 301:Library/src/lcm32f06x_exti.c **** 
 302:Library/src/lcm32f06x_exti.c ****   /* Check the parameters */
 303:Library/src/lcm32f06x_exti.c ****   if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
 797              		.loc 1 303 3 view .LVU234
 304:Library/src/lcm32f06x_exti.c ****   {
 305:Library/src/lcm32f06x_exti.c ****     /* Compute the Corresponding IRQ Priority --------------------------------*/
 306:Library/src/lcm32f06x_exti.c ****     tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
 307:Library/src/lcm32f06x_exti.c ****     tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)
 308:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 309:Library/src/lcm32f06x_exti.c **** 
 310:Library/src/lcm32f06x_exti.c ****     NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
 311:Library/src/lcm32f06x_exti.c **** 
 312:Library/src/lcm32f06x_exti.c ****     /* Enable the Selected IRQ Channels --------------------------------------*/
 313:Library/src/lcm32f06x_exti.c ****     NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
 798              		.loc 1 313 73 is_stmt 0 view .LVU235
 799 0000 1F23     		movs	r3, #31
 800              		.loc 1 313 36 view .LVU236
 801 0002 0122     		movs	r2, #1
 299:Library/src/lcm32f06x_exti.c ****   uint32_t tmppriority = 0x00;
 802              		.loc 1 299 1 view .LVU237
 803 0004 F0B5     		push	{r4, r5, r6, r7, lr}
 804              	.LCFI3:
 805              		.cfi_def_cfa_offset 20
 806              		.cfi_offset 4, -20
 807              		.cfi_offset 5, -16
 808              		.cfi_offset 6, -12
 809              		.cfi_offset 7, -8
 810              		.cfi_offset 14, -4
 306:Library/src/lcm32f06x_exti.c ****     tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)
 811              		.loc 1 306 43 view .LVU238
 812 0006 0578     		ldrb	r5, [r0]
 813              		.loc 1 313 73 view .LVU239
 814 0008 2B40     		ands	r3, r5
 815              		.loc 1 313 36 view .LVU240
 816 000a 9A40     		lsls	r2, r2, r3
 303:Library/src/lcm32f06x_exti.c ****   {
ARM GAS  /tmp/cctKAvId.s 			page 44


 817              		.loc 1 303 6 view .LVU241
 818 000c 8378     		ldrb	r3, [r0, #2]
 819 000e 002B     		cmp	r3, #0
 820 0010 17D0     		beq	.L45
 306:Library/src/lcm32f06x_exti.c ****     tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)
 821              		.loc 1 306 5 is_stmt 1 view .LVU242
 822 0012 0E4B     		ldr	r3, .L47
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 823              		.loc 1 307 88 is_stmt 0 view .LVU243
 824 0014 0324     		movs	r4, #3
 825 0016 9C46     		mov	ip, r3
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 826              		.loc 1 307 50 view .LVU244
 827 0018 FF23     		movs	r3, #255
 828 001a A908     		lsrs	r1, r5, #2
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 829              		.loc 1 307 88 view .LVU245
 830 001c 2C40     		ands	r4, r5
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 831              		.loc 1 307 50 view .LVU246
 832 001e 1D00     		movs	r5, r3
 308:Library/src/lcm32f06x_exti.c **** 
 833              		.loc 1 308 33 view .LVU247
 834 0020 4078     		ldrb	r0, [r0, #1]
 835              	.LVL44:
 306:Library/src/lcm32f06x_exti.c ****     tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)
 836              		.loc 1 306 17 view .LVU248
 837 0022 C026     		movs	r6, #192
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 838              		.loc 1 307 96 view .LVU249
 839 0024 E400     		lsls	r4, r4, #3
 308:Library/src/lcm32f06x_exti.c **** 
 840              		.loc 1 308 84 view .LVU250
 841 0026 8001     		lsls	r0, r0, #6
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 842              		.loc 1 307 50 view .LVU251
 843 0028 A540     		lsls	r5, r5, r4
 308:Library/src/lcm32f06x_exti.c **** 
 844              		.loc 1 308 90 view .LVU252
 845 002a 0340     		ands	r3, r0
 308:Library/src/lcm32f06x_exti.c **** 
 846              		.loc 1 308 20 view .LVU253
 847 002c A340     		lsls	r3, r3, r4
 848 002e 8900     		lsls	r1, r1, #2
 849 0030 6144     		add	r1, r1, ip
 306:Library/src/lcm32f06x_exti.c ****     tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)
 850              		.loc 1 306 17 view .LVU254
 851 0032 B600     		lsls	r6, r6, #2
 852 0034 8F59     		ldr	r7, [r1, r6]
 853              	.LVL45:
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 854              		.loc 1 307 5 is_stmt 1 view .LVU255
 307:Library/src/lcm32f06x_exti.c ****     tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) <<
 855              		.loc 1 307 17 is_stmt 0 view .LVU256
 856 0036 AF43     		bics	r7, r5
 857              	.LVL46:
 308:Library/src/lcm32f06x_exti.c **** 
ARM GAS  /tmp/cctKAvId.s 			page 45


 858              		.loc 1 308 5 is_stmt 1 view .LVU257
 308:Library/src/lcm32f06x_exti.c **** 
 859              		.loc 1 308 17 is_stmt 0 view .LVU258
 860 0038 3B43     		orrs	r3, r7
 861              	.LVL47:
 310:Library/src/lcm32f06x_exti.c **** 
 862              		.loc 1 310 5 is_stmt 1 view .LVU259
 310:Library/src/lcm32f06x_exti.c **** 
 863              		.loc 1 310 56 is_stmt 0 view .LVU260
 864 003a 8B51     		str	r3, [r1, r6]
 865              		.loc 1 313 5 is_stmt 1 view .LVU261
 866              		.loc 1 313 19 is_stmt 0 view .LVU262
 867 003c 6346     		mov	r3, ip
 868              	.LVL48:
 869              		.loc 1 313 19 view .LVU263
 870 003e 1A60     		str	r2, [r3]
 871              	.LVL49:
 872              	.L44:
 314:Library/src/lcm32f06x_exti.c ****   }
 315:Library/src/lcm32f06x_exti.c ****   else
 316:Library/src/lcm32f06x_exti.c ****   {
 317:Library/src/lcm32f06x_exti.c ****     /* Disable the Selected IRQ Channels -------------------------------------*/
 318:Library/src/lcm32f06x_exti.c ****     NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
 319:Library/src/lcm32f06x_exti.c ****   }
 320:Library/src/lcm32f06x_exti.c **** }
 873              		.loc 1 320 1 view .LVU264
 874              		@ sp needed
 875 0040 F0BD     		pop	{r4, r5, r6, r7, pc}
 876              	.LVL50:
 877              	.L45:
 318:Library/src/lcm32f06x_exti.c ****   }
 878              		.loc 1 318 5 is_stmt 1 view .LVU265
 318:Library/src/lcm32f06x_exti.c ****   }
 879              		.loc 1 318 19 is_stmt 0 view .LVU266
 880 0042 8023     		movs	r3, #128
 881 0044 0149     		ldr	r1, .L47
 882 0046 CA50     		str	r2, [r1, r3]
 883              		.loc 1 320 1 view .LVU267
 884 0048 FAE7     		b	.L44
 885              	.L48:
 886 004a C046     		.align	2
 887              	.L47:
 888 004c 00E100E0 		.word	-536813312
 889              		.cfi_endproc
 890              	.LFE54:
 892              		.text
 893              	.Letext0:
 894              		.file 3 "Library/inc/lcm32f06x.h"
 895              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 896              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 897              		.file 6 "Core/core_cm0.h"
 898              		.file 7 "Library/inc/lcm32f06x_exti.h"
ARM GAS  /tmp/cctKAvId.s 			page 46


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_exti.c
     /tmp/cctKAvId.s:17     .text.EXTI_DeInit:00000000 $t
     /tmp/cctKAvId.s:24     .text.EXTI_DeInit:00000000 EXTI_DeInit
     /tmp/cctKAvId.s:57     .text.EXTI_DeInit:00000014 $d
     /tmp/cctKAvId.s:63     .text.EXTI_Init:00000000 $t
     /tmp/cctKAvId.s:70     .text.EXTI_Init:00000000 EXTI_Init
     /tmp/cctKAvId.s:195    .text.EXTI_Init:00000060 $d
     /tmp/cctKAvId.s:200    .text.EXTI_StructInit:00000000 $t
     /tmp/cctKAvId.s:207    .text.EXTI_StructInit:00000000 EXTI_StructInit
     /tmp/cctKAvId.s:239    .text.EXTI_GenerateSWInterrupt:00000000 $t
     /tmp/cctKAvId.s:246    .text.EXTI_GenerateSWInterrupt:00000000 EXTI_GenerateSWInterrupt
     /tmp/cctKAvId.s:270    .text.EXTI_GenerateSWInterrupt:0000000c $d
     /tmp/cctKAvId.s:275    .text.EXTI_GetFlagStatus:00000000 $t
     /tmp/cctKAvId.s:282    .text.EXTI_GetFlagStatus:00000000 EXTI_GetFlagStatus
     /tmp/cctKAvId.s:315    .text.EXTI_GetFlagStatus:00000010 $d
     /tmp/cctKAvId.s:320    .text.EXTI_ClearFlag:00000000 $t
     /tmp/cctKAvId.s:327    .text.EXTI_ClearFlag:00000000 EXTI_ClearFlag
     /tmp/cctKAvId.s:348    .text.EXTI_ClearFlag:00000008 $d
     /tmp/cctKAvId.s:353    .text.EXTI_GetITStatus:00000000 $t
     /tmp/cctKAvId.s:360    .text.EXTI_GetITStatus:00000000 EXTI_GetITStatus
     /tmp/cctKAvId.s:406    .text.EXTI_GetITStatus:00000018 $d
     /tmp/cctKAvId.s:411    .text.EXTI_ClearITPendingBit:00000000 $t
     /tmp/cctKAvId.s:418    .text.EXTI_ClearITPendingBit:00000000 EXTI_ClearITPendingBit
     /tmp/cctKAvId.s:432    .text.EXTI_ClearITPendingBit:00000008 $d
     /tmp/cctKAvId.s:437    .text.EXTI_ConnectTo:00000000 $t
     /tmp/cctKAvId.s:444    .text.EXTI_ConnectTo:00000000 EXTI_ConnectTo
     /tmp/cctKAvId.s:774    .text.EXTI_ConnectTo:000000c0 $d
     /tmp/cctKAvId.s:782    .text.NVIC_Init:00000000 $t
     /tmp/cctKAvId.s:789    .text.NVIC_Init:00000000 NVIC_Init
     /tmp/cctKAvId.s:888    .text.NVIC_Init:0000004c $d

NO UNDEFINED SYMBOLS
