ARM GAS  /tmp/cckWj3Ij.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_pwr.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Library/src/lcm32f06x_pwr.c"
  16              		.section	.text.PWR_EnterSleepMode,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	PWR_EnterSleepMode
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	PWR_EnterSleepMode:
  25              	.LVL0:
  26              	.LFB45:
   1:Library/src/lcm32f06x_pwr.c **** /**
   2:Library/src/lcm32f06x_pwr.c ****   ******************************************************************************
   3:Library/src/lcm32f06x_pwr.c ****   * @file    lcm32f06x_pwr.c
   4:Library/src/lcm32f06x_pwr.c ****   * @author  System R&D Team
   5:Library/src/lcm32f06x_pwr.c ****   * @version V2.0.2
   6:Library/src/lcm32f06x_pwr.c ****   * @date    10-April-2025
   7:Library/src/lcm32f06x_pwr.c ****   * @brief   This file provides all the pwr firmware functions.
   8:Library/src/lcm32f06x_pwr.c ****   ******************************************************************************
   9:Library/src/lcm32f06x_pwr.c ****   * @attention
  10:Library/src/lcm32f06x_pwr.c ****   *
  11:Library/src/lcm32f06x_pwr.c ****   * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  12:Library/src/lcm32f06x_pwr.c ****   * All rights reserved.
  13:Library/src/lcm32f06x_pwr.c ****   *
  14:Library/src/lcm32f06x_pwr.c ****   * This software is licensed under terms that can be found in the LICENSE file
  15:Library/src/lcm32f06x_pwr.c ****   * in the root directory of this software component.
  16:Library/src/lcm32f06x_pwr.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  17:Library/src/lcm32f06x_pwr.c ****   *
  18:Library/src/lcm32f06x_pwr.c ****   ******************************************************************************
  19:Library/src/lcm32f06x_pwr.c ****   */
  20:Library/src/lcm32f06x_pwr.c **** /* Includes ------------------------------------------------------------------*/
  21:Library/src/lcm32f06x_pwr.c **** #include "lcm32f06x_pwr.h"
  22:Library/src/lcm32f06x_pwr.c **** 
  23:Library/src/lcm32f06x_pwr.c **** /*--------------------------------------------------------------------------------------------
  24:Library/src/lcm32f06x_pwr.c **** sleepmode cmd :  mcu Working current about 400ua
  25:Library/src/lcm32f06x_pwr.c ****   --------------------------------------------------------------------------------------------*/
  26:Library/src/lcm32f06x_pwr.c **** /**
  27:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LDODriverLevel
  28:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enters Sleep mode.
  29:Library/src/lcm32f06x_pwr.c ****   *         CN: 进入睡眠模式。
  30:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_SLEEPEntry: 
  31:Library/src/lcm32f06x_pwr.c ****   *         EN: specifies if SLEEP mode in entered with WFI or WFE instruction.
  32:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定是否使用WFI或WFE指令进入睡眠模式。
ARM GAS  /tmp/cckWj3Ij.s 			page 2


  33:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_SLEEPEntry_WFI
  34:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_SLEEPEntry_WFE
  35:Library/src/lcm32f06x_pwr.c ****   * @retval None
  36:Library/src/lcm32f06x_pwr.c ****   */
  37:Library/src/lcm32f06x_pwr.c **** void PWR_EnterSleepMode(uint32_t PWR_SLEEPEntry)
  38:Library/src/lcm32f06x_pwr.c **** {
  27              		.loc 1 38 1 view -0
  28              		.cfi_startproc
  29              		@ args = 0, pretend = 0, frame = 0
  30              		@ frame_needed = 0, uses_anonymous_args = 0
  31              		@ link register save eliminated.
  39:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
  32              		.loc 1 39 3 view .LVU1
  40:Library/src/lcm32f06x_pwr.c **** 
  41:Library/src/lcm32f06x_pwr.c ****   /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
  42:Library/src/lcm32f06x_pwr.c ****   SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  33              		.loc 1 42 3 view .LVU2
  34              		.loc 1 42 12 is_stmt 0 view .LVU3
  35 0000 0421     		movs	r1, #4
  36              		.loc 1 42 6 view .LVU4
  37 0002 054A     		ldr	r2, .L6
  38 0004 1369     		ldr	r3, [r2, #16]
  39              		.loc 1 42 12 view .LVU5
  40 0006 8B43     		bics	r3, r1
  41 0008 1361     		str	r3, [r2, #16]
  43:Library/src/lcm32f06x_pwr.c **** 
  44:Library/src/lcm32f06x_pwr.c ****   /* Select SLEEP mode entry -------------------------------------------------*/
  45:Library/src/lcm32f06x_pwr.c ****   if (PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
  42              		.loc 1 45 3 is_stmt 1 view .LVU6
  43              		.loc 1 45 6 is_stmt 0 view .LVU7
  44 000a 0128     		cmp	r0, #1
  45 000c 01D0     		beq	.L5
  46:Library/src/lcm32f06x_pwr.c ****   {
  47:Library/src/lcm32f06x_pwr.c ****     __WFI();
  48:Library/src/lcm32f06x_pwr.c ****   }
  49:Library/src/lcm32f06x_pwr.c ****   else
  50:Library/src/lcm32f06x_pwr.c ****   {
  51:Library/src/lcm32f06x_pwr.c ****     __WFE();
  46              		.loc 1 51 5 is_stmt 1 view .LVU8
  47              		.syntax divided
  48              	@ 51 "Library/src/lcm32f06x_pwr.c" 1
  49 000e 20BF     		wfe
  50              	@ 0 "" 2
  51              		.thumb
  52              		.syntax unified
  53              	.L1:
  52:Library/src/lcm32f06x_pwr.c ****   }
  53:Library/src/lcm32f06x_pwr.c **** }
  54              		.loc 1 53 1 is_stmt 0 view .LVU9
  55              		@ sp needed
  56 0010 7047     		bx	lr
  57              	.L5:
  47:Library/src/lcm32f06x_pwr.c ****   }
  58              		.loc 1 47 5 is_stmt 1 view .LVU10
  59              		.syntax divided
  60              	@ 47 "Library/src/lcm32f06x_pwr.c" 1
  61 0012 30BF     		wfi
ARM GAS  /tmp/cckWj3Ij.s 			page 3


  62              	@ 0 "" 2
  63              		.thumb
  64              		.syntax unified
  65 0014 FCE7     		b	.L1
  66              	.L7:
  67 0016 C046     		.align	2
  68              	.L6:
  69 0018 00ED00E0 		.word	-536810240
  70              		.cfi_endproc
  71              	.LFE45:
  73              		.section	.text.PWR_EnterUR_STOPMode,"ax",%progbits
  74              		.align	1
  75              		.p2align 2,,3
  76              		.global	PWR_EnterUR_STOPMode
  77              		.syntax unified
  78              		.code	16
  79              		.thumb_func
  81              	PWR_EnterUR_STOPMode:
  82              	.LVL1:
  83              	.LFB46:
  54:Library/src/lcm32f06x_pwr.c **** /**
  55:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_EnterUR_STOPMode
  56:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enters Ultra low power stop mode.
  57:Library/src/lcm32f06x_pwr.c ****   *         CN: 进入超低功耗停机模式。
  58:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_STOPEntry: 
  59:Library/src/lcm32f06x_pwr.c ****   *         EN: specifies if Ultra low power stop mode in entered with WFI or WFE instruction.
  60:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定是否使用WFI或WFE指令进入超低功耗停机模式。
  61:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFI
  62:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFE
  63:Library/src/lcm32f06x_pwr.c ****   * @retval None
  64:Library/src/lcm32f06x_pwr.c ****   */
  65:Library/src/lcm32f06x_pwr.c **** void PWR_EnterUR_STOPMode(uint32_t PWR_STOPEntry)
  66:Library/src/lcm32f06x_pwr.c **** {
  84              		.loc 1 66 1 view -0
  85              		.cfi_startproc
  86              		@ args = 0, pretend = 0, frame = 0
  87              		@ frame_needed = 0, uses_anonymous_args = 0
  67:Library/src/lcm32f06x_pwr.c ****   /* Check the parameters */
  68:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
  88              		.loc 1 68 3 view .LVU12
  69:Library/src/lcm32f06x_pwr.c **** 
  70:Library/src/lcm32f06x_pwr.c ****   // deep-sleep
  71:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);              // PUMEN
  89              		.loc 1 71 3 view .LVU13
  90              	.LBB446:
  91              	.LBI446:
  72:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);  // FPDS
  73:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(ENABLE);        // LPDS  内核LDO  /kernel LDO
  74:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(ENABLE);   // ULPDS  使能超低功耗 /Enable ultra-low power consumption
  75:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
  76:Library/src/lcm32f06x_pwr.c **** 
  77:Library/src/lcm32f06x_pwr.c ****   SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  78:Library/src/lcm32f06x_pwr.c **** 
  79:Library/src/lcm32f06x_pwr.c ****   if (PWR_STOPEntry == PWR_STOPEntry_WFI)
  80:Library/src/lcm32f06x_pwr.c ****   {
  81:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Interrupt */
  82:Library/src/lcm32f06x_pwr.c ****     __WFI();
ARM GAS  /tmp/cckWj3Ij.s 			page 4


  83:Library/src/lcm32f06x_pwr.c ****     SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  84:Library/src/lcm32f06x_pwr.c ****   }
  85:Library/src/lcm32f06x_pwr.c ****   else
  86:Library/src/lcm32f06x_pwr.c ****   {
  87:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Event */
  88:Library/src/lcm32f06x_pwr.c ****     __WFE();
  89:Library/src/lcm32f06x_pwr.c ****     SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  90:Library/src/lcm32f06x_pwr.c ****   }
  91:Library/src/lcm32f06x_pwr.c **** 
  92:Library/src/lcm32f06x_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
  93:Library/src/lcm32f06x_pwr.c **** }
  94:Library/src/lcm32f06x_pwr.c **** 
  95:Library/src/lcm32f06x_pwr.c **** /**
  96:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_EnterSTOPMode
  97:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enters stop mode.
  98:Library/src/lcm32f06x_pwr.c ****   *         CN: 进入停机模式。
  99:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_STOPEntry: 
 100:Library/src/lcm32f06x_pwr.c ****   *         EN: specifies if stop mode in entered with WFI or WFE instruction.
 101:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定是否使用WFI或WFE指令进入停机模式。
 102:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFI
 103:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFE
 104:Library/src/lcm32f06x_pwr.c ****   * @retval None
 105:Library/src/lcm32f06x_pwr.c ****   */
 106:Library/src/lcm32f06x_pwr.c **** void PWR_EnterSTOPMode(uint32_t PWR_STOPEntry)
 107:Library/src/lcm32f06x_pwr.c **** {
 108:Library/src/lcm32f06x_pwr.c **** 
 109:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);
 110:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);
 111:Library/src/lcm32f06x_pwr.c ****   //	PWR_PowerDownDeepSleep(DISABLE);
 112:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(DISABLE);
 113:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(DISABLE);
 114:Library/src/lcm32f06x_pwr.c **** 
 115:Library/src/lcm32f06x_pwr.c ****   SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 116:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 117:Library/src/lcm32f06x_pwr.c ****   if (PWR_STOPEntry == PWR_STOPEntry_WFI)
 118:Library/src/lcm32f06x_pwr.c ****   {
 119:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Interrupt */
 120:Library/src/lcm32f06x_pwr.c ****     __WFI();
 121:Library/src/lcm32f06x_pwr.c ****   }
 122:Library/src/lcm32f06x_pwr.c ****   else
 123:Library/src/lcm32f06x_pwr.c ****   {
 124:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Event */
 125:Library/src/lcm32f06x_pwr.c ****     __WFE();
 126:Library/src/lcm32f06x_pwr.c ****   }
 127:Library/src/lcm32f06x_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 128:Library/src/lcm32f06x_pwr.c ****   SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 129:Library/src/lcm32f06x_pwr.c **** }
 130:Library/src/lcm32f06x_pwr.c **** 
 131:Library/src/lcm32f06x_pwr.c **** /**
 132:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_EnterLowPowerSTOPMode
 133:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enters low power stop mode.
 134:Library/src/lcm32f06x_pwr.c ****   *         CN: 进入低功耗停机模式。
 135:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_STOPEntry: 
 136:Library/src/lcm32f06x_pwr.c ****   *         EN: specifies if low power stop mode in entered with WFI or WFE instruction.
 137:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定是否使用WFI或WFE指令进入低功耗停机模式。
 138:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFI
 139:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_STOPEntry_WFE
ARM GAS  /tmp/cckWj3Ij.s 			page 5


 140:Library/src/lcm32f06x_pwr.c ****   * @retval None
 141:Library/src/lcm32f06x_pwr.c ****   */
 142:Library/src/lcm32f06x_pwr.c **** void PWR_EnterLowPowerSTOPMode(uint32_t PWR_STOPEntry)
 143:Library/src/lcm32f06x_pwr.c **** {
 144:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);
 145:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);
 146:Library/src/lcm32f06x_pwr.c **** //  PWR_PowerDownDeepSleep(DISABLE);
 147:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(ENABLE);
 148:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(DISABLE);
 149:Library/src/lcm32f06x_pwr.c **** 
 150:Library/src/lcm32f06x_pwr.c ****   SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 151:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 152:Library/src/lcm32f06x_pwr.c ****   if (PWR_STOPEntry == PWR_STOPEntry_WFI)
 153:Library/src/lcm32f06x_pwr.c ****   {
 154:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Interrupt */
 155:Library/src/lcm32f06x_pwr.c ****     __WFI();
 156:Library/src/lcm32f06x_pwr.c ****   }
 157:Library/src/lcm32f06x_pwr.c ****   else
 158:Library/src/lcm32f06x_pwr.c ****   {
 159:Library/src/lcm32f06x_pwr.c ****     /* Request Wait For Event */
 160:Library/src/lcm32f06x_pwr.c ****     __WFE();
 161:Library/src/lcm32f06x_pwr.c ****   }
 162:Library/src/lcm32f06x_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 163:Library/src/lcm32f06x_pwr.c ****   SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 164:Library/src/lcm32f06x_pwr.c **** }
 165:Library/src/lcm32f06x_pwr.c **** 
 166:Library/src/lcm32f06x_pwr.c **** /**
 167:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_EnterSTANDBYMode
 168:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enters standyby mode.
 169:Library/src/lcm32f06x_pwr.c ****   *         CN: 进入待机模式。
 170:Library/src/lcm32f06x_pwr.c ****   * @retval None
 171:Library/src/lcm32f06x_pwr.c ****   */
 172:Library/src/lcm32f06x_pwr.c **** void PWR_EnterSTANDBYMode(void)
 173:Library/src/lcm32f06x_pwr.c **** { /* Check the parameters */
 174:Library/src/lcm32f06x_pwr.c **** 
 175:Library/src/lcm32f06x_pwr.c ****   // deep-sleep
 176:Library/src/lcm32f06x_pwr.c **** 
 177:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);              //CHIPCTRL->CR_b.PMUEN=1;
 178:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);  //CHIPCTRL->CR_b.FPDS=1;
 179:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(ENABLE);        //CHIPCTRL->CR_b.LPDS=1;
 180:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(ENABLE);   //CHIPCTRL->CR_b.ULPDS=1;
 181:Library/src/lcm32f06x_pwr.c ****   SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 182:Library/src/lcm32f06x_pwr.c **** 
 183:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 184:Library/src/lcm32f06x_pwr.c ****   /* Request Wait For Interrupt */
 185:Library/src/lcm32f06x_pwr.c ****   __WFI();
 186:Library/src/lcm32f06x_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 187:Library/src/lcm32f06x_pwr.c ****   //  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 188:Library/src/lcm32f06x_pwr.c **** }
 189:Library/src/lcm32f06x_pwr.c **** 
 190:Library/src/lcm32f06x_pwr.c **** /**
 191:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_AOUTConfig
 192:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Chip power observation output selection.
 193:Library/src/lcm32f06x_pwr.c ****   *         CN: 芯片电源观测输出选择。
 194:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_AOUT: 
 195:Library/src/lcm32f06x_pwr.c ****   *         EN: specifies if Chip power observation output .
 196:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定芯片功率观测输出。
ARM GAS  /tmp/cckWj3Ij.s 			page 6


 197:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_VBG
 198:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_FLASH
 199:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_LOWPOWER
 200:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_ACMPCVREF
 201:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_HALL_MID
 202:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_AOUT_SEL_VDDA_2
 203:Library/src/lcm32f06x_pwr.c ****   * @retval None
 204:Library/src/lcm32f06x_pwr.c ****   */
 205:Library/src/lcm32f06x_pwr.c **** void PWR_AOUTConfig(uint8_t PWR_AOUT)
 206:Library/src/lcm32f06x_pwr.c **** {
 207:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_AOUT_SEL_MODE(PWR_AOUT));
 208:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 209:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 210:Library/src/lcm32f06x_pwr.c ****   __dekey();
 211:Library/src/lcm32f06x_pwr.c **** }
 212:Library/src/lcm32f06x_pwr.c **** 
 213:Library/src/lcm32f06x_pwr.c **** /**
 214:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_AOUTcmd
 215:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Chip power observation output enable.
 216:Library/src/lcm32f06x_pwr.c ****   *         CN: 芯片电源观测输出使能。
 217:Library/src/lcm32f06x_pwr.c ****   * @param  NewState: 
 218:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 219:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 220:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 221:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 222:Library/src/lcm32f06x_pwr.c ****   * @retval None
 223:Library/src/lcm32f06x_pwr.c ****   */
 224:Library/src/lcm32f06x_pwr.c **** void PWR_AOUTcmd(FunctionalState NewState)
 225:Library/src/lcm32f06x_pwr.c **** {
 226:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 227:Library/src/lcm32f06x_pwr.c ****   {
 228:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 229:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 230:Library/src/lcm32f06x_pwr.c ****   }
 231:Library/src/lcm32f06x_pwr.c ****   else
 232:Library/src/lcm32f06x_pwr.c ****   {
 233:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 234:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 235:Library/src/lcm32f06x_pwr.c ****   }
 236:Library/src/lcm32f06x_pwr.c ****   __dekey();
 237:Library/src/lcm32f06x_pwr.c **** }
 238:Library/src/lcm32f06x_pwr.c **** 
 239:Library/src/lcm32f06x_pwr.c **** /**
 240:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVDConfig
 241:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: LVD low-voltage detection level selection.
 242:Library/src/lcm32f06x_pwr.c ****   *         CN: LVD 低压检测电平选择。
 243:Library/src/lcm32f06x_pwr.c ****   * @param  IE: 
 244:Library/src/lcm32f06x_pwr.c ****   *         EN: PWR_LVDLevel.
 245:Library/src/lcm32f06x_pwr.c ****   *         CN: 检测源。
 246:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_LVDLevel: 
 247:Library/src/lcm32f06x_pwr.c ****   *         EN: Detecting voltage levels.
 248:Library/src/lcm32f06x_pwr.c ****   *         CN: 检测电压水平。
 249:Library/src/lcm32f06x_pwr.c ****   * @retval None
 250:Library/src/lcm32f06x_pwr.c ****   */
 251:Library/src/lcm32f06x_pwr.c **** void PWR_LVDConfig(uint8_t IE, uint8_t PWR_LVDLevel)
 252:Library/src/lcm32f06x_pwr.c **** {
 253:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVDIE(IE));
ARM GAS  /tmp/cckWj3Ij.s 			page 7


 254:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVDInternal_MODE(PWR_LVDLevel));
 255:Library/src/lcm32f06x_pwr.c ****   if (!IE) // if internal
 256:Library/src/lcm32f06x_pwr.c ****   {
 257:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 258:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 259:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 260:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 261:Library/src/lcm32f06x_pwr.c ****   }
 262:Library/src/lcm32f06x_pwr.c ****   else
 263:Library/src/lcm32f06x_pwr.c ****   {
 264:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 265:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 266:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 267:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 268:Library/src/lcm32f06x_pwr.c ****   }
 269:Library/src/lcm32f06x_pwr.c ****   __dekey();
 270:Library/src/lcm32f06x_pwr.c **** }
 271:Library/src/lcm32f06x_pwr.c **** 
 272:Library/src/lcm32f06x_pwr.c **** /**
 273:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVDCmd
 274:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: LVD enable control.
 275:Library/src/lcm32f06x_pwr.c ****   *         CN: LVD使能。
 276:Library/src/lcm32f06x_pwr.c ****   * @param NewState: 
 277:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 278:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 279:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 280:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 281:Library/src/lcm32f06x_pwr.c ****   * @retval None
 282:Library/src/lcm32f06x_pwr.c ****   */
 283:Library/src/lcm32f06x_pwr.c **** void PWR_LVDCmd(FunctionalState NewState)
 284:Library/src/lcm32f06x_pwr.c **** {
 285:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 286:Library/src/lcm32f06x_pwr.c ****   {
 287:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 288:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 289:Library/src/lcm32f06x_pwr.c ****   }
 290:Library/src/lcm32f06x_pwr.c ****   else
 291:Library/src/lcm32f06x_pwr.c ****   {
 292:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 293:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 294:Library/src/lcm32f06x_pwr.c ****   }
 295:Library/src/lcm32f06x_pwr.c ****   __dekey();
 296:Library/src/lcm32f06x_pwr.c **** }
 297:Library/src/lcm32f06x_pwr.c **** 
 298:Library/src/lcm32f06x_pwr.c **** /**
 299:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVRConfig
 300:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: LVR Low voltage reset point selection.
 301:Library/src/lcm32f06x_pwr.c ****   *         CN: LVR 低压复位点选择。
 302:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_LVRLevel: 
 303:Library/src/lcm32f06x_pwr.c ****   *         EN: Low voltage reset point.
 304:Library/src/lcm32f06x_pwr.c ****   *         CN: 低压复位点。
 305:Library/src/lcm32f06x_pwr.c ****   * @retval None
 306:Library/src/lcm32f06x_pwr.c ****   */
 307:Library/src/lcm32f06x_pwr.c **** void PWR_LVRConfig(uint32_t PWR_LVRLevel)
 308:Library/src/lcm32f06x_pwr.c **** {
 309:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVRLevel(PWR_LVRLevel));
 310:Library/src/lcm32f06x_pwr.c **** 
ARM GAS  /tmp/cckWj3Ij.s 			page 8


 311:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 312:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 313:Library/src/lcm32f06x_pwr.c ****   __dekey();
 314:Library/src/lcm32f06x_pwr.c **** }
 315:Library/src/lcm32f06x_pwr.c **** 
 316:Library/src/lcm32f06x_pwr.c **** /**
 317:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVRCmd
 318:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: LVR enable control.
 319:Library/src/lcm32f06x_pwr.c ****   *         CN: LVR使能。
 320:Library/src/lcm32f06x_pwr.c ****   * @param NewState: 
 321:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 322:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 323:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 324:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 325:Library/src/lcm32f06x_pwr.c ****   * @retval None
 326:Library/src/lcm32f06x_pwr.c ****   */
 327:Library/src/lcm32f06x_pwr.c **** void PWR_LVRCmd(FunctionalState NewState)
 328:Library/src/lcm32f06x_pwr.c **** {
 329:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 330:Library/src/lcm32f06x_pwr.c ****   {
 331:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 332:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 333:Library/src/lcm32f06x_pwr.c ****   }
 334:Library/src/lcm32f06x_pwr.c ****   else
 335:Library/src/lcm32f06x_pwr.c ****   {
 336:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 337:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 338:Library/src/lcm32f06x_pwr.c ****   }
 339:Library/src/lcm32f06x_pwr.c ****   __dekey();
 340:Library/src/lcm32f06x_pwr.c **** }
 341:Library/src/lcm32f06x_pwr.c **** #if defined (LCM32F067) || defined (LCM32F063)  || defined (LCM32CF6990)
 342:Library/src/lcm32f06x_pwr.c **** /**
 343:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_OPA_BiasCurrentSel
 344:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Operational amplifier bias current control.
 345:Library/src/lcm32f06x_pwr.c ****   *         CN: 运放偏置电流控制。
 346:Library/src/lcm32f06x_pwr.c ****   * @param Bisa_current: 
 347:Library/src/lcm32f06x_pwr.c ****   *         EN: Bias current selection.
 348:Library/src/lcm32f06x_pwr.c ****   *         CN: 偏置电流选择。
 349:Library/src/lcm32f06x_pwr.c ****   * @retval None
 350:Library/src/lcm32f06x_pwr.c ****   */
 351:Library/src/lcm32f06x_pwr.c **** void PWR_OPA_BiasCurrentSel(OPA_TypeDef *OPAx, uint8_t Bisa_current)
 352:Library/src/lcm32f06x_pwr.c **** {
 353:Library/src/lcm32f06x_pwr.c ****     if(OPAx == OPA0)
 354:Library/src/lcm32f06x_pwr.c ****     {
 355:Library/src/lcm32f06x_pwr.c ****       chipctrl_access();
 356:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 357:Library/src/lcm32f06x_pwr.c ****       __dekey();
 358:Library/src/lcm32f06x_pwr.c ****     }
 359:Library/src/lcm32f06x_pwr.c ****     else if(OPAx == OPA1)
 360:Library/src/lcm32f06x_pwr.c ****     {
 361:Library/src/lcm32f06x_pwr.c ****       chipctrl_access();
 362:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 363:Library/src/lcm32f06x_pwr.c ****       __dekey();
 364:Library/src/lcm32f06x_pwr.c ****     }
 365:Library/src/lcm32f06x_pwr.c ****     else if(OPAx == OPA2)
 366:Library/src/lcm32f06x_pwr.c ****     {
 367:Library/src/lcm32f06x_pwr.c ****       chipctrl_access();
ARM GAS  /tmp/cckWj3Ij.s 			page 9


 368:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 369:Library/src/lcm32f06x_pwr.c ****       __dekey();
 370:Library/src/lcm32f06x_pwr.c ****     }
 371:Library/src/lcm32f06x_pwr.c **** }
 372:Library/src/lcm32f06x_pwr.c **** #elif defined (LCM32F062)
 373:Library/src/lcm32f06x_pwr.c ****   /* None OPA */
 374:Library/src/lcm32f06x_pwr.c **** #endif
 375:Library/src/lcm32f06x_pwr.c **** 
 376:Library/src/lcm32f06x_pwr.c **** /**
 377:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVRClearFlag
 378:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Clear the low voltage monitoring reset flag.
 379:Library/src/lcm32f06x_pwr.c ****   *         CN: 清除低压监测复位标志。
 380:Library/src/lcm32f06x_pwr.c ****   * @retval None
 381:Library/src/lcm32f06x_pwr.c ****   */
 382:Library/src/lcm32f06x_pwr.c **** void PWR_LVRClearFlag(void)
 383:Library/src/lcm32f06x_pwr.c **** {
 384:Library/src/lcm32f06x_pwr.c ****   assert_param();
 385:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 386:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 387:Library/src/lcm32f06x_pwr.c ****   __dekey();
 388:Library/src/lcm32f06x_pwr.c **** }
 389:Library/src/lcm32f06x_pwr.c **** /**
 390:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LVRClearFlag
 391:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Clear power on/off reset flag.
 392:Library/src/lcm32f06x_pwr.c ****   *         CN: 清除上电/掉电复位标志。
 393:Library/src/lcm32f06x_pwr.c ****   * @retval None
 394:Library/src/lcm32f06x_pwr.c ****   */
 395:Library/src/lcm32f06x_pwr.c **** void PWR_POR_PDRClearFlag(void)
 396:Library/src/lcm32f06x_pwr.c **** {
 397:Library/src/lcm32f06x_pwr.c ****   assert_param();
 398:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 399:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 400:Library/src/lcm32f06x_pwr.c ****   __dekey();
 401:Library/src/lcm32f06x_pwr.c **** }
 402:Library/src/lcm32f06x_pwr.c **** 
 403:Library/src/lcm32f06x_pwr.c **** /**
 404:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_UltraLowPowerDeepSleep
 405:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enable Ultra low power stop mode.
 406:Library/src/lcm32f06x_pwr.c ****   *         CN: 使能超低功耗停机模式。
 407:Library/src/lcm32f06x_pwr.c ****   * @param NewState: 
 408:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 409:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 410:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 411:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 412:Library/src/lcm32f06x_pwr.c ****   * @retval None
 413:Library/src/lcm32f06x_pwr.c ****   */
 414:Library/src/lcm32f06x_pwr.c **** void PWR_UltraLowPowerDeepSleep(FunctionalState NewState)
 415:Library/src/lcm32f06x_pwr.c **** {
 416:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 417:Library/src/lcm32f06x_pwr.c ****   {
 418:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 419:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 420:Library/src/lcm32f06x_pwr.c ****   }
 421:Library/src/lcm32f06x_pwr.c ****   else
 422:Library/src/lcm32f06x_pwr.c ****   {
 423:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 424:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
ARM GAS  /tmp/cckWj3Ij.s 			page 10


 425:Library/src/lcm32f06x_pwr.c ****   }
 426:Library/src/lcm32f06x_pwr.c ****   __dekey();
 427:Library/src/lcm32f06x_pwr.c **** }
 428:Library/src/lcm32f06x_pwr.c **** 
 429:Library/src/lcm32f06x_pwr.c **** /**
 430:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_FlashPowerDownDeepSleep
 431:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Enter deep power failure mode.
 432:Library/src/lcm32f06x_pwr.c ****   *         CN: flash 进入深度掉电模式 。
 433:Library/src/lcm32f06x_pwr.c ****   * @param NewState: 
 434:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 435:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 436:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 437:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 438:Library/src/lcm32f06x_pwr.c ****   * @retval None
 439:Library/src/lcm32f06x_pwr.c ****   */
 440:Library/src/lcm32f06x_pwr.c **** void PWR_FlashPowerDownDeepSleep(FunctionalState NewState)
 441:Library/src/lcm32f06x_pwr.c **** {
 442:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 443:Library/src/lcm32f06x_pwr.c ****   {
 444:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 445:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 446:Library/src/lcm32f06x_pwr.c ****   }
 447:Library/src/lcm32f06x_pwr.c ****   else
 448:Library/src/lcm32f06x_pwr.c ****   {
 449:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 450:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 451:Library/src/lcm32f06x_pwr.c ****   }
 452:Library/src/lcm32f06x_pwr.c ****   __dekey();
 453:Library/src/lcm32f06x_pwr.c **** }
 454:Library/src/lcm32f06x_pwr.c **** 
 455:Library/src/lcm32f06x_pwr.c **** /**
 456:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LowPowerCmd
 457:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Low power mode enable.
 458:Library/src/lcm32f06x_pwr.c ****   *         CN: 低功耗模式使能 。
 459:Library/src/lcm32f06x_pwr.c ****   * @param NewState: 
 460:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 461:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 462:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 463:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 464:Library/src/lcm32f06x_pwr.c ****   * @retval None
 465:Library/src/lcm32f06x_pwr.c ****   */
 466:Library/src/lcm32f06x_pwr.c **** void PWR_LowPowerCmd(FunctionalState NewState)
  92              		.loc 1 466 6 view .LVU14
  93              	.LBB447:
 467:Library/src/lcm32f06x_pwr.c **** {
 468:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
  94              		.loc 1 468 3 view .LVU15
 469:Library/src/lcm32f06x_pwr.c ****   {
 470:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
  95              		.loc 1 470 5 view .LVU16
  96              	.LBB448:
  97              	.LBI448:
  98              		.file 2 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
ARM GAS  /tmp/cckWj3Ij.s 			page 11


   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
ARM GAS  /tmp/cckWj3Ij.s 			page 12


  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cckWj3Ij.s 			page 13


 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/cckWj3Ij.s 			page 14


 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
ARM GAS  /tmp/cckWj3Ij.s 			page 15


 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
  99              		.loc 2 258 27 view .LVU17
 100              	.LBB449:
 259:Core/cmsis_gcc.h **** {
 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 101              		.loc 2 260 3 view .LVU18
 102              	.LBE449:
 103              	.LBE448:
 104              	.LBE447:
 105              	.LBE446:
  66:Library/src/lcm32f06x_pwr.c ****   /* Check the parameters */
 106              		.loc 1 66 1 is_stmt 0 view .LVU19
 107 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 108              	.LCFI0:
 109              		.cfi_def_cfa_offset 20
 110              		.cfi_offset 4, -20
 111              		.cfi_offset 5, -16
 112              		.cfi_offset 6, -12
 113              		.cfi_offset 7, -8
 114              		.cfi_offset 14, -4
 115              	.LBB459:
 116              	.LBB458:
 117              	.LBB451:
 118              	.LBB450:
 119              		.loc 2 260 3 view .LVU20
 120              		.syntax divided
 121              	@ 260 "Core/cmsis_gcc.h" 1
 122 0002 BFF36F8F 		isb 0xF
 123              	@ 0 "" 2
 124              		.thumb
 125              		.syntax unified
 126              	.LBE450:
ARM GAS  /tmp/cckWj3Ij.s 			page 16


 127              	.LBE451:
 128              		.loc 1 470 5 is_stmt 1 discriminator 1 view .LVU21
 129              	.LBB452:
 130              	.LBI452:
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
ARM GAS  /tmp/cckWj3Ij.s 			page 17


 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
ARM GAS  /tmp/cckWj3Ij.s 			page 18


 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
ARM GAS  /tmp/cckWj3Ij.s 			page 19


 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cckWj3Ij.s 			page 20


 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/cckWj3Ij.s 			page 21


 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
ARM GAS  /tmp/cckWj3Ij.s 			page 22


 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cckWj3Ij.s 			page 23


 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
ARM GAS  /tmp/cckWj3Ij.s 			page 24


 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/cckWj3Ij.s 			page 25


 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
ARM GAS  /tmp/cckWj3Ij.s 			page 26


 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
ARM GAS  /tmp/cckWj3Ij.s 			page 27


 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
ARM GAS  /tmp/cckWj3Ij.s 			page 28


 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 963:Core/cmsis_gcc.h **** }
 964:Core/cmsis_gcc.h **** 
 965:Core/cmsis_gcc.h **** 
 966:Core/cmsis_gcc.h **** /**
 967:Core/cmsis_gcc.h ****   \brief   Get Control Register
 968:Core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 969:Core/cmsis_gcc.h ****   \return               Control Register value
 970:Core/cmsis_gcc.h ****  */
 971:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 972:Core/cmsis_gcc.h **** {
 973:Core/cmsis_gcc.h ****   uint32_t result;
 974:Core/cmsis_gcc.h **** 
 975:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 976:Core/cmsis_gcc.h ****   return(result);
 977:Core/cmsis_gcc.h **** }
 978:Core/cmsis_gcc.h **** 
 979:Core/cmsis_gcc.h **** 
 980:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 981:Core/cmsis_gcc.h **** /**
 982:Core/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 983:Core/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 984:Core/cmsis_gcc.h ****   \return               non-secure Control Register value
 985:Core/cmsis_gcc.h ****  */
 986:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 987:Core/cmsis_gcc.h **** {
 988:Core/cmsis_gcc.h ****   uint32_t result;
 989:Core/cmsis_gcc.h **** 
 990:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 991:Core/cmsis_gcc.h ****   return(result);
 992:Core/cmsis_gcc.h **** }
 993:Core/cmsis_gcc.h **** #endif
 994:Core/cmsis_gcc.h **** 
 995:Core/cmsis_gcc.h **** 
 996:Core/cmsis_gcc.h **** /**
 997:Core/cmsis_gcc.h ****   \brief   Set Control Register
ARM GAS  /tmp/cckWj3Ij.s 			page 29


 998:Core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 999:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1000:Core/cmsis_gcc.h ****  */
1001:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1002:Core/cmsis_gcc.h **** {
1003:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1004:Core/cmsis_gcc.h ****   __ISB();
1005:Core/cmsis_gcc.h **** }
1006:Core/cmsis_gcc.h **** 
1007:Core/cmsis_gcc.h **** 
1008:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1009:Core/cmsis_gcc.h **** /**
1010:Core/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
1011:Core/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
1012:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1013:Core/cmsis_gcc.h ****  */
1014:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1015:Core/cmsis_gcc.h **** {
1016:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1017:Core/cmsis_gcc.h ****   __ISB();
1018:Core/cmsis_gcc.h **** }
1019:Core/cmsis_gcc.h **** #endif
1020:Core/cmsis_gcc.h **** 
1021:Core/cmsis_gcc.h **** 
1022:Core/cmsis_gcc.h **** /**
1023:Core/cmsis_gcc.h ****   \brief   Get IPSR Register
1024:Core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
1025:Core/cmsis_gcc.h ****   \return               IPSR Register value
1026:Core/cmsis_gcc.h ****  */
1027:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1028:Core/cmsis_gcc.h **** {
1029:Core/cmsis_gcc.h ****   uint32_t result;
1030:Core/cmsis_gcc.h **** 
1031:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1032:Core/cmsis_gcc.h ****   return(result);
1033:Core/cmsis_gcc.h **** }
1034:Core/cmsis_gcc.h **** 
1035:Core/cmsis_gcc.h **** 
1036:Core/cmsis_gcc.h **** /**
1037:Core/cmsis_gcc.h ****   \brief   Get APSR Register
1038:Core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
1039:Core/cmsis_gcc.h ****   \return               APSR Register value
1040:Core/cmsis_gcc.h ****  */
1041:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1042:Core/cmsis_gcc.h **** {
1043:Core/cmsis_gcc.h ****   uint32_t result;
1044:Core/cmsis_gcc.h **** 
1045:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
1046:Core/cmsis_gcc.h ****   return(result);
1047:Core/cmsis_gcc.h **** }
1048:Core/cmsis_gcc.h **** 
1049:Core/cmsis_gcc.h **** 
1050:Core/cmsis_gcc.h **** /**
1051:Core/cmsis_gcc.h ****   \brief   Get xPSR Register
1052:Core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
1053:Core/cmsis_gcc.h ****   \return               xPSR Register value
1054:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/cckWj3Ij.s 			page 30


1055:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1056:Core/cmsis_gcc.h **** {
1057:Core/cmsis_gcc.h ****   uint32_t result;
1058:Core/cmsis_gcc.h **** 
1059:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1060:Core/cmsis_gcc.h ****   return(result);
1061:Core/cmsis_gcc.h **** }
1062:Core/cmsis_gcc.h **** 
1063:Core/cmsis_gcc.h **** 
1064:Core/cmsis_gcc.h **** /**
1065:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
1066:Core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
1067:Core/cmsis_gcc.h ****   \return               PSP Register value
1068:Core/cmsis_gcc.h ****  */
1069:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1070:Core/cmsis_gcc.h **** {
1071:Core/cmsis_gcc.h ****   uint32_t result;
1072:Core/cmsis_gcc.h **** 
1073:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
1074:Core/cmsis_gcc.h ****   return(result);
1075:Core/cmsis_gcc.h **** }
1076:Core/cmsis_gcc.h **** 
1077:Core/cmsis_gcc.h **** 
1078:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1079:Core/cmsis_gcc.h **** /**
1080:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
1081:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
1082:Core/cmsis_gcc.h ****   \return               PSP Register value
1083:Core/cmsis_gcc.h ****  */
1084:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1085:Core/cmsis_gcc.h **** {
1086:Core/cmsis_gcc.h ****   uint32_t result;
1087:Core/cmsis_gcc.h **** 
1088:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
1089:Core/cmsis_gcc.h ****   return(result);
1090:Core/cmsis_gcc.h **** }
1091:Core/cmsis_gcc.h **** #endif
1092:Core/cmsis_gcc.h **** 
1093:Core/cmsis_gcc.h **** 
1094:Core/cmsis_gcc.h **** /**
1095:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
1096:Core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
1097:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1098:Core/cmsis_gcc.h ****  */
1099:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1100:Core/cmsis_gcc.h **** {
1101:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1102:Core/cmsis_gcc.h **** }
1103:Core/cmsis_gcc.h **** 
1104:Core/cmsis_gcc.h **** 
1105:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1106:Core/cmsis_gcc.h **** /**
1107:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
1108:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
1109:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1110:Core/cmsis_gcc.h ****  */
1111:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
ARM GAS  /tmp/cckWj3Ij.s 			page 31


1112:Core/cmsis_gcc.h **** {
1113:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1114:Core/cmsis_gcc.h **** }
1115:Core/cmsis_gcc.h **** #endif
1116:Core/cmsis_gcc.h **** 
1117:Core/cmsis_gcc.h **** 
1118:Core/cmsis_gcc.h **** /**
1119:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
1120:Core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
1121:Core/cmsis_gcc.h ****   \return               MSP Register value
1122:Core/cmsis_gcc.h ****  */
1123:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1124:Core/cmsis_gcc.h **** {
1125:Core/cmsis_gcc.h ****   uint32_t result;
1126:Core/cmsis_gcc.h **** 
1127:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
1128:Core/cmsis_gcc.h ****   return(result);
1129:Core/cmsis_gcc.h **** }
1130:Core/cmsis_gcc.h **** 
1131:Core/cmsis_gcc.h **** 
1132:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1133:Core/cmsis_gcc.h **** /**
1134:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
1135:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
1136:Core/cmsis_gcc.h ****   \return               MSP Register value
1137:Core/cmsis_gcc.h ****  */
1138:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1139:Core/cmsis_gcc.h **** {
1140:Core/cmsis_gcc.h ****   uint32_t result;
1141:Core/cmsis_gcc.h **** 
1142:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1143:Core/cmsis_gcc.h ****   return(result);
1144:Core/cmsis_gcc.h **** }
1145:Core/cmsis_gcc.h **** #endif
1146:Core/cmsis_gcc.h **** 
1147:Core/cmsis_gcc.h **** 
1148:Core/cmsis_gcc.h **** /**
1149:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
1150:Core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
1151:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1152:Core/cmsis_gcc.h ****  */
1153:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1154:Core/cmsis_gcc.h **** {
1155:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1156:Core/cmsis_gcc.h **** }
1157:Core/cmsis_gcc.h **** 
1158:Core/cmsis_gcc.h **** 
1159:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1160:Core/cmsis_gcc.h **** /**
1161:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
1162:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1163:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1164:Core/cmsis_gcc.h ****  */
1165:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1166:Core/cmsis_gcc.h **** {
1167:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1168:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 32


1169:Core/cmsis_gcc.h **** #endif
1170:Core/cmsis_gcc.h **** 
1171:Core/cmsis_gcc.h **** 
1172:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1173:Core/cmsis_gcc.h **** /**
1174:Core/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
1175:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1176:Core/cmsis_gcc.h ****   \return               SP Register value
1177:Core/cmsis_gcc.h ****  */
1178:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1179:Core/cmsis_gcc.h **** {
1180:Core/cmsis_gcc.h ****   uint32_t result;
1181:Core/cmsis_gcc.h **** 
1182:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1183:Core/cmsis_gcc.h ****   return(result);
1184:Core/cmsis_gcc.h **** }
1185:Core/cmsis_gcc.h **** 
1186:Core/cmsis_gcc.h **** 
1187:Core/cmsis_gcc.h **** /**
1188:Core/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
1189:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1190:Core/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
1191:Core/cmsis_gcc.h ****  */
1192:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1193:Core/cmsis_gcc.h **** {
1194:Core/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1195:Core/cmsis_gcc.h **** }
1196:Core/cmsis_gcc.h **** #endif
1197:Core/cmsis_gcc.h **** 
1198:Core/cmsis_gcc.h **** 
1199:Core/cmsis_gcc.h **** /**
1200:Core/cmsis_gcc.h ****   \brief   Get Priority Mask
1201:Core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202:Core/cmsis_gcc.h ****   \return               Priority Mask value
1203:Core/cmsis_gcc.h ****  */
1204:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 131              		.loc 2 1204 31 view .LVU22
 132              	.LBB453:
1205:Core/cmsis_gcc.h **** {
1206:Core/cmsis_gcc.h ****   uint32_t result;
 133              		.loc 2 1206 3 view .LVU23
1207:Core/cmsis_gcc.h **** 
1208:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
 134              		.loc 2 1208 3 view .LVU24
 135              		.syntax divided
 136              	@ 1208 "Core/cmsis_gcc.h" 1
 137 0006 EFF31083 		MRS r3, primask
 138              	@ 0 "" 2
 139              	.LVL2:
1209:Core/cmsis_gcc.h ****   return(result);
 140              		.loc 2 1209 3 view .LVU25
 141              		.loc 2 1209 3 is_stmt 0 view .LVU26
 142              		.thumb
 143              		.syntax unified
 144              	.LBE453:
 145              	.LBE452:
 146              		.loc 1 470 5 is_stmt 1 discriminator 2 view .LVU27
ARM GAS  /tmp/cckWj3Ij.s 			page 33


 147              	.LBB454:
 148              	.LBI454:
 960:Core/cmsis_gcc.h **** {
 149              		.loc 2 960 27 view .LVU28
 150              	.LBB455:
 962:Core/cmsis_gcc.h **** }
 151              		.loc 2 962 3 view .LVU29
 152              		.syntax divided
 153              	@ 962 "Core/cmsis_gcc.h" 1
 154 000a 72B6     		cpsid i
 155              	@ 0 "" 2
 156              		.thumb
 157              		.syntax unified
 158              	.LBE455:
 159              	.LBE454:
 160              		.loc 1 470 5 discriminator 3 view .LVU30
 471:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 161              		.loc 1 471 30 is_stmt 0 view .LVU31
 162 000c 3023     		movs	r3, #48
 163 000e 0427     		movs	r7, #4
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 164              		.loc 1 470 5 discriminator 3 view .LVU32
 165 0010 1C49     		ldr	r1, .L12
 166 0012 1D4C     		ldr	r4, .L12+4
 167              		.loc 1 471 30 view .LVU33
 168 0014 1D4A     		ldr	r2, .L12+8
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 169              		.loc 1 470 5 discriminator 3 view .LVU34
 170 0016 0C60     		str	r4, [r1]
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 171              		.loc 1 470 22 is_stmt 1 discriminator 3 view .LVU35
 172              		.loc 1 471 5 view .LVU36
 173              		.loc 1 471 30 is_stmt 0 view .LVU37
 174 0018 D55C     		ldrb	r5, [r2, r3]
 175 001a 0426     		movs	r6, #4
 176 001c 3D43     		orrs	r5, r7
 177 001e D554     		strb	r5, [r2, r3]
 472:Library/src/lcm32f06x_pwr.c ****   }
 473:Library/src/lcm32f06x_pwr.c ****   else
 474:Library/src/lcm32f06x_pwr.c ****   {
 475:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 476:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 477:Library/src/lcm32f06x_pwr.c ****   }
 478:Library/src/lcm32f06x_pwr.c ****   __dekey();
 178              		.loc 1 478 3 is_stmt 1 view .LVU38
 179              	.LBB456:
 180              	.LBI456:
 949:Core/cmsis_gcc.h **** {
 181              		.loc 2 949 27 view .LVU39
 182              	.LBB457:
 951:Core/cmsis_gcc.h **** }
 183              		.loc 2 951 3 view .LVU40
 184              		.syntax divided
 185              	@ 951 "Core/cmsis_gcc.h" 1
 186 0020 62B6     		cpsie i
 187              	@ 0 "" 2
 188              		.thumb
ARM GAS  /tmp/cckWj3Ij.s 			page 34


 189              		.syntax unified
 190              	.LBE457:
 191              	.LBE456:
 192              		.loc 1 478 12 discriminator 1 view .LVU41
 193              	.LVL3:
 194              		.loc 1 478 12 is_stmt 0 discriminator 1 view .LVU42
 195              	.LBE458:
 196              	.LBE459:
  72:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(ENABLE);        // LPDS  内核LDO  /kernel LDO
 197              		.loc 1 72 3 is_stmt 1 view .LVU43
 198              	.LBB460:
 199              	.LBI460:
 440:Library/src/lcm32f06x_pwr.c **** {
 200              		.loc 1 440 6 view .LVU44
 201              	.LBB461:
 442:Library/src/lcm32f06x_pwr.c ****   {
 202              		.loc 1 442 3 view .LVU45
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 203              		.loc 1 444 5 view .LVU46
 204              	.LBB462:
 205              	.LBI462:
 258:Core/cmsis_gcc.h **** {
 206              		.loc 2 258 27 view .LVU47
 207              	.LBB463:
 260:Core/cmsis_gcc.h **** }
 208              		.loc 2 260 3 view .LVU48
 209              		.syntax divided
 210              	@ 260 "Core/cmsis_gcc.h" 1
 211 0022 BFF36F8F 		isb 0xF
 212              	@ 0 "" 2
 213              		.thumb
 214              		.syntax unified
 215              	.LBE463:
 216              	.LBE462:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 217              		.loc 1 444 5 discriminator 1 view .LVU49
 218              	.LBB464:
 219              	.LBI464:
1204:Core/cmsis_gcc.h **** {
 220              		.loc 2 1204 31 view .LVU50
 221              	.LBB465:
1206:Core/cmsis_gcc.h **** 
 222              		.loc 2 1206 3 view .LVU51
1208:Core/cmsis_gcc.h ****   return(result);
 223              		.loc 2 1208 3 view .LVU52
 224              		.syntax divided
 225              	@ 1208 "Core/cmsis_gcc.h" 1
 226 0026 EFF31085 		MRS r5, primask
 227              	@ 0 "" 2
 228              	.LVL4:
 229              		.loc 2 1209 3 view .LVU53
 230              		.loc 2 1209 3 is_stmt 0 view .LVU54
 231              		.thumb
 232              		.syntax unified
 233              	.LBE465:
 234              	.LBE464:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
ARM GAS  /tmp/cckWj3Ij.s 			page 35


 235              		.loc 1 444 5 is_stmt 1 discriminator 2 view .LVU55
 236              	.LBB466:
 237              	.LBI466:
 960:Core/cmsis_gcc.h **** {
 238              		.loc 2 960 27 view .LVU56
 239              	.LBB467:
 962:Core/cmsis_gcc.h **** }
 240              		.loc 2 962 3 view .LVU57
 241              		.syntax divided
 242              	@ 962 "Core/cmsis_gcc.h" 1
 243 002a 72B6     		cpsid i
 244              	@ 0 "" 2
 245              		.thumb
 246              		.syntax unified
 247              	.LBE467:
 248              	.LBE466:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 249              		.loc 1 444 5 discriminator 3 view .LVU58
 445:Library/src/lcm32f06x_pwr.c ****   }
 250              		.loc 1 445 29 is_stmt 0 view .LVU59
 251 002c 0827     		movs	r7, #8
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 252              		.loc 1 444 5 discriminator 3 view .LVU60
 253 002e 0C60     		str	r4, [r1]
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 254              		.loc 1 444 22 is_stmt 1 discriminator 3 view .LVU61
 445:Library/src/lcm32f06x_pwr.c ****   }
 255              		.loc 1 445 5 view .LVU62
 445:Library/src/lcm32f06x_pwr.c ****   }
 256              		.loc 1 445 29 is_stmt 0 view .LVU63
 257 0030 D55C     		ldrb	r5, [r2, r3]
 258 0032 3D43     		orrs	r5, r7
 259 0034 D554     		strb	r5, [r2, r3]
 452:Library/src/lcm32f06x_pwr.c **** }
 260              		.loc 1 452 3 is_stmt 1 view .LVU64
 261              	.LBB468:
 262              	.LBI468:
 949:Core/cmsis_gcc.h **** {
 263              		.loc 2 949 27 view .LVU65
 264              	.LBB469:
 951:Core/cmsis_gcc.h **** }
 265              		.loc 2 951 3 view .LVU66
 266              		.syntax divided
 267              	@ 951 "Core/cmsis_gcc.h" 1
 268 0036 62B6     		cpsie i
 269              	@ 0 "" 2
 270              		.thumb
 271              		.syntax unified
 272              	.LBE469:
 273              	.LBE468:
 452:Library/src/lcm32f06x_pwr.c **** }
 274              		.loc 1 452 12 discriminator 1 view .LVU67
 275              	.LVL5:
 452:Library/src/lcm32f06x_pwr.c **** }
 276              		.loc 1 452 12 is_stmt 0 discriminator 1 view .LVU68
 277              	.LBE461:
 278              	.LBE460:
ARM GAS  /tmp/cckWj3Ij.s 			page 36


  73:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(ENABLE);   // ULPDS  使能超低功耗 /Enable ultra-low power consumption
 279              		.loc 1 73 3 is_stmt 1 view .LVU69
 280              	.LBB470:
 281              	.LBI470:
 479:Library/src/lcm32f06x_pwr.c **** }
 480:Library/src/lcm32f06x_pwr.c **** 
 481:Library/src/lcm32f06x_pwr.c **** /**
 482:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LowPowerDeepSleep
 483:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: In stop mode, the kernel LDO is in low-power mode.
 484:Library/src/lcm32f06x_pwr.c ****   *         CN: 停机模式下，内核 LDO 处于低功耗模式模式。
 485:Library/src/lcm32f06x_pwr.c ****   * @param  NewState: 
 486:Library/src/lcm32f06x_pwr.c ****   *         EN: new state.
 487:Library/src/lcm32f06x_pwr.c ****   *         CN: 新状态。
 488:Library/src/lcm32f06x_pwr.c ****   *             @arg ENABLE
 489:Library/src/lcm32f06x_pwr.c ****   *             @arg DISABLE
 490:Library/src/lcm32f06x_pwr.c ****   * @retval None
 491:Library/src/lcm32f06x_pwr.c ****   */
 492:Library/src/lcm32f06x_pwr.c **** void PWR_LowPowerDeepSleep(FunctionalState NewState)
 282              		.loc 1 492 6 view .LVU70
 283              	.LBB471:
 493:Library/src/lcm32f06x_pwr.c **** {
 494:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 284              		.loc 1 494 3 view .LVU71
 495:Library/src/lcm32f06x_pwr.c ****   {
 496:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 285              		.loc 1 496 5 view .LVU72
 286              	.LBB472:
 287              	.LBI472:
 258:Core/cmsis_gcc.h **** {
 288              		.loc 2 258 27 view .LVU73
 289              	.LBB473:
 260:Core/cmsis_gcc.h **** }
 290              		.loc 2 260 3 view .LVU74
 291              		.syntax divided
 292              	@ 260 "Core/cmsis_gcc.h" 1
 293 0038 BFF36F8F 		isb 0xF
 294              	@ 0 "" 2
 295              		.thumb
 296              		.syntax unified
 297              	.LBE473:
 298              	.LBE472:
 299              		.loc 1 496 5 discriminator 1 view .LVU75
 300              	.LBB474:
 301              	.LBI474:
1204:Core/cmsis_gcc.h **** {
 302              		.loc 2 1204 31 view .LVU76
 303              	.LBB475:
1206:Core/cmsis_gcc.h **** 
 304              		.loc 2 1206 3 view .LVU77
1208:Core/cmsis_gcc.h ****   return(result);
 305              		.loc 2 1208 3 view .LVU78
 306              		.syntax divided
 307              	@ 1208 "Core/cmsis_gcc.h" 1
 308 003c EFF31085 		MRS r5, primask
 309              	@ 0 "" 2
 310              	.LVL6:
 311              		.loc 2 1209 3 view .LVU79
ARM GAS  /tmp/cckWj3Ij.s 			page 37


 312              		.loc 2 1209 3 is_stmt 0 view .LVU80
 313              		.thumb
 314              		.syntax unified
 315              	.LBE475:
 316              	.LBE474:
 317              		.loc 1 496 5 is_stmt 1 discriminator 2 view .LVU81
 318              	.LBB476:
 319              	.LBI476:
 960:Core/cmsis_gcc.h **** {
 320              		.loc 2 960 27 view .LVU82
 321              	.LBB477:
 962:Core/cmsis_gcc.h **** }
 322              		.loc 2 962 3 view .LVU83
 323              		.syntax divided
 324              	@ 962 "Core/cmsis_gcc.h" 1
 325 0040 72B6     		cpsid i
 326              	@ 0 "" 2
 327              		.thumb
 328              		.syntax unified
 329              	.LBE477:
 330              	.LBE476:
 331              		.loc 1 496 5 discriminator 3 view .LVU84
 497:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 332              		.loc 1 497 29 is_stmt 0 view .LVU85
 333 0042 0127     		movs	r7, #1
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 334              		.loc 1 496 5 discriminator 3 view .LVU86
 335 0044 0C60     		str	r4, [r1]
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 336              		.loc 1 496 22 is_stmt 1 discriminator 3 view .LVU87
 337              		.loc 1 497 5 view .LVU88
 338              		.loc 1 497 29 is_stmt 0 view .LVU89
 339 0046 D55C     		ldrb	r5, [r2, r3]
 340 0048 3D43     		orrs	r5, r7
 341 004a D554     		strb	r5, [r2, r3]
 498:Library/src/lcm32f06x_pwr.c ****   }
 499:Library/src/lcm32f06x_pwr.c ****   else
 500:Library/src/lcm32f06x_pwr.c ****   {
 501:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 502:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 503:Library/src/lcm32f06x_pwr.c ****   }
 504:Library/src/lcm32f06x_pwr.c ****   __dekey();
 342              		.loc 1 504 3 is_stmt 1 view .LVU90
 343              	.LBB478:
 344              	.LBI478:
 949:Core/cmsis_gcc.h **** {
 345              		.loc 2 949 27 view .LVU91
 346              	.LBB479:
 951:Core/cmsis_gcc.h **** }
 347              		.loc 2 951 3 view .LVU92
 348              		.syntax divided
 349              	@ 951 "Core/cmsis_gcc.h" 1
 350 004c 62B6     		cpsie i
 351              	@ 0 "" 2
 352              		.thumb
 353              		.syntax unified
 354              	.LBE479:
ARM GAS  /tmp/cckWj3Ij.s 			page 38


 355              	.LBE478:
 356              		.loc 1 504 12 discriminator 1 view .LVU93
 357              	.LVL7:
 358              		.loc 1 504 12 is_stmt 0 discriminator 1 view .LVU94
 359              	.LBE471:
 360              	.LBE470:
  74:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 361              		.loc 1 74 3 is_stmt 1 view .LVU95
 362              	.LBB480:
 363              	.LBI480:
 414:Library/src/lcm32f06x_pwr.c **** {
 364              		.loc 1 414 6 view .LVU96
 365              	.LBB481:
 416:Library/src/lcm32f06x_pwr.c ****   {
 366              		.loc 1 416 3 view .LVU97
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 367              		.loc 1 418 5 view .LVU98
 368              	.LBB482:
 369              	.LBI482:
 258:Core/cmsis_gcc.h **** {
 370              		.loc 2 258 27 view .LVU99
 371              	.LBB483:
 260:Core/cmsis_gcc.h **** }
 372              		.loc 2 260 3 view .LVU100
 373              		.syntax divided
 374              	@ 260 "Core/cmsis_gcc.h" 1
 375 004e BFF36F8F 		isb 0xF
 376              	@ 0 "" 2
 377              		.thumb
 378              		.syntax unified
 379              	.LBE483:
 380              	.LBE482:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 381              		.loc 1 418 5 discriminator 1 view .LVU101
 382              	.LBB484:
 383              	.LBI484:
1204:Core/cmsis_gcc.h **** {
 384              		.loc 2 1204 31 view .LVU102
 385              	.LBB485:
1206:Core/cmsis_gcc.h **** 
 386              		.loc 2 1206 3 view .LVU103
1208:Core/cmsis_gcc.h ****   return(result);
 387              		.loc 2 1208 3 view .LVU104
 388              		.syntax divided
 389              	@ 1208 "Core/cmsis_gcc.h" 1
 390 0052 EFF31085 		MRS r5, primask
 391              	@ 0 "" 2
 392              	.LVL8:
 393              		.loc 2 1209 3 view .LVU105
 394              		.loc 2 1209 3 is_stmt 0 view .LVU106
 395              		.thumb
 396              		.syntax unified
 397              	.LBE485:
 398              	.LBE484:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 399              		.loc 1 418 5 is_stmt 1 discriminator 2 view .LVU107
 400              	.LBB486:
ARM GAS  /tmp/cckWj3Ij.s 			page 39


 401              	.LBI486:
 960:Core/cmsis_gcc.h **** {
 402              		.loc 2 960 27 view .LVU108
 403              	.LBB487:
 962:Core/cmsis_gcc.h **** }
 404              		.loc 2 962 3 view .LVU109
 405              		.syntax divided
 406              	@ 962 "Core/cmsis_gcc.h" 1
 407 0056 72B6     		cpsid i
 408              	@ 0 "" 2
 409              		.thumb
 410              		.syntax unified
 411              	.LBE487:
 412              	.LBE486:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 413              		.loc 1 418 5 discriminator 3 view .LVU110
 414 0058 0C60     		str	r4, [r1]
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 415              		.loc 1 418 22 discriminator 3 view .LVU111
 419:Library/src/lcm32f06x_pwr.c ****   }
 416              		.loc 1 419 5 view .LVU112
 419:Library/src/lcm32f06x_pwr.c ****   }
 417              		.loc 1 419 30 is_stmt 0 view .LVU113
 418 005a 1024     		movs	r4, #16
 419 005c D15C     		ldrb	r1, [r2, r3]
 420 005e 2143     		orrs	r1, r4
 421 0060 D154     		strb	r1, [r2, r3]
 426:Library/src/lcm32f06x_pwr.c **** }
 422              		.loc 1 426 3 is_stmt 1 view .LVU114
 423              	.LBB488:
 424              	.LBI488:
 949:Core/cmsis_gcc.h **** {
 425              		.loc 2 949 27 view .LVU115
 426              	.LBB489:
 951:Core/cmsis_gcc.h **** }
 427              		.loc 2 951 3 view .LVU116
 428              		.syntax divided
 429              	@ 951 "Core/cmsis_gcc.h" 1
 430 0062 62B6     		cpsie i
 431              	@ 0 "" 2
 432              		.thumb
 433              		.syntax unified
 434              	.LBE489:
 435              	.LBE488:
 426:Library/src/lcm32f06x_pwr.c **** }
 436              		.loc 1 426 12 discriminator 1 view .LVU117
 437              	.LVL9:
 426:Library/src/lcm32f06x_pwr.c **** }
 438              		.loc 1 426 12 is_stmt 0 discriminator 1 view .LVU118
 439              	.LBE481:
 440              	.LBE480:
  77:Library/src/lcm32f06x_pwr.c **** 
 441              		.loc 1 77 3 is_stmt 1 view .LVU119
  77:Library/src/lcm32f06x_pwr.c **** 
 442              		.loc 1 77 6 is_stmt 0 view .LVU120
 443 0064 0A4B     		ldr	r3, .L12+12
 444 0066 1A69     		ldr	r2, [r3, #16]
ARM GAS  /tmp/cckWj3Ij.s 			page 40


  77:Library/src/lcm32f06x_pwr.c **** 
 445              		.loc 1 77 12 view .LVU121
 446 0068 3243     		orrs	r2, r6
 447 006a 1A61     		str	r2, [r3, #16]
  79:Library/src/lcm32f06x_pwr.c ****   {
 448              		.loc 1 79 3 is_stmt 1 view .LVU122
  79:Library/src/lcm32f06x_pwr.c ****   {
 449              		.loc 1 79 6 is_stmt 0 view .LVU123
 450 006c 0128     		cmp	r0, #1
 451 006e 04D0     		beq	.L11
  88:Library/src/lcm32f06x_pwr.c ****     SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 452              		.loc 1 88 5 is_stmt 1 view .LVU124
 453              		.syntax divided
 454              	@ 88 "Library/src/lcm32f06x_pwr.c" 1
 455 0070 20BF     		wfe
 456              	@ 0 "" 2
  89:Library/src/lcm32f06x_pwr.c ****   }
 457              		.loc 1 89 5 view .LVU125
  89:Library/src/lcm32f06x_pwr.c ****   }
 458              		.loc 1 89 8 is_stmt 0 view .LVU126
 459              		.thumb
 460              		.syntax unified
 461 0072 1A69     		ldr	r2, [r3, #16]
  89:Library/src/lcm32f06x_pwr.c ****   }
 462              		.loc 1 89 14 view .LVU127
 463 0074 B243     		bics	r2, r6
 464 0076 1A61     		str	r2, [r3, #16]
 465              	.L8:
  93:Library/src/lcm32f06x_pwr.c **** 
 466              		.loc 1 93 1 view .LVU128
 467              		@ sp needed
 468 0078 F0BD     		pop	{r4, r5, r6, r7, pc}
 469              	.L11:
  82:Library/src/lcm32f06x_pwr.c ****     SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 470              		.loc 1 82 5 is_stmt 1 view .LVU129
 471              		.syntax divided
 472              	@ 82 "Library/src/lcm32f06x_pwr.c" 1
 473 007a 30BF     		wfi
 474              	@ 0 "" 2
  83:Library/src/lcm32f06x_pwr.c ****   }
 475              		.loc 1 83 5 view .LVU130
  83:Library/src/lcm32f06x_pwr.c ****   }
 476              		.loc 1 83 8 is_stmt 0 view .LVU131
 477              		.thumb
 478              		.syntax unified
 479 007c 1A69     		ldr	r2, [r3, #16]
  83:Library/src/lcm32f06x_pwr.c ****   }
 480              		.loc 1 83 14 view .LVU132
 481 007e B243     		bics	r2, r6
 482 0080 1A61     		str	r2, [r3, #16]
 483 0082 F9E7     		b	.L8
 484              	.L13:
 485              		.align	2
 486              	.L12:
 487 0084 20700140 		.word	1073836064
 488 0088 65432187 		.word	-2027863195
 489 008c 00700140 		.word	1073836032
ARM GAS  /tmp/cckWj3Ij.s 			page 41


 490 0090 00ED00E0 		.word	-536810240
 491              		.cfi_endproc
 492              	.LFE46:
 494              		.section	.text.PWR_EnterSTOPMode,"ax",%progbits
 495              		.align	1
 496              		.p2align 2,,3
 497              		.global	PWR_EnterSTOPMode
 498              		.syntax unified
 499              		.code	16
 500              		.thumb_func
 502              	PWR_EnterSTOPMode:
 503              	.LVL10:
 504              	.LFB47:
 107:Library/src/lcm32f06x_pwr.c **** 
 505              		.loc 1 107 1 is_stmt 1 view -0
 506              		.cfi_startproc
 507              		@ args = 0, pretend = 0, frame = 0
 508              		@ frame_needed = 0, uses_anonymous_args = 0
 109:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);
 509              		.loc 1 109 3 view .LVU134
 510              	.LBB490:
 511              	.LBI490:
 466:Library/src/lcm32f06x_pwr.c **** {
 512              		.loc 1 466 6 view .LVU135
 513              	.LBB491:
 468:Library/src/lcm32f06x_pwr.c ****   {
 514              		.loc 1 468 3 view .LVU136
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 515              		.loc 1 470 5 view .LVU137
 516              	.LBB492:
 517              	.LBI492:
 258:Core/cmsis_gcc.h **** {
 518              		.loc 2 258 27 view .LVU138
 519              	.LBB493:
 260:Core/cmsis_gcc.h **** }
 520              		.loc 2 260 3 view .LVU139
 521              	.LBE493:
 522              	.LBE492:
 523              	.LBE491:
 524              	.LBE490:
 107:Library/src/lcm32f06x_pwr.c **** 
 525              		.loc 1 107 1 is_stmt 0 view .LVU140
 526 0000 70B5     		push	{r4, r5, r6, lr}
 527              	.LCFI1:
 528              		.cfi_def_cfa_offset 16
 529              		.cfi_offset 4, -16
 530              		.cfi_offset 5, -12
 531              		.cfi_offset 6, -8
 532              		.cfi_offset 14, -4
 533              	.LBB503:
 534              	.LBB502:
 535              	.LBB495:
 536              	.LBB494:
 260:Core/cmsis_gcc.h **** }
 537              		.loc 2 260 3 view .LVU141
 538              		.syntax divided
 539              	@ 260 "Core/cmsis_gcc.h" 1
ARM GAS  /tmp/cckWj3Ij.s 			page 42


 540 0002 BFF36F8F 		isb 0xF
 541              	@ 0 "" 2
 542              		.thumb
 543              		.syntax unified
 544              	.LBE494:
 545              	.LBE495:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 546              		.loc 1 470 5 is_stmt 1 discriminator 1 view .LVU142
 547              	.LBB496:
 548              	.LBI496:
1204:Core/cmsis_gcc.h **** {
 549              		.loc 2 1204 31 view .LVU143
 550              	.LBB497:
1206:Core/cmsis_gcc.h **** 
 551              		.loc 2 1206 3 view .LVU144
1208:Core/cmsis_gcc.h ****   return(result);
 552              		.loc 2 1208 3 view .LVU145
 553              		.syntax divided
 554              	@ 1208 "Core/cmsis_gcc.h" 1
 555 0006 EFF31083 		MRS r3, primask
 556              	@ 0 "" 2
 557              	.LVL11:
 558              		.loc 2 1209 3 view .LVU146
 559              		.loc 2 1209 3 is_stmt 0 view .LVU147
 560              		.thumb
 561              		.syntax unified
 562              	.LBE497:
 563              	.LBE496:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 564              		.loc 1 470 5 is_stmt 1 discriminator 2 view .LVU148
 565              	.LBB498:
 566              	.LBI498:
 960:Core/cmsis_gcc.h **** {
 567              		.loc 2 960 27 view .LVU149
 568              	.LBB499:
 962:Core/cmsis_gcc.h **** }
 569              		.loc 2 962 3 view .LVU150
 570              		.syntax divided
 571              	@ 962 "Core/cmsis_gcc.h" 1
 572 000a 72B6     		cpsid i
 573              	@ 0 "" 2
 574              		.thumb
 575              		.syntax unified
 576              	.LBE499:
 577              	.LBE498:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 578              		.loc 1 470 5 discriminator 3 view .LVU151
 471:Library/src/lcm32f06x_pwr.c ****   }
 579              		.loc 1 471 30 is_stmt 0 view .LVU152
 580 000c 3023     		movs	r3, #48
 581 000e 0426     		movs	r6, #4
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 582              		.loc 1 470 5 discriminator 3 view .LVU153
 583 0010 1C49     		ldr	r1, .L18
 584 0012 1D4C     		ldr	r4, .L18+4
 471:Library/src/lcm32f06x_pwr.c ****   }
 585              		.loc 1 471 30 view .LVU154
ARM GAS  /tmp/cckWj3Ij.s 			page 43


 586 0014 1D4A     		ldr	r2, .L18+8
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 587              		.loc 1 470 5 discriminator 3 view .LVU155
 588 0016 0C60     		str	r4, [r1]
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 589              		.loc 1 470 22 is_stmt 1 discriminator 3 view .LVU156
 471:Library/src/lcm32f06x_pwr.c ****   }
 590              		.loc 1 471 5 view .LVU157
 471:Library/src/lcm32f06x_pwr.c ****   }
 591              		.loc 1 471 30 is_stmt 0 view .LVU158
 592 0018 D55C     		ldrb	r5, [r2, r3]
 593 001a 3543     		orrs	r5, r6
 594 001c D554     		strb	r5, [r2, r3]
 478:Library/src/lcm32f06x_pwr.c **** }
 595              		.loc 1 478 3 is_stmt 1 view .LVU159
 596              	.LBB500:
 597              	.LBI500:
 949:Core/cmsis_gcc.h **** {
 598              		.loc 2 949 27 view .LVU160
 599              	.LBB501:
 951:Core/cmsis_gcc.h **** }
 600              		.loc 2 951 3 view .LVU161
 601              		.syntax divided
 602              	@ 951 "Core/cmsis_gcc.h" 1
 603 001e 62B6     		cpsie i
 604              	@ 0 "" 2
 605              		.thumb
 606              		.syntax unified
 607              	.LBE501:
 608              	.LBE500:
 478:Library/src/lcm32f06x_pwr.c **** }
 609              		.loc 1 478 12 discriminator 1 view .LVU162
 610              	.LVL12:
 478:Library/src/lcm32f06x_pwr.c **** }
 611              		.loc 1 478 12 is_stmt 0 discriminator 1 view .LVU163
 612              	.LBE502:
 613              	.LBE503:
 110:Library/src/lcm32f06x_pwr.c ****   //	PWR_PowerDownDeepSleep(DISABLE);
 614              		.loc 1 110 3 is_stmt 1 view .LVU164
 615              	.LBB504:
 616              	.LBI504:
 440:Library/src/lcm32f06x_pwr.c **** {
 617              		.loc 1 440 6 view .LVU165
 618              	.LBB505:
 442:Library/src/lcm32f06x_pwr.c ****   {
 619              		.loc 1 442 3 view .LVU166
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 620              		.loc 1 444 5 view .LVU167
 621              	.LBB506:
 622              	.LBI506:
 258:Core/cmsis_gcc.h **** {
 623              		.loc 2 258 27 view .LVU168
 624              	.LBB507:
 260:Core/cmsis_gcc.h **** }
 625              		.loc 2 260 3 view .LVU169
 626              		.syntax divided
 627              	@ 260 "Core/cmsis_gcc.h" 1
ARM GAS  /tmp/cckWj3Ij.s 			page 44


 628 0020 BFF36F8F 		isb 0xF
 629              	@ 0 "" 2
 630              		.thumb
 631              		.syntax unified
 632              	.LBE507:
 633              	.LBE506:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 634              		.loc 1 444 5 discriminator 1 view .LVU170
 635              	.LBB508:
 636              	.LBI508:
1204:Core/cmsis_gcc.h **** {
 637              		.loc 2 1204 31 view .LVU171
 638              	.LBB509:
1206:Core/cmsis_gcc.h **** 
 639              		.loc 2 1206 3 view .LVU172
1208:Core/cmsis_gcc.h ****   return(result);
 640              		.loc 2 1208 3 view .LVU173
 641              		.syntax divided
 642              	@ 1208 "Core/cmsis_gcc.h" 1
 643 0024 EFF31085 		MRS r5, primask
 644              	@ 0 "" 2
 645              	.LVL13:
 646              		.loc 2 1209 3 view .LVU174
 647              		.loc 2 1209 3 is_stmt 0 view .LVU175
 648              		.thumb
 649              		.syntax unified
 650              	.LBE509:
 651              	.LBE508:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 652              		.loc 1 444 5 is_stmt 1 discriminator 2 view .LVU176
 653              	.LBB510:
 654              	.LBI510:
 960:Core/cmsis_gcc.h **** {
 655              		.loc 2 960 27 view .LVU177
 656              	.LBB511:
 962:Core/cmsis_gcc.h **** }
 657              		.loc 2 962 3 view .LVU178
 658              		.syntax divided
 659              	@ 962 "Core/cmsis_gcc.h" 1
 660 0028 72B6     		cpsid i
 661              	@ 0 "" 2
 662              		.thumb
 663              		.syntax unified
 664              	.LBE511:
 665              	.LBE510:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 666              		.loc 1 444 5 discriminator 3 view .LVU179
 445:Library/src/lcm32f06x_pwr.c ****   }
 667              		.loc 1 445 29 is_stmt 0 view .LVU180
 668 002a 0826     		movs	r6, #8
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 669              		.loc 1 444 5 discriminator 3 view .LVU181
 670 002c 0C60     		str	r4, [r1]
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 671              		.loc 1 444 22 is_stmt 1 discriminator 3 view .LVU182
 445:Library/src/lcm32f06x_pwr.c ****   }
 672              		.loc 1 445 5 view .LVU183
ARM GAS  /tmp/cckWj3Ij.s 			page 45


 445:Library/src/lcm32f06x_pwr.c ****   }
 673              		.loc 1 445 29 is_stmt 0 view .LVU184
 674 002e D55C     		ldrb	r5, [r2, r3]
 675 0030 3543     		orrs	r5, r6
 676 0032 D554     		strb	r5, [r2, r3]
 452:Library/src/lcm32f06x_pwr.c **** }
 677              		.loc 1 452 3 is_stmt 1 view .LVU185
 678              	.LBB512:
 679              	.LBI512:
 949:Core/cmsis_gcc.h **** {
 680              		.loc 2 949 27 view .LVU186
 681              	.LBB513:
 951:Core/cmsis_gcc.h **** }
 682              		.loc 2 951 3 view .LVU187
 683              		.syntax divided
 684              	@ 951 "Core/cmsis_gcc.h" 1
 685 0034 62B6     		cpsie i
 686              	@ 0 "" 2
 687              		.thumb
 688              		.syntax unified
 689              	.LBE513:
 690              	.LBE512:
 452:Library/src/lcm32f06x_pwr.c **** }
 691              		.loc 1 452 12 discriminator 1 view .LVU188
 692              	.LVL14:
 452:Library/src/lcm32f06x_pwr.c **** }
 693              		.loc 1 452 12 is_stmt 0 discriminator 1 view .LVU189
 694              	.LBE505:
 695              	.LBE504:
 112:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(DISABLE);
 696              		.loc 1 112 3 is_stmt 1 view .LVU190
 697              	.LBB514:
 698              	.LBI514:
 492:Library/src/lcm32f06x_pwr.c **** {
 699              		.loc 1 492 6 view .LVU191
 700              	.LBB515:
 494:Library/src/lcm32f06x_pwr.c ****   {
 701              		.loc 1 494 3 view .LVU192
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 702              		.loc 1 501 5 view .LVU193
 703              	.LBB516:
 704              	.LBI516:
 258:Core/cmsis_gcc.h **** {
 705              		.loc 2 258 27 view .LVU194
 706              	.LBB517:
 260:Core/cmsis_gcc.h **** }
 707              		.loc 2 260 3 view .LVU195
 708              		.syntax divided
 709              	@ 260 "Core/cmsis_gcc.h" 1
 710 0036 BFF36F8F 		isb 0xF
 711              	@ 0 "" 2
 712              		.thumb
 713              		.syntax unified
 714              	.LBE517:
 715              	.LBE516:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 716              		.loc 1 501 5 discriminator 1 view .LVU196
ARM GAS  /tmp/cckWj3Ij.s 			page 46


 717              	.LBB518:
 718              	.LBI518:
1204:Core/cmsis_gcc.h **** {
 719              		.loc 2 1204 31 view .LVU197
 720              	.LBB519:
1206:Core/cmsis_gcc.h **** 
 721              		.loc 2 1206 3 view .LVU198
1208:Core/cmsis_gcc.h ****   return(result);
 722              		.loc 2 1208 3 view .LVU199
 723              		.syntax divided
 724              	@ 1208 "Core/cmsis_gcc.h" 1
 725 003a EFF31085 		MRS r5, primask
 726              	@ 0 "" 2
 727              	.LVL15:
 728              		.loc 2 1209 3 view .LVU200
 729              		.loc 2 1209 3 is_stmt 0 view .LVU201
 730              		.thumb
 731              		.syntax unified
 732              	.LBE519:
 733              	.LBE518:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 734              		.loc 1 501 5 is_stmt 1 discriminator 2 view .LVU202
 735              	.LBB520:
 736              	.LBI520:
 960:Core/cmsis_gcc.h **** {
 737              		.loc 2 960 27 view .LVU203
 738              	.LBB521:
 962:Core/cmsis_gcc.h **** }
 739              		.loc 2 962 3 view .LVU204
 740              		.syntax divided
 741              	@ 962 "Core/cmsis_gcc.h" 1
 742 003e 72B6     		cpsid i
 743              	@ 0 "" 2
 744              		.thumb
 745              		.syntax unified
 746              	.LBE521:
 747              	.LBE520:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 748              		.loc 1 501 5 discriminator 3 view .LVU205
 502:Library/src/lcm32f06x_pwr.c ****   }
 749              		.loc 1 502 29 is_stmt 0 view .LVU206
 750 0040 0126     		movs	r6, #1
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 751              		.loc 1 501 5 discriminator 3 view .LVU207
 752 0042 0C60     		str	r4, [r1]
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 753              		.loc 1 501 22 is_stmt 1 discriminator 3 view .LVU208
 502:Library/src/lcm32f06x_pwr.c ****   }
 754              		.loc 1 502 5 view .LVU209
 502:Library/src/lcm32f06x_pwr.c ****   }
 755              		.loc 1 502 29 is_stmt 0 view .LVU210
 756 0044 D55C     		ldrb	r5, [r2, r3]
 757 0046 B543     		bics	r5, r6
 758 0048 D554     		strb	r5, [r2, r3]
 759              		.loc 1 504 3 is_stmt 1 view .LVU211
 760              	.LBB522:
 761              	.LBI522:
ARM GAS  /tmp/cckWj3Ij.s 			page 47


 949:Core/cmsis_gcc.h **** {
 762              		.loc 2 949 27 view .LVU212
 763              	.LBB523:
 951:Core/cmsis_gcc.h **** }
 764              		.loc 2 951 3 view .LVU213
 765              		.syntax divided
 766              	@ 951 "Core/cmsis_gcc.h" 1
 767 004a 62B6     		cpsie i
 768              	@ 0 "" 2
 769              		.thumb
 770              		.syntax unified
 771              	.LBE523:
 772              	.LBE522:
 773              		.loc 1 504 12 discriminator 1 view .LVU214
 774              	.LVL16:
 775              		.loc 1 504 12 is_stmt 0 discriminator 1 view .LVU215
 776              	.LBE515:
 777              	.LBE514:
 113:Library/src/lcm32f06x_pwr.c **** 
 778              		.loc 1 113 3 is_stmt 1 view .LVU216
 779              	.LBB524:
 780              	.LBI524:
 414:Library/src/lcm32f06x_pwr.c **** {
 781              		.loc 1 414 6 view .LVU217
 782              	.LBB525:
 416:Library/src/lcm32f06x_pwr.c ****   {
 783              		.loc 1 416 3 view .LVU218
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 784              		.loc 1 423 5 view .LVU219
 785              	.LBB526:
 786              	.LBI526:
 258:Core/cmsis_gcc.h **** {
 787              		.loc 2 258 27 view .LVU220
 788              	.LBB527:
 260:Core/cmsis_gcc.h **** }
 789              		.loc 2 260 3 view .LVU221
 790              		.syntax divided
 791              	@ 260 "Core/cmsis_gcc.h" 1
 792 004c BFF36F8F 		isb 0xF
 793              	@ 0 "" 2
 794              		.thumb
 795              		.syntax unified
 796              	.LBE527:
 797              	.LBE526:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 798              		.loc 1 423 5 discriminator 1 view .LVU222
 799              	.LBB528:
 800              	.LBI528:
1204:Core/cmsis_gcc.h **** {
 801              		.loc 2 1204 31 view .LVU223
 802              	.LBB529:
1206:Core/cmsis_gcc.h **** 
 803              		.loc 2 1206 3 view .LVU224
1208:Core/cmsis_gcc.h ****   return(result);
 804              		.loc 2 1208 3 view .LVU225
 805              		.syntax divided
 806              	@ 1208 "Core/cmsis_gcc.h" 1
ARM GAS  /tmp/cckWj3Ij.s 			page 48


 807 0050 EFF31085 		MRS r5, primask
 808              	@ 0 "" 2
 809              	.LVL17:
 810              		.loc 2 1209 3 view .LVU226
 811              		.loc 2 1209 3 is_stmt 0 view .LVU227
 812              		.thumb
 813              		.syntax unified
 814              	.LBE529:
 815              	.LBE528:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 816              		.loc 1 423 5 is_stmt 1 discriminator 2 view .LVU228
 817              	.LBB530:
 818              	.LBI530:
 960:Core/cmsis_gcc.h **** {
 819              		.loc 2 960 27 view .LVU229
 820              	.LBB531:
 962:Core/cmsis_gcc.h **** }
 821              		.loc 2 962 3 view .LVU230
 822              		.syntax divided
 823              	@ 962 "Core/cmsis_gcc.h" 1
 824 0054 72B6     		cpsid i
 825              	@ 0 "" 2
 826              		.thumb
 827              		.syntax unified
 828              	.LBE531:
 829              	.LBE530:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 830              		.loc 1 423 5 discriminator 3 view .LVU231
 831 0056 0C60     		str	r4, [r1]
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 832              		.loc 1 423 22 discriminator 3 view .LVU232
 424:Library/src/lcm32f06x_pwr.c ****   }
 833              		.loc 1 424 5 view .LVU233
 424:Library/src/lcm32f06x_pwr.c ****   }
 834              		.loc 1 424 30 is_stmt 0 view .LVU234
 835 0058 1024     		movs	r4, #16
 836 005a D15C     		ldrb	r1, [r2, r3]
 837 005c A143     		bics	r1, r4
 838 005e D154     		strb	r1, [r2, r3]
 426:Library/src/lcm32f06x_pwr.c **** }
 839              		.loc 1 426 3 is_stmt 1 view .LVU235
 840              	.LBB532:
 841              	.LBI532:
 949:Core/cmsis_gcc.h **** {
 842              		.loc 2 949 27 view .LVU236
 843              	.LBB533:
 951:Core/cmsis_gcc.h **** }
 844              		.loc 2 951 3 view .LVU237
 845              		.syntax divided
 846              	@ 951 "Core/cmsis_gcc.h" 1
 847 0060 62B6     		cpsie i
 848              	@ 0 "" 2
 849              		.thumb
 850              		.syntax unified
 851              	.LBE533:
 852              	.LBE532:
 426:Library/src/lcm32f06x_pwr.c **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 49


 853              		.loc 1 426 12 discriminator 1 view .LVU238
 854              	.LVL18:
 426:Library/src/lcm32f06x_pwr.c **** }
 855              		.loc 1 426 12 is_stmt 0 discriminator 1 view .LVU239
 856              	.LBE525:
 857              	.LBE524:
 115:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 858              		.loc 1 115 3 is_stmt 1 view .LVU240
 115:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 859              		.loc 1 115 12 is_stmt 0 view .LVU241
 860 0062 0421     		movs	r1, #4
 115:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 861              		.loc 1 115 6 view .LVU242
 862 0064 0A4A     		ldr	r2, .L18+12
 863 0066 1369     		ldr	r3, [r2, #16]
 115:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 864              		.loc 1 115 12 view .LVU243
 865 0068 0B43     		orrs	r3, r1
 866 006a 1361     		str	r3, [r2, #16]
 117:Library/src/lcm32f06x_pwr.c ****   {
 867              		.loc 1 117 3 is_stmt 1 view .LVU244
 117:Library/src/lcm32f06x_pwr.c ****   {
 868              		.loc 1 117 6 is_stmt 0 view .LVU245
 869 006c 0128     		cmp	r0, #1
 870 006e 06D0     		beq	.L17
 125:Library/src/lcm32f06x_pwr.c ****   }
 871              		.loc 1 125 5 is_stmt 1 view .LVU246
 872              		.syntax divided
 873              	@ 125 "Library/src/lcm32f06x_pwr.c" 1
 874 0070 20BF     		wfe
 875              	@ 0 "" 2
 876              		.thumb
 877              		.syntax unified
 878              	.L16:
 128:Library/src/lcm32f06x_pwr.c **** }
 879              		.loc 1 128 3 view .LVU247
 129:Library/src/lcm32f06x_pwr.c **** 
 880              		.loc 1 129 1 is_stmt 0 view .LVU248
 881              		@ sp needed
 128:Library/src/lcm32f06x_pwr.c **** }
 882              		.loc 1 128 12 view .LVU249
 883 0072 0421     		movs	r1, #4
 128:Library/src/lcm32f06x_pwr.c **** }
 884              		.loc 1 128 6 view .LVU250
 885 0074 064A     		ldr	r2, .L18+12
 886 0076 1369     		ldr	r3, [r2, #16]
 128:Library/src/lcm32f06x_pwr.c **** }
 887              		.loc 1 128 12 view .LVU251
 888 0078 8B43     		bics	r3, r1
 889 007a 1361     		str	r3, [r2, #16]
 129:Library/src/lcm32f06x_pwr.c **** 
 890              		.loc 1 129 1 view .LVU252
 891 007c 70BD     		pop	{r4, r5, r6, pc}
 892              	.L17:
 120:Library/src/lcm32f06x_pwr.c ****   }
 893              		.loc 1 120 5 is_stmt 1 view .LVU253
 894              		.syntax divided
ARM GAS  /tmp/cckWj3Ij.s 			page 50


 895              	@ 120 "Library/src/lcm32f06x_pwr.c" 1
 896 007e 30BF     		wfi
 897              	@ 0 "" 2
 898              		.thumb
 899              		.syntax unified
 900 0080 F7E7     		b	.L16
 901              	.L19:
 902 0082 C046     		.align	2
 903              	.L18:
 904 0084 20700140 		.word	1073836064
 905 0088 65432187 		.word	-2027863195
 906 008c 00700140 		.word	1073836032
 907 0090 00ED00E0 		.word	-536810240
 908              		.cfi_endproc
 909              	.LFE47:
 911              		.section	.text.PWR_EnterLowPowerSTOPMode,"ax",%progbits
 912              		.align	1
 913              		.p2align 2,,3
 914              		.global	PWR_EnterLowPowerSTOPMode
 915              		.syntax unified
 916              		.code	16
 917              		.thumb_func
 919              	PWR_EnterLowPowerSTOPMode:
 920              	.LVL19:
 921              	.LFB48:
 143:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);
 922              		.loc 1 143 1 view -0
 923              		.cfi_startproc
 924              		@ args = 0, pretend = 0, frame = 0
 925              		@ frame_needed = 0, uses_anonymous_args = 0
 144:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);
 926              		.loc 1 144 3 view .LVU255
 927              	.LBB534:
 928              	.LBI534:
 466:Library/src/lcm32f06x_pwr.c **** {
 929              		.loc 1 466 6 view .LVU256
 930              	.LBB535:
 468:Library/src/lcm32f06x_pwr.c ****   {
 931              		.loc 1 468 3 view .LVU257
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 932              		.loc 1 470 5 view .LVU258
 933              	.LBB536:
 934              	.LBI536:
 258:Core/cmsis_gcc.h **** {
 935              		.loc 2 258 27 view .LVU259
 936              	.LBB537:
 260:Core/cmsis_gcc.h **** }
 937              		.loc 2 260 3 view .LVU260
 938              	.LBE537:
 939              	.LBE536:
 940              	.LBE535:
 941              	.LBE534:
 143:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerCmd(ENABLE);
 942              		.loc 1 143 1 is_stmt 0 view .LVU261
 943 0000 70B5     		push	{r4, r5, r6, lr}
 944              	.LCFI2:
 945              		.cfi_def_cfa_offset 16
ARM GAS  /tmp/cckWj3Ij.s 			page 51


 946              		.cfi_offset 4, -16
 947              		.cfi_offset 5, -12
 948              		.cfi_offset 6, -8
 949              		.cfi_offset 14, -4
 950              	.LBB547:
 951              	.LBB546:
 952              	.LBB539:
 953              	.LBB538:
 260:Core/cmsis_gcc.h **** }
 954              		.loc 2 260 3 view .LVU262
 955              		.syntax divided
 956              	@ 260 "Core/cmsis_gcc.h" 1
 957 0002 BFF36F8F 		isb 0xF
 958              	@ 0 "" 2
 959              		.thumb
 960              		.syntax unified
 961              	.LBE538:
 962              	.LBE539:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 963              		.loc 1 470 5 is_stmt 1 discriminator 1 view .LVU263
 964              	.LBB540:
 965              	.LBI540:
1204:Core/cmsis_gcc.h **** {
 966              		.loc 2 1204 31 view .LVU264
 967              	.LBB541:
1206:Core/cmsis_gcc.h **** 
 968              		.loc 2 1206 3 view .LVU265
1208:Core/cmsis_gcc.h ****   return(result);
 969              		.loc 2 1208 3 view .LVU266
 970              		.syntax divided
 971              	@ 1208 "Core/cmsis_gcc.h" 1
 972 0006 EFF31083 		MRS r3, primask
 973              	@ 0 "" 2
 974              	.LVL20:
 975              		.loc 2 1209 3 view .LVU267
 976              		.loc 2 1209 3 is_stmt 0 view .LVU268
 977              		.thumb
 978              		.syntax unified
 979              	.LBE541:
 980              	.LBE540:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 981              		.loc 1 470 5 is_stmt 1 discriminator 2 view .LVU269
 982              	.LBB542:
 983              	.LBI542:
 960:Core/cmsis_gcc.h **** {
 984              		.loc 2 960 27 view .LVU270
 985              	.LBB543:
 962:Core/cmsis_gcc.h **** }
 986              		.loc 2 962 3 view .LVU271
 987              		.syntax divided
 988              	@ 962 "Core/cmsis_gcc.h" 1
 989 000a 72B6     		cpsid i
 990              	@ 0 "" 2
 991              		.thumb
 992              		.syntax unified
 993              	.LBE543:
 994              	.LBE542:
ARM GAS  /tmp/cckWj3Ij.s 			page 52


 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 995              		.loc 1 470 5 discriminator 3 view .LVU272
 471:Library/src/lcm32f06x_pwr.c ****   }
 996              		.loc 1 471 30 is_stmt 0 view .LVU273
 997 000c 3023     		movs	r3, #48
 998 000e 0426     		movs	r6, #4
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 999              		.loc 1 470 5 discriminator 3 view .LVU274
 1000 0010 1C49     		ldr	r1, .L24
 1001 0012 1D4C     		ldr	r4, .L24+4
 471:Library/src/lcm32f06x_pwr.c ****   }
 1002              		.loc 1 471 30 view .LVU275
 1003 0014 1D4A     		ldr	r2, .L24+8
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1004              		.loc 1 470 5 discriminator 3 view .LVU276
 1005 0016 0C60     		str	r4, [r1]
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1006              		.loc 1 470 22 is_stmt 1 discriminator 3 view .LVU277
 471:Library/src/lcm32f06x_pwr.c ****   }
 1007              		.loc 1 471 5 view .LVU278
 471:Library/src/lcm32f06x_pwr.c ****   }
 1008              		.loc 1 471 30 is_stmt 0 view .LVU279
 1009 0018 D55C     		ldrb	r5, [r2, r3]
 1010 001a 3543     		orrs	r5, r6
 1011 001c D554     		strb	r5, [r2, r3]
 478:Library/src/lcm32f06x_pwr.c **** }
 1012              		.loc 1 478 3 is_stmt 1 view .LVU280
 1013              	.LBB544:
 1014              	.LBI544:
 949:Core/cmsis_gcc.h **** {
 1015              		.loc 2 949 27 view .LVU281
 1016              	.LBB545:
 951:Core/cmsis_gcc.h **** }
 1017              		.loc 2 951 3 view .LVU282
 1018              		.syntax divided
 1019              	@ 951 "Core/cmsis_gcc.h" 1
 1020 001e 62B6     		cpsie i
 1021              	@ 0 "" 2
 1022              		.thumb
 1023              		.syntax unified
 1024              	.LBE545:
 1025              	.LBE544:
 478:Library/src/lcm32f06x_pwr.c **** }
 1026              		.loc 1 478 12 discriminator 1 view .LVU283
 1027              	.LVL21:
 478:Library/src/lcm32f06x_pwr.c **** }
 1028              		.loc 1 478 12 is_stmt 0 discriminator 1 view .LVU284
 1029              	.LBE546:
 1030              	.LBE547:
 145:Library/src/lcm32f06x_pwr.c **** //  PWR_PowerDownDeepSleep(DISABLE);
 1031              		.loc 1 145 3 is_stmt 1 view .LVU285
 1032              	.LBB548:
 1033              	.LBI548:
 440:Library/src/lcm32f06x_pwr.c **** {
 1034              		.loc 1 440 6 view .LVU286
 1035              	.LBB549:
 442:Library/src/lcm32f06x_pwr.c ****   {
ARM GAS  /tmp/cckWj3Ij.s 			page 53


 1036              		.loc 1 442 3 view .LVU287
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1037              		.loc 1 444 5 view .LVU288
 1038              	.LBB550:
 1039              	.LBI550:
 258:Core/cmsis_gcc.h **** {
 1040              		.loc 2 258 27 view .LVU289
 1041              	.LBB551:
 260:Core/cmsis_gcc.h **** }
 1042              		.loc 2 260 3 view .LVU290
 1043              		.syntax divided
 1044              	@ 260 "Core/cmsis_gcc.h" 1
 1045 0020 BFF36F8F 		isb 0xF
 1046              	@ 0 "" 2
 1047              		.thumb
 1048              		.syntax unified
 1049              	.LBE551:
 1050              	.LBE550:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1051              		.loc 1 444 5 discriminator 1 view .LVU291
 1052              	.LBB552:
 1053              	.LBI552:
1204:Core/cmsis_gcc.h **** {
 1054              		.loc 2 1204 31 view .LVU292
 1055              	.LBB553:
1206:Core/cmsis_gcc.h **** 
 1056              		.loc 2 1206 3 view .LVU293
1208:Core/cmsis_gcc.h ****   return(result);
 1057              		.loc 2 1208 3 view .LVU294
 1058              		.syntax divided
 1059              	@ 1208 "Core/cmsis_gcc.h" 1
 1060 0024 EFF31085 		MRS r5, primask
 1061              	@ 0 "" 2
 1062              	.LVL22:
 1063              		.loc 2 1209 3 view .LVU295
 1064              		.loc 2 1209 3 is_stmt 0 view .LVU296
 1065              		.thumb
 1066              		.syntax unified
 1067              	.LBE553:
 1068              	.LBE552:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1069              		.loc 1 444 5 is_stmt 1 discriminator 2 view .LVU297
 1070              	.LBB554:
 1071              	.LBI554:
 960:Core/cmsis_gcc.h **** {
 1072              		.loc 2 960 27 view .LVU298
 1073              	.LBB555:
 962:Core/cmsis_gcc.h **** }
 1074              		.loc 2 962 3 view .LVU299
 1075              		.syntax divided
 1076              	@ 962 "Core/cmsis_gcc.h" 1
 1077 0028 72B6     		cpsid i
 1078              	@ 0 "" 2
 1079              		.thumb
 1080              		.syntax unified
 1081              	.LBE555:
 1082              	.LBE554:
ARM GAS  /tmp/cckWj3Ij.s 			page 54


 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1083              		.loc 1 444 5 discriminator 3 view .LVU300
 445:Library/src/lcm32f06x_pwr.c ****   }
 1084              		.loc 1 445 29 is_stmt 0 view .LVU301
 1085 002a 0826     		movs	r6, #8
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1086              		.loc 1 444 5 discriminator 3 view .LVU302
 1087 002c 0C60     		str	r4, [r1]
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1088              		.loc 1 444 22 is_stmt 1 discriminator 3 view .LVU303
 445:Library/src/lcm32f06x_pwr.c ****   }
 1089              		.loc 1 445 5 view .LVU304
 445:Library/src/lcm32f06x_pwr.c ****   }
 1090              		.loc 1 445 29 is_stmt 0 view .LVU305
 1091 002e D55C     		ldrb	r5, [r2, r3]
 1092 0030 3543     		orrs	r5, r6
 1093 0032 D554     		strb	r5, [r2, r3]
 452:Library/src/lcm32f06x_pwr.c **** }
 1094              		.loc 1 452 3 is_stmt 1 view .LVU306
 1095              	.LBB556:
 1096              	.LBI556:
 949:Core/cmsis_gcc.h **** {
 1097              		.loc 2 949 27 view .LVU307
 1098              	.LBB557:
 951:Core/cmsis_gcc.h **** }
 1099              		.loc 2 951 3 view .LVU308
 1100              		.syntax divided
 1101              	@ 951 "Core/cmsis_gcc.h" 1
 1102 0034 62B6     		cpsie i
 1103              	@ 0 "" 2
 1104              		.thumb
 1105              		.syntax unified
 1106              	.LBE557:
 1107              	.LBE556:
 452:Library/src/lcm32f06x_pwr.c **** }
 1108              		.loc 1 452 12 discriminator 1 view .LVU309
 1109              	.LVL23:
 452:Library/src/lcm32f06x_pwr.c **** }
 1110              		.loc 1 452 12 is_stmt 0 discriminator 1 view .LVU310
 1111              	.LBE549:
 1112              	.LBE548:
 147:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(DISABLE);
 1113              		.loc 1 147 3 is_stmt 1 view .LVU311
 1114              	.LBB558:
 1115              	.LBI558:
 492:Library/src/lcm32f06x_pwr.c **** {
 1116              		.loc 1 492 6 view .LVU312
 1117              	.LBB559:
 494:Library/src/lcm32f06x_pwr.c ****   {
 1118              		.loc 1 494 3 view .LVU313
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1119              		.loc 1 496 5 view .LVU314
 1120              	.LBB560:
 1121              	.LBI560:
 258:Core/cmsis_gcc.h **** {
 1122              		.loc 2 258 27 view .LVU315
 1123              	.LBB561:
ARM GAS  /tmp/cckWj3Ij.s 			page 55


 260:Core/cmsis_gcc.h **** }
 1124              		.loc 2 260 3 view .LVU316
 1125              		.syntax divided
 1126              	@ 260 "Core/cmsis_gcc.h" 1
 1127 0036 BFF36F8F 		isb 0xF
 1128              	@ 0 "" 2
 1129              		.thumb
 1130              		.syntax unified
 1131              	.LBE561:
 1132              	.LBE560:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1133              		.loc 1 496 5 discriminator 1 view .LVU317
 1134              	.LBB562:
 1135              	.LBI562:
1204:Core/cmsis_gcc.h **** {
 1136              		.loc 2 1204 31 view .LVU318
 1137              	.LBB563:
1206:Core/cmsis_gcc.h **** 
 1138              		.loc 2 1206 3 view .LVU319
1208:Core/cmsis_gcc.h ****   return(result);
 1139              		.loc 2 1208 3 view .LVU320
 1140              		.syntax divided
 1141              	@ 1208 "Core/cmsis_gcc.h" 1
 1142 003a EFF31085 		MRS r5, primask
 1143              	@ 0 "" 2
 1144              	.LVL24:
 1145              		.loc 2 1209 3 view .LVU321
 1146              		.loc 2 1209 3 is_stmt 0 view .LVU322
 1147              		.thumb
 1148              		.syntax unified
 1149              	.LBE563:
 1150              	.LBE562:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1151              		.loc 1 496 5 is_stmt 1 discriminator 2 view .LVU323
 1152              	.LBB564:
 1153              	.LBI564:
 960:Core/cmsis_gcc.h **** {
 1154              		.loc 2 960 27 view .LVU324
 1155              	.LBB565:
 962:Core/cmsis_gcc.h **** }
 1156              		.loc 2 962 3 view .LVU325
 1157              		.syntax divided
 1158              	@ 962 "Core/cmsis_gcc.h" 1
 1159 003e 72B6     		cpsid i
 1160              	@ 0 "" 2
 1161              		.thumb
 1162              		.syntax unified
 1163              	.LBE565:
 1164              	.LBE564:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1165              		.loc 1 496 5 discriminator 3 view .LVU326
 497:Library/src/lcm32f06x_pwr.c ****   }
 1166              		.loc 1 497 29 is_stmt 0 view .LVU327
 1167 0040 0126     		movs	r6, #1
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1168              		.loc 1 496 5 discriminator 3 view .LVU328
 1169 0042 0C60     		str	r4, [r1]
ARM GAS  /tmp/cckWj3Ij.s 			page 56


 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1170              		.loc 1 496 22 is_stmt 1 discriminator 3 view .LVU329
 497:Library/src/lcm32f06x_pwr.c ****   }
 1171              		.loc 1 497 5 view .LVU330
 497:Library/src/lcm32f06x_pwr.c ****   }
 1172              		.loc 1 497 29 is_stmt 0 view .LVU331
 1173 0044 D55C     		ldrb	r5, [r2, r3]
 1174 0046 3543     		orrs	r5, r6
 1175 0048 D554     		strb	r5, [r2, r3]
 1176              		.loc 1 504 3 is_stmt 1 view .LVU332
 1177              	.LBB566:
 1178              	.LBI566:
 949:Core/cmsis_gcc.h **** {
 1179              		.loc 2 949 27 view .LVU333
 1180              	.LBB567:
 951:Core/cmsis_gcc.h **** }
 1181              		.loc 2 951 3 view .LVU334
 1182              		.syntax divided
 1183              	@ 951 "Core/cmsis_gcc.h" 1
 1184 004a 62B6     		cpsie i
 1185              	@ 0 "" 2
 1186              		.thumb
 1187              		.syntax unified
 1188              	.LBE567:
 1189              	.LBE566:
 1190              		.loc 1 504 12 discriminator 1 view .LVU335
 1191              	.LVL25:
 1192              		.loc 1 504 12 is_stmt 0 discriminator 1 view .LVU336
 1193              	.LBE559:
 1194              	.LBE558:
 148:Library/src/lcm32f06x_pwr.c **** 
 1195              		.loc 1 148 3 is_stmt 1 view .LVU337
 1196              	.LBB568:
 1197              	.LBI568:
 414:Library/src/lcm32f06x_pwr.c **** {
 1198              		.loc 1 414 6 view .LVU338
 1199              	.LBB569:
 416:Library/src/lcm32f06x_pwr.c ****   {
 1200              		.loc 1 416 3 view .LVU339
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 1201              		.loc 1 423 5 view .LVU340
 1202              	.LBB570:
 1203              	.LBI570:
 258:Core/cmsis_gcc.h **** {
 1204              		.loc 2 258 27 view .LVU341
 1205              	.LBB571:
 260:Core/cmsis_gcc.h **** }
 1206              		.loc 2 260 3 view .LVU342
 1207              		.syntax divided
 1208              	@ 260 "Core/cmsis_gcc.h" 1
 1209 004c BFF36F8F 		isb 0xF
 1210              	@ 0 "" 2
 1211              		.thumb
 1212              		.syntax unified
 1213              	.LBE571:
 1214              	.LBE570:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
ARM GAS  /tmp/cckWj3Ij.s 			page 57


 1215              		.loc 1 423 5 discriminator 1 view .LVU343
 1216              	.LBB572:
 1217              	.LBI572:
1204:Core/cmsis_gcc.h **** {
 1218              		.loc 2 1204 31 view .LVU344
 1219              	.LBB573:
1206:Core/cmsis_gcc.h **** 
 1220              		.loc 2 1206 3 view .LVU345
1208:Core/cmsis_gcc.h ****   return(result);
 1221              		.loc 2 1208 3 view .LVU346
 1222              		.syntax divided
 1223              	@ 1208 "Core/cmsis_gcc.h" 1
 1224 0050 EFF31085 		MRS r5, primask
 1225              	@ 0 "" 2
 1226              	.LVL26:
 1227              		.loc 2 1209 3 view .LVU347
 1228              		.loc 2 1209 3 is_stmt 0 view .LVU348
 1229              		.thumb
 1230              		.syntax unified
 1231              	.LBE573:
 1232              	.LBE572:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 1233              		.loc 1 423 5 is_stmt 1 discriminator 2 view .LVU349
 1234              	.LBB574:
 1235              	.LBI574:
 960:Core/cmsis_gcc.h **** {
 1236              		.loc 2 960 27 view .LVU350
 1237              	.LBB575:
 962:Core/cmsis_gcc.h **** }
 1238              		.loc 2 962 3 view .LVU351
 1239              		.syntax divided
 1240              	@ 962 "Core/cmsis_gcc.h" 1
 1241 0054 72B6     		cpsid i
 1242              	@ 0 "" 2
 1243              		.thumb
 1244              		.syntax unified
 1245              	.LBE575:
 1246              	.LBE574:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 1247              		.loc 1 423 5 discriminator 3 view .LVU352
 1248 0056 0C60     		str	r4, [r1]
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 1249              		.loc 1 423 22 discriminator 3 view .LVU353
 424:Library/src/lcm32f06x_pwr.c ****   }
 1250              		.loc 1 424 5 view .LVU354
 424:Library/src/lcm32f06x_pwr.c ****   }
 1251              		.loc 1 424 30 is_stmt 0 view .LVU355
 1252 0058 1024     		movs	r4, #16
 1253 005a D15C     		ldrb	r1, [r2, r3]
 1254 005c A143     		bics	r1, r4
 1255 005e D154     		strb	r1, [r2, r3]
 426:Library/src/lcm32f06x_pwr.c **** }
 1256              		.loc 1 426 3 is_stmt 1 view .LVU356
 1257              	.LBB576:
 1258              	.LBI576:
 949:Core/cmsis_gcc.h **** {
 1259              		.loc 2 949 27 view .LVU357
ARM GAS  /tmp/cckWj3Ij.s 			page 58


 1260              	.LBB577:
 951:Core/cmsis_gcc.h **** }
 1261              		.loc 2 951 3 view .LVU358
 1262              		.syntax divided
 1263              	@ 951 "Core/cmsis_gcc.h" 1
 1264 0060 62B6     		cpsie i
 1265              	@ 0 "" 2
 1266              		.thumb
 1267              		.syntax unified
 1268              	.LBE577:
 1269              	.LBE576:
 426:Library/src/lcm32f06x_pwr.c **** }
 1270              		.loc 1 426 12 discriminator 1 view .LVU359
 1271              	.LVL27:
 426:Library/src/lcm32f06x_pwr.c **** }
 1272              		.loc 1 426 12 is_stmt 0 discriminator 1 view .LVU360
 1273              	.LBE569:
 1274              	.LBE568:
 150:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 1275              		.loc 1 150 3 is_stmt 1 view .LVU361
 150:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 1276              		.loc 1 150 12 is_stmt 0 view .LVU362
 1277 0062 0421     		movs	r1, #4
 150:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 1278              		.loc 1 150 6 view .LVU363
 1279 0064 0A4A     		ldr	r2, .L24+12
 1280 0066 1369     		ldr	r3, [r2, #16]
 150:Library/src/lcm32f06x_pwr.c ****   /* Select STOP mode entry --------------------------------------------------*/
 1281              		.loc 1 150 12 view .LVU364
 1282 0068 0B43     		orrs	r3, r1
 1283 006a 1361     		str	r3, [r2, #16]
 152:Library/src/lcm32f06x_pwr.c ****   {
 1284              		.loc 1 152 3 is_stmt 1 view .LVU365
 152:Library/src/lcm32f06x_pwr.c ****   {
 1285              		.loc 1 152 6 is_stmt 0 view .LVU366
 1286 006c 0128     		cmp	r0, #1
 1287 006e 06D0     		beq	.L23
 160:Library/src/lcm32f06x_pwr.c ****   }
 1288              		.loc 1 160 5 is_stmt 1 view .LVU367
 1289              		.syntax divided
 1290              	@ 160 "Library/src/lcm32f06x_pwr.c" 1
 1291 0070 20BF     		wfe
 1292              	@ 0 "" 2
 1293              		.thumb
 1294              		.syntax unified
 1295              	.L22:
 163:Library/src/lcm32f06x_pwr.c **** }
 1296              		.loc 1 163 3 view .LVU368
 164:Library/src/lcm32f06x_pwr.c **** 
 1297              		.loc 1 164 1 is_stmt 0 view .LVU369
 1298              		@ sp needed
 163:Library/src/lcm32f06x_pwr.c **** }
 1299              		.loc 1 163 12 view .LVU370
 1300 0072 0421     		movs	r1, #4
 163:Library/src/lcm32f06x_pwr.c **** }
 1301              		.loc 1 163 6 view .LVU371
 1302 0074 064A     		ldr	r2, .L24+12
ARM GAS  /tmp/cckWj3Ij.s 			page 59


 1303 0076 1369     		ldr	r3, [r2, #16]
 163:Library/src/lcm32f06x_pwr.c **** }
 1304              		.loc 1 163 12 view .LVU372
 1305 0078 8B43     		bics	r3, r1
 1306 007a 1361     		str	r3, [r2, #16]
 164:Library/src/lcm32f06x_pwr.c **** 
 1307              		.loc 1 164 1 view .LVU373
 1308 007c 70BD     		pop	{r4, r5, r6, pc}
 1309              	.L23:
 155:Library/src/lcm32f06x_pwr.c ****   }
 1310              		.loc 1 155 5 is_stmt 1 view .LVU374
 1311              		.syntax divided
 1312              	@ 155 "Library/src/lcm32f06x_pwr.c" 1
 1313 007e 30BF     		wfi
 1314              	@ 0 "" 2
 1315              		.thumb
 1316              		.syntax unified
 1317 0080 F7E7     		b	.L22
 1318              	.L25:
 1319 0082 C046     		.align	2
 1320              	.L24:
 1321 0084 20700140 		.word	1073836064
 1322 0088 65432187 		.word	-2027863195
 1323 008c 00700140 		.word	1073836032
 1324 0090 00ED00E0 		.word	-536810240
 1325              		.cfi_endproc
 1326              	.LFE48:
 1328              		.section	.text.PWR_EnterSTANDBYMode,"ax",%progbits
 1329              		.align	1
 1330              		.p2align 2,,3
 1331              		.global	PWR_EnterSTANDBYMode
 1332              		.syntax unified
 1333              		.code	16
 1334              		.thumb_func
 1336              	PWR_EnterSTANDBYMode:
 1337              	.LFB49:
 173:Library/src/lcm32f06x_pwr.c **** 
 1338              		.loc 1 173 1 view -0
 1339              		.cfi_startproc
 1340              		@ args = 0, pretend = 0, frame = 0
 1341              		@ frame_needed = 0, uses_anonymous_args = 0
 177:Library/src/lcm32f06x_pwr.c ****   PWR_FlashPowerDownDeepSleep(ENABLE);  //CHIPCTRL->CR_b.FPDS=1;
 1342              		.loc 1 177 3 view .LVU376
 1343              	.LVL28:
 1344              	.LBB578:
 1345              	.LBI578:
 466:Library/src/lcm32f06x_pwr.c **** {
 1346              		.loc 1 466 6 view .LVU377
 1347              	.LBB579:
 468:Library/src/lcm32f06x_pwr.c ****   {
 1348              		.loc 1 468 3 view .LVU378
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1349              		.loc 1 470 5 view .LVU379
 1350              	.LBB580:
 1351              	.LBI580:
 258:Core/cmsis_gcc.h **** {
 1352              		.loc 2 258 27 view .LVU380
ARM GAS  /tmp/cckWj3Ij.s 			page 60


 1353              	.LBB581:
 260:Core/cmsis_gcc.h **** }
 1354              		.loc 2 260 3 view .LVU381
 1355              	.LBE581:
 1356              	.LBE580:
 1357              	.LBE579:
 1358              	.LBE578:
 173:Library/src/lcm32f06x_pwr.c **** 
 1359              		.loc 1 173 1 is_stmt 0 view .LVU382
 1360 0000 30B5     		push	{r4, r5, lr}
 1361              	.LCFI3:
 1362              		.cfi_def_cfa_offset 12
 1363              		.cfi_offset 4, -12
 1364              		.cfi_offset 5, -8
 1365              		.cfi_offset 14, -4
 1366              	.LBB591:
 1367              	.LBB590:
 1368              	.LBB583:
 1369              	.LBB582:
 260:Core/cmsis_gcc.h **** }
 1370              		.loc 2 260 3 view .LVU383
 1371              		.syntax divided
 1372              	@ 260 "Core/cmsis_gcc.h" 1
 1373 0002 BFF36F8F 		isb 0xF
 1374              	@ 0 "" 2
 1375              		.thumb
 1376              		.syntax unified
 1377              	.LBE582:
 1378              	.LBE583:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1379              		.loc 1 470 5 is_stmt 1 discriminator 1 view .LVU384
 1380              	.LBB584:
 1381              	.LBI584:
1204:Core/cmsis_gcc.h **** {
 1382              		.loc 2 1204 31 view .LVU385
 1383              	.LBB585:
1206:Core/cmsis_gcc.h **** 
 1384              		.loc 2 1206 3 view .LVU386
1208:Core/cmsis_gcc.h ****   return(result);
 1385              		.loc 2 1208 3 view .LVU387
 1386              		.syntax divided
 1387              	@ 1208 "Core/cmsis_gcc.h" 1
 1388 0006 EFF31083 		MRS r3, primask
 1389              	@ 0 "" 2
 1390              	.LVL29:
 1391              		.loc 2 1209 3 view .LVU388
 1392              		.loc 2 1209 3 is_stmt 0 view .LVU389
 1393              		.thumb
 1394              		.syntax unified
 1395              	.LBE585:
 1396              	.LBE584:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1397              		.loc 1 470 5 is_stmt 1 discriminator 2 view .LVU390
 1398              	.LBB586:
 1399              	.LBI586:
 960:Core/cmsis_gcc.h **** {
 1400              		.loc 2 960 27 view .LVU391
ARM GAS  /tmp/cckWj3Ij.s 			page 61


 1401              	.LBB587:
 962:Core/cmsis_gcc.h **** }
 1402              		.loc 2 962 3 view .LVU392
 1403              		.syntax divided
 1404              	@ 962 "Core/cmsis_gcc.h" 1
 1405 000a 72B6     		cpsid i
 1406              	@ 0 "" 2
 1407              		.thumb
 1408              		.syntax unified
 1409              	.LBE587:
 1410              	.LBE586:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1411              		.loc 1 470 5 discriminator 3 view .LVU393
 471:Library/src/lcm32f06x_pwr.c ****   }
 1412              		.loc 1 471 30 is_stmt 0 view .LVU394
 1413 000c 3023     		movs	r3, #48
 1414 000e 0425     		movs	r5, #4
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1415              		.loc 1 470 5 discriminator 3 view .LVU395
 1416 0010 1749     		ldr	r1, .L27
 1417 0012 1848     		ldr	r0, .L27+4
 471:Library/src/lcm32f06x_pwr.c ****   }
 1418              		.loc 1 471 30 view .LVU396
 1419 0014 184A     		ldr	r2, .L27+8
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1420              		.loc 1 470 5 discriminator 3 view .LVU397
 1421 0016 0860     		str	r0, [r1]
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 1422              		.loc 1 470 22 is_stmt 1 discriminator 3 view .LVU398
 471:Library/src/lcm32f06x_pwr.c ****   }
 1423              		.loc 1 471 5 view .LVU399
 471:Library/src/lcm32f06x_pwr.c ****   }
 1424              		.loc 1 471 30 is_stmt 0 view .LVU400
 1425 0018 D45C     		ldrb	r4, [r2, r3]
 1426 001a 2C43     		orrs	r4, r5
 1427 001c D454     		strb	r4, [r2, r3]
 478:Library/src/lcm32f06x_pwr.c **** }
 1428              		.loc 1 478 3 is_stmt 1 view .LVU401
 1429              	.LBB588:
 1430              	.LBI588:
 949:Core/cmsis_gcc.h **** {
 1431              		.loc 2 949 27 view .LVU402
 1432              	.LBB589:
 951:Core/cmsis_gcc.h **** }
 1433              		.loc 2 951 3 view .LVU403
 1434              		.syntax divided
 1435              	@ 951 "Core/cmsis_gcc.h" 1
 1436 001e 62B6     		cpsie i
 1437              	@ 0 "" 2
 1438              		.thumb
 1439              		.syntax unified
 1440              	.LBE589:
 1441              	.LBE588:
 478:Library/src/lcm32f06x_pwr.c **** }
 1442              		.loc 1 478 12 discriminator 1 view .LVU404
 1443              	.LVL30:
 478:Library/src/lcm32f06x_pwr.c **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 62


 1444              		.loc 1 478 12 is_stmt 0 discriminator 1 view .LVU405
 1445              	.LBE590:
 1446              	.LBE591:
 178:Library/src/lcm32f06x_pwr.c ****   PWR_LowPowerDeepSleep(ENABLE);        //CHIPCTRL->CR_b.LPDS=1;
 1447              		.loc 1 178 3 is_stmt 1 view .LVU406
 1448              	.LBB592:
 1449              	.LBI592:
 440:Library/src/lcm32f06x_pwr.c **** {
 1450              		.loc 1 440 6 view .LVU407
 1451              	.LBB593:
 442:Library/src/lcm32f06x_pwr.c ****   {
 1452              		.loc 1 442 3 view .LVU408
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1453              		.loc 1 444 5 view .LVU409
 1454              	.LBB594:
 1455              	.LBI594:
 258:Core/cmsis_gcc.h **** {
 1456              		.loc 2 258 27 view .LVU410
 1457              	.LBB595:
 260:Core/cmsis_gcc.h **** }
 1458              		.loc 2 260 3 view .LVU411
 1459              		.syntax divided
 1460              	@ 260 "Core/cmsis_gcc.h" 1
 1461 0020 BFF36F8F 		isb 0xF
 1462              	@ 0 "" 2
 1463              		.thumb
 1464              		.syntax unified
 1465              	.LBE595:
 1466              	.LBE594:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1467              		.loc 1 444 5 discriminator 1 view .LVU412
 1468              	.LBB596:
 1469              	.LBI596:
1204:Core/cmsis_gcc.h **** {
 1470              		.loc 2 1204 31 view .LVU413
 1471              	.LBB597:
1206:Core/cmsis_gcc.h **** 
 1472              		.loc 2 1206 3 view .LVU414
1208:Core/cmsis_gcc.h ****   return(result);
 1473              		.loc 2 1208 3 view .LVU415
 1474              		.syntax divided
 1475              	@ 1208 "Core/cmsis_gcc.h" 1
 1476 0024 EFF31084 		MRS r4, primask
 1477              	@ 0 "" 2
 1478              	.LVL31:
 1479              		.loc 2 1209 3 view .LVU416
 1480              		.loc 2 1209 3 is_stmt 0 view .LVU417
 1481              		.thumb
 1482              		.syntax unified
 1483              	.LBE597:
 1484              	.LBE596:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1485              		.loc 1 444 5 is_stmt 1 discriminator 2 view .LVU418
 1486              	.LBB598:
 1487              	.LBI598:
 960:Core/cmsis_gcc.h **** {
 1488              		.loc 2 960 27 view .LVU419
ARM GAS  /tmp/cckWj3Ij.s 			page 63


 1489              	.LBB599:
 962:Core/cmsis_gcc.h **** }
 1490              		.loc 2 962 3 view .LVU420
 1491              		.syntax divided
 1492              	@ 962 "Core/cmsis_gcc.h" 1
 1493 0028 72B6     		cpsid i
 1494              	@ 0 "" 2
 1495              		.thumb
 1496              		.syntax unified
 1497              	.LBE599:
 1498              	.LBE598:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1499              		.loc 1 444 5 discriminator 3 view .LVU421
 445:Library/src/lcm32f06x_pwr.c ****   }
 1500              		.loc 1 445 29 is_stmt 0 view .LVU422
 1501 002a 0825     		movs	r5, #8
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1502              		.loc 1 444 5 discriminator 3 view .LVU423
 1503 002c 0860     		str	r0, [r1]
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 1504              		.loc 1 444 22 is_stmt 1 discriminator 3 view .LVU424
 445:Library/src/lcm32f06x_pwr.c ****   }
 1505              		.loc 1 445 5 view .LVU425
 445:Library/src/lcm32f06x_pwr.c ****   }
 1506              		.loc 1 445 29 is_stmt 0 view .LVU426
 1507 002e D45C     		ldrb	r4, [r2, r3]
 1508 0030 2C43     		orrs	r4, r5
 1509 0032 D454     		strb	r4, [r2, r3]
 452:Library/src/lcm32f06x_pwr.c **** }
 1510              		.loc 1 452 3 is_stmt 1 view .LVU427
 1511              	.LBB600:
 1512              	.LBI600:
 949:Core/cmsis_gcc.h **** {
 1513              		.loc 2 949 27 view .LVU428
 1514              	.LBB601:
 951:Core/cmsis_gcc.h **** }
 1515              		.loc 2 951 3 view .LVU429
 1516              		.syntax divided
 1517              	@ 951 "Core/cmsis_gcc.h" 1
 1518 0034 62B6     		cpsie i
 1519              	@ 0 "" 2
 1520              		.thumb
 1521              		.syntax unified
 1522              	.LBE601:
 1523              	.LBE600:
 452:Library/src/lcm32f06x_pwr.c **** }
 1524              		.loc 1 452 12 discriminator 1 view .LVU430
 1525              	.LVL32:
 452:Library/src/lcm32f06x_pwr.c **** }
 1526              		.loc 1 452 12 is_stmt 0 discriminator 1 view .LVU431
 1527              	.LBE593:
 1528              	.LBE592:
 179:Library/src/lcm32f06x_pwr.c ****   PWR_UltraLowPowerDeepSleep(ENABLE);   //CHIPCTRL->CR_b.ULPDS=1;
 1529              		.loc 1 179 3 is_stmt 1 view .LVU432
 1530              	.LBB602:
 1531              	.LBI602:
 492:Library/src/lcm32f06x_pwr.c **** {
ARM GAS  /tmp/cckWj3Ij.s 			page 64


 1532              		.loc 1 492 6 view .LVU433
 1533              	.LBB603:
 494:Library/src/lcm32f06x_pwr.c ****   {
 1534              		.loc 1 494 3 view .LVU434
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1535              		.loc 1 496 5 view .LVU435
 1536              	.LBB604:
 1537              	.LBI604:
 258:Core/cmsis_gcc.h **** {
 1538              		.loc 2 258 27 view .LVU436
 1539              	.LBB605:
 260:Core/cmsis_gcc.h **** }
 1540              		.loc 2 260 3 view .LVU437
 1541              		.syntax divided
 1542              	@ 260 "Core/cmsis_gcc.h" 1
 1543 0036 BFF36F8F 		isb 0xF
 1544              	@ 0 "" 2
 1545              		.thumb
 1546              		.syntax unified
 1547              	.LBE605:
 1548              	.LBE604:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1549              		.loc 1 496 5 discriminator 1 view .LVU438
 1550              	.LBB606:
 1551              	.LBI606:
1204:Core/cmsis_gcc.h **** {
 1552              		.loc 2 1204 31 view .LVU439
 1553              	.LBB607:
1206:Core/cmsis_gcc.h **** 
 1554              		.loc 2 1206 3 view .LVU440
1208:Core/cmsis_gcc.h ****   return(result);
 1555              		.loc 2 1208 3 view .LVU441
 1556              		.syntax divided
 1557              	@ 1208 "Core/cmsis_gcc.h" 1
 1558 003a EFF31084 		MRS r4, primask
 1559              	@ 0 "" 2
 1560              	.LVL33:
 1561              		.loc 2 1209 3 view .LVU442
 1562              		.loc 2 1209 3 is_stmt 0 view .LVU443
 1563              		.thumb
 1564              		.syntax unified
 1565              	.LBE607:
 1566              	.LBE606:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1567              		.loc 1 496 5 is_stmt 1 discriminator 2 view .LVU444
 1568              	.LBB608:
 1569              	.LBI608:
 960:Core/cmsis_gcc.h **** {
 1570              		.loc 2 960 27 view .LVU445
 1571              	.LBB609:
 962:Core/cmsis_gcc.h **** }
 1572              		.loc 2 962 3 view .LVU446
 1573              		.syntax divided
 1574              	@ 962 "Core/cmsis_gcc.h" 1
 1575 003e 72B6     		cpsid i
 1576              	@ 0 "" 2
 1577              		.thumb
ARM GAS  /tmp/cckWj3Ij.s 			page 65


 1578              		.syntax unified
 1579              	.LBE609:
 1580              	.LBE608:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1581              		.loc 1 496 5 discriminator 3 view .LVU447
 497:Library/src/lcm32f06x_pwr.c ****   }
 1582              		.loc 1 497 29 is_stmt 0 view .LVU448
 1583 0040 0125     		movs	r5, #1
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1584              		.loc 1 496 5 discriminator 3 view .LVU449
 1585 0042 0860     		str	r0, [r1]
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 1586              		.loc 1 496 22 is_stmt 1 discriminator 3 view .LVU450
 497:Library/src/lcm32f06x_pwr.c ****   }
 1587              		.loc 1 497 5 view .LVU451
 497:Library/src/lcm32f06x_pwr.c ****   }
 1588              		.loc 1 497 29 is_stmt 0 view .LVU452
 1589 0044 D45C     		ldrb	r4, [r2, r3]
 1590 0046 2C43     		orrs	r4, r5
 1591 0048 D454     		strb	r4, [r2, r3]
 1592              		.loc 1 504 3 is_stmt 1 view .LVU453
 1593              	.LBB610:
 1594              	.LBI610:
 949:Core/cmsis_gcc.h **** {
 1595              		.loc 2 949 27 view .LVU454
 1596              	.LBB611:
 951:Core/cmsis_gcc.h **** }
 1597              		.loc 2 951 3 view .LVU455
 1598              		.syntax divided
 1599              	@ 951 "Core/cmsis_gcc.h" 1
 1600 004a 62B6     		cpsie i
 1601              	@ 0 "" 2
 1602              		.thumb
 1603              		.syntax unified
 1604              	.LBE611:
 1605              	.LBE610:
 1606              		.loc 1 504 12 discriminator 1 view .LVU456
 1607              	.LVL34:
 1608              		.loc 1 504 12 is_stmt 0 discriminator 1 view .LVU457
 1609              	.LBE603:
 1610              	.LBE602:
 180:Library/src/lcm32f06x_pwr.c ****   SCB->SCR |= ((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 1611              		.loc 1 180 3 is_stmt 1 view .LVU458
 1612              	.LBB612:
 1613              	.LBI612:
 414:Library/src/lcm32f06x_pwr.c **** {
 1614              		.loc 1 414 6 view .LVU459
 1615              	.LBB613:
 416:Library/src/lcm32f06x_pwr.c ****   {
 1616              		.loc 1 416 3 view .LVU460
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 1617              		.loc 1 418 5 view .LVU461
 1618              	.LBB614:
 1619              	.LBI614:
 258:Core/cmsis_gcc.h **** {
 1620              		.loc 2 258 27 view .LVU462
 1621              	.LBB615:
ARM GAS  /tmp/cckWj3Ij.s 			page 66


 260:Core/cmsis_gcc.h **** }
 1622              		.loc 2 260 3 view .LVU463
 1623              		.syntax divided
 1624              	@ 260 "Core/cmsis_gcc.h" 1
 1625 004c BFF36F8F 		isb 0xF
 1626              	@ 0 "" 2
 1627              		.thumb
 1628              		.syntax unified
 1629              	.LBE615:
 1630              	.LBE614:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 1631              		.loc 1 418 5 discriminator 1 view .LVU464
 1632              	.LBB616:
 1633              	.LBI616:
1204:Core/cmsis_gcc.h **** {
 1634              		.loc 2 1204 31 view .LVU465
 1635              	.LBB617:
1206:Core/cmsis_gcc.h **** 
 1636              		.loc 2 1206 3 view .LVU466
1208:Core/cmsis_gcc.h ****   return(result);
 1637              		.loc 2 1208 3 view .LVU467
 1638              		.syntax divided
 1639              	@ 1208 "Core/cmsis_gcc.h" 1
 1640 0050 EFF31084 		MRS r4, primask
 1641              	@ 0 "" 2
 1642              	.LVL35:
 1643              		.loc 2 1209 3 view .LVU468
 1644              		.loc 2 1209 3 is_stmt 0 view .LVU469
 1645              		.thumb
 1646              		.syntax unified
 1647              	.LBE617:
 1648              	.LBE616:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 1649              		.loc 1 418 5 is_stmt 1 discriminator 2 view .LVU470
 1650              	.LBB618:
 1651              	.LBI618:
 960:Core/cmsis_gcc.h **** {
 1652              		.loc 2 960 27 view .LVU471
 1653              	.LBB619:
 962:Core/cmsis_gcc.h **** }
 1654              		.loc 2 962 3 view .LVU472
 1655              		.syntax divided
 1656              	@ 962 "Core/cmsis_gcc.h" 1
 1657 0054 72B6     		cpsid i
 1658              	@ 0 "" 2
 1659              		.thumb
 1660              		.syntax unified
 1661              	.LBE619:
 1662              	.LBE618:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 1663              		.loc 1 418 5 discriminator 3 view .LVU473
 1664 0056 0860     		str	r0, [r1]
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 1665              		.loc 1 418 22 discriminator 3 view .LVU474
 419:Library/src/lcm32f06x_pwr.c ****   }
 1666              		.loc 1 419 5 view .LVU475
 419:Library/src/lcm32f06x_pwr.c ****   }
ARM GAS  /tmp/cckWj3Ij.s 			page 67


 1667              		.loc 1 419 30 is_stmt 0 view .LVU476
 1668 0058 1020     		movs	r0, #16
 1669 005a D15C     		ldrb	r1, [r2, r3]
 1670 005c 0143     		orrs	r1, r0
 1671 005e D154     		strb	r1, [r2, r3]
 426:Library/src/lcm32f06x_pwr.c **** }
 1672              		.loc 1 426 3 is_stmt 1 view .LVU477
 1673              	.LBB620:
 1674              	.LBI620:
 949:Core/cmsis_gcc.h **** {
 1675              		.loc 2 949 27 view .LVU478
 1676              	.LBB621:
 951:Core/cmsis_gcc.h **** }
 1677              		.loc 2 951 3 view .LVU479
 1678              		.syntax divided
 1679              	@ 951 "Core/cmsis_gcc.h" 1
 1680 0060 62B6     		cpsie i
 1681              	@ 0 "" 2
 1682              		.thumb
 1683              		.syntax unified
 1684              	.LBE621:
 1685              	.LBE620:
 426:Library/src/lcm32f06x_pwr.c **** }
 1686              		.loc 1 426 12 discriminator 1 view .LVU480
 1687              	.LVL36:
 426:Library/src/lcm32f06x_pwr.c **** }
 1688              		.loc 1 426 12 is_stmt 0 discriminator 1 view .LVU481
 1689              	.LBE613:
 1690              	.LBE612:
 181:Library/src/lcm32f06x_pwr.c **** 
 1691              		.loc 1 181 3 is_stmt 1 view .LVU482
 181:Library/src/lcm32f06x_pwr.c **** 
 1692              		.loc 1 181 12 is_stmt 0 view .LVU483
 1693 0062 0421     		movs	r1, #4
 181:Library/src/lcm32f06x_pwr.c **** 
 1694              		.loc 1 181 6 view .LVU484
 1695 0064 054A     		ldr	r2, .L27+12
 1696 0066 1369     		ldr	r3, [r2, #16]
 181:Library/src/lcm32f06x_pwr.c **** 
 1697              		.loc 1 181 12 view .LVU485
 1698 0068 0B43     		orrs	r3, r1
 1699 006a 1361     		str	r3, [r2, #16]
 185:Library/src/lcm32f06x_pwr.c ****   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 1700              		.loc 1 185 3 is_stmt 1 view .LVU486
 1701              		.syntax divided
 1702              	@ 185 "Library/src/lcm32f06x_pwr.c" 1
 1703 006c 30BF     		wfi
 1704              	@ 0 "" 2
 188:Library/src/lcm32f06x_pwr.c **** 
 1705              		.loc 1 188 1 is_stmt 0 view .LVU487
 1706              		.thumb
 1707              		.syntax unified
 1708              		@ sp needed
 1709 006e 30BD     		pop	{r4, r5, pc}
 1710              	.L28:
 1711              		.align	2
 1712              	.L27:
ARM GAS  /tmp/cckWj3Ij.s 			page 68


 1713 0070 20700140 		.word	1073836064
 1714 0074 65432187 		.word	-2027863195
 1715 0078 00700140 		.word	1073836032
 1716 007c 00ED00E0 		.word	-536810240
 1717              		.cfi_endproc
 1718              	.LFE49:
 1720              		.section	.text.PWR_AOUTConfig,"ax",%progbits
 1721              		.align	1
 1722              		.p2align 2,,3
 1723              		.global	PWR_AOUTConfig
 1724              		.syntax unified
 1725              		.code	16
 1726              		.thumb_func
 1728              	PWR_AOUTConfig:
 1729              	.LVL37:
 1730              	.LFB50:
 206:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_AOUT_SEL_MODE(PWR_AOUT));
 1731              		.loc 1 206 1 is_stmt 1 view -0
 1732              		.cfi_startproc
 1733              		@ args = 0, pretend = 0, frame = 0
 1734              		@ frame_needed = 0, uses_anonymous_args = 0
 1735              		@ link register save eliminated.
 207:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 1736              		.loc 1 207 3 view .LVU489
 208:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 1737              		.loc 1 208 3 view .LVU490
 1738              	.LBB622:
 1739              	.LBI622:
 258:Core/cmsis_gcc.h **** {
 1740              		.loc 2 258 27 view .LVU491
 1741              	.LBB623:
 260:Core/cmsis_gcc.h **** }
 1742              		.loc 2 260 3 view .LVU492
 1743              	.LBE623:
 1744              	.LBE622:
 206:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_AOUT_SEL_MODE(PWR_AOUT));
 1745              		.loc 1 206 1 is_stmt 0 view .LVU493
 1746 0000 0200     		movs	r2, r0
 1747              	.LBB625:
 1748              	.LBB624:
 260:Core/cmsis_gcc.h **** }
 1749              		.loc 2 260 3 view .LVU494
 1750              		.syntax divided
 1751              	@ 260 "Core/cmsis_gcc.h" 1
 1752 0002 BFF36F8F 		isb 0xF
 1753              	@ 0 "" 2
 1754              		.thumb
 1755              		.syntax unified
 1756              	.LBE624:
 1757              	.LBE625:
 208:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 1758              		.loc 1 208 3 is_stmt 1 discriminator 1 view .LVU495
 1759              	.LBB626:
 1760              	.LBI626:
1204:Core/cmsis_gcc.h **** {
 1761              		.loc 2 1204 31 view .LVU496
 1762              	.LBB627:
ARM GAS  /tmp/cckWj3Ij.s 			page 69


1206:Core/cmsis_gcc.h **** 
 1763              		.loc 2 1206 3 view .LVU497
1208:Core/cmsis_gcc.h ****   return(result);
 1764              		.loc 2 1208 3 view .LVU498
 1765              		.syntax divided
 1766              	@ 1208 "Core/cmsis_gcc.h" 1
 1767 0006 EFF31083 		MRS r3, primask
 1768              	@ 0 "" 2
 1769              	.LVL38:
 1770              		.loc 2 1209 3 view .LVU499
 1771              		.loc 2 1209 3 is_stmt 0 view .LVU500
 1772              		.thumb
 1773              		.syntax unified
 1774              	.LBE627:
 1775              	.LBE626:
 208:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 1776              		.loc 1 208 3 is_stmt 1 discriminator 2 view .LVU501
 1777              	.LBB628:
 1778              	.LBI628:
 960:Core/cmsis_gcc.h **** {
 1779              		.loc 2 960 27 view .LVU502
 1780              	.LBB629:
 962:Core/cmsis_gcc.h **** }
 1781              		.loc 2 962 3 view .LVU503
 1782              		.syntax divided
 1783              	@ 962 "Core/cmsis_gcc.h" 1
 1784 000a 72B6     		cpsid i
 1785              	@ 0 "" 2
 1786              		.thumb
 1787              		.syntax unified
 1788              	.LBE629:
 1789              	.LBE628:
 208:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 1790              		.loc 1 208 3 discriminator 3 view .LVU504
 1791 000c 064B     		ldr	r3, .L30
 1792 000e 0749     		ldr	r1, .L30+4
 1793 0010 1960     		str	r1, [r3]
 208:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.AOUT_SEL = PWR_AOUT;
 1794              		.loc 1 208 20 discriminator 3 view .LVU505
 209:Library/src/lcm32f06x_pwr.c ****   __dekey();
 1795              		.loc 1 209 3 view .LVU506
 209:Library/src/lcm32f06x_pwr.c ****   __dekey();
 1796              		.loc 1 209 32 is_stmt 0 view .LVU507
 1797 0012 0723     		movs	r3, #7
 1798 0014 1340     		ands	r3, r2
 1799 0016 E022     		movs	r2, #224
 1800 0018 0549     		ldr	r1, .L30+8
 1801 001a 5B01     		lsls	r3, r3, #5
 1802 001c 4868     		ldr	r0, [r1, #4]
 1803              	.LVL39:
 209:Library/src/lcm32f06x_pwr.c ****   __dekey();
 1804              		.loc 1 209 32 view .LVU508
 1805 001e 9043     		bics	r0, r2
 1806 0020 1843     		orrs	r0, r3
 1807 0022 4860     		str	r0, [r1, #4]
 210:Library/src/lcm32f06x_pwr.c **** }
 1808              		.loc 1 210 3 is_stmt 1 view .LVU509
ARM GAS  /tmp/cckWj3Ij.s 			page 70


 1809              	.LBB630:
 1810              	.LBI630:
 949:Core/cmsis_gcc.h **** {
 1811              		.loc 2 949 27 view .LVU510
 1812              	.LBB631:
 951:Core/cmsis_gcc.h **** }
 1813              		.loc 2 951 3 view .LVU511
 1814              		.syntax divided
 1815              	@ 951 "Core/cmsis_gcc.h" 1
 1816 0024 62B6     		cpsie i
 1817              	@ 0 "" 2
 1818              		.thumb
 1819              		.syntax unified
 1820              	.LBE631:
 1821              	.LBE630:
 210:Library/src/lcm32f06x_pwr.c **** }
 1822              		.loc 1 210 12 discriminator 1 view .LVU512
 211:Library/src/lcm32f06x_pwr.c **** 
 1823              		.loc 1 211 1 is_stmt 0 view .LVU513
 1824              		@ sp needed
 1825 0026 7047     		bx	lr
 1826              	.L31:
 1827              		.align	2
 1828              	.L30:
 1829 0028 20700140 		.word	1073836064
 1830 002c 65432187 		.word	-2027863195
 1831 0030 00700140 		.word	1073836032
 1832              		.cfi_endproc
 1833              	.LFE50:
 1835              		.section	.text.PWR_AOUTcmd,"ax",%progbits
 1836              		.align	1
 1837              		.p2align 2,,3
 1838              		.global	PWR_AOUTcmd
 1839              		.syntax unified
 1840              		.code	16
 1841              		.thumb_func
 1843              	PWR_AOUTcmd:
 1844              	.LVL40:
 1845              	.LFB51:
 225:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 1846              		.loc 1 225 1 is_stmt 1 view -0
 1847              		.cfi_startproc
 1848              		@ args = 0, pretend = 0, frame = 0
 1849              		@ frame_needed = 0, uses_anonymous_args = 0
 1850              		@ link register save eliminated.
 226:Library/src/lcm32f06x_pwr.c ****   {
 1851              		.loc 1 226 3 view .LVU515
 226:Library/src/lcm32f06x_pwr.c ****   {
 1852              		.loc 1 226 6 is_stmt 0 view .LVU516
 1853 0000 0028     		cmp	r0, #0
 1854 0002 0FD0     		beq	.L33
 228:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 1855              		.loc 1 228 5 is_stmt 1 view .LVU517
 1856              	.LBB632:
 1857              	.LBI632:
 258:Core/cmsis_gcc.h **** {
 1858              		.loc 2 258 27 view .LVU518
ARM GAS  /tmp/cckWj3Ij.s 			page 71


 1859              	.LBB633:
 260:Core/cmsis_gcc.h **** }
 1860              		.loc 2 260 3 view .LVU519
 1861              		.syntax divided
 1862              	@ 260 "Core/cmsis_gcc.h" 1
 1863 0004 BFF36F8F 		isb 0xF
 1864              	@ 0 "" 2
 1865              		.thumb
 1866              		.syntax unified
 1867              	.LBE633:
 1868              	.LBE632:
 228:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 1869              		.loc 1 228 5 discriminator 1 view .LVU520
 1870              	.LBB634:
 1871              	.LBI634:
1204:Core/cmsis_gcc.h **** {
 1872              		.loc 2 1204 31 view .LVU521
 1873              	.LBB635:
1206:Core/cmsis_gcc.h **** 
 1874              		.loc 2 1206 3 view .LVU522
1208:Core/cmsis_gcc.h ****   return(result);
 1875              		.loc 2 1208 3 view .LVU523
 1876              		.syntax divided
 1877              	@ 1208 "Core/cmsis_gcc.h" 1
 1878 0008 EFF31083 		MRS r3, primask
 1879              	@ 0 "" 2
 1880              	.LVL41:
 1881              		.loc 2 1209 3 view .LVU524
 1882              		.loc 2 1209 3 is_stmt 0 view .LVU525
 1883              		.thumb
 1884              		.syntax unified
 1885              	.LBE635:
 1886              	.LBE634:
 228:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 1887              		.loc 1 228 5 is_stmt 1 discriminator 2 view .LVU526
 1888              	.LBB636:
 1889              	.LBI636:
 960:Core/cmsis_gcc.h **** {
 1890              		.loc 2 960 27 view .LVU527
 1891              	.LBB637:
 962:Core/cmsis_gcc.h **** }
 1892              		.loc 2 962 3 view .LVU528
 1893              		.syntax divided
 1894              	@ 962 "Core/cmsis_gcc.h" 1
 1895 000c 72B6     		cpsid i
 1896              	@ 0 "" 2
 1897              		.thumb
 1898              		.syntax unified
 1899              	.LBE637:
 1900              	.LBE636:
 228:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 1901              		.loc 1 228 5 discriminator 3 view .LVU529
 1902 000e 0C4B     		ldr	r3, .L35
 1903 0010 0C4A     		ldr	r2, .L35+4
 1904 0012 1A60     		str	r2, [r3]
 228:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 1;
 1905              		.loc 1 228 22 discriminator 3 view .LVU530
ARM GAS  /tmp/cckWj3Ij.s 			page 72


 229:Library/src/lcm32f06x_pwr.c ****   }
 1906              		.loc 1 229 5 view .LVU531
 229:Library/src/lcm32f06x_pwr.c ****   }
 1907              		.loc 1 229 33 is_stmt 0 view .LVU532
 1908 0014 8023     		movs	r3, #128
 1909 0016 0C4A     		ldr	r2, .L35+8
 1910 0018 9B01     		lsls	r3, r3, #6
 1911 001a 5168     		ldr	r1, [r2, #4]
 1912 001c 0B43     		orrs	r3, r1
 1913 001e 5360     		str	r3, [r2, #4]
 1914              	.L34:
 236:Library/src/lcm32f06x_pwr.c **** }
 1915              		.loc 1 236 3 is_stmt 1 view .LVU533
 1916              	.LBB638:
 1917              	.LBI638:
 949:Core/cmsis_gcc.h **** {
 1918              		.loc 2 949 27 view .LVU534
 1919              	.LBB639:
 951:Core/cmsis_gcc.h **** }
 1920              		.loc 2 951 3 view .LVU535
 1921              		.syntax divided
 1922              	@ 951 "Core/cmsis_gcc.h" 1
 1923 0020 62B6     		cpsie i
 1924              	@ 0 "" 2
 1925              		.thumb
 1926              		.syntax unified
 1927              	.LBE639:
 1928              	.LBE638:
 236:Library/src/lcm32f06x_pwr.c **** }
 1929              		.loc 1 236 12 discriminator 1 view .LVU536
 237:Library/src/lcm32f06x_pwr.c **** 
 1930              		.loc 1 237 1 is_stmt 0 view .LVU537
 1931              		@ sp needed
 1932 0022 7047     		bx	lr
 1933              	.L33:
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1934              		.loc 1 233 5 is_stmt 1 view .LVU538
 1935              	.LBB640:
 1936              	.LBI640:
 258:Core/cmsis_gcc.h **** {
 1937              		.loc 2 258 27 view .LVU539
 1938              	.LBB641:
 260:Core/cmsis_gcc.h **** }
 1939              		.loc 2 260 3 view .LVU540
 1940              		.syntax divided
 1941              	@ 260 "Core/cmsis_gcc.h" 1
 1942 0024 BFF36F8F 		isb 0xF
 1943              	@ 0 "" 2
 1944              		.thumb
 1945              		.syntax unified
 1946              	.LBE641:
 1947              	.LBE640:
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1948              		.loc 1 233 5 discriminator 1 view .LVU541
 1949              	.LBB642:
 1950              	.LBI642:
1204:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/cckWj3Ij.s 			page 73


 1951              		.loc 2 1204 31 view .LVU542
 1952              	.LBB643:
1206:Core/cmsis_gcc.h **** 
 1953              		.loc 2 1206 3 view .LVU543
1208:Core/cmsis_gcc.h ****   return(result);
 1954              		.loc 2 1208 3 view .LVU544
 1955              		.syntax divided
 1956              	@ 1208 "Core/cmsis_gcc.h" 1
 1957 0028 EFF31083 		MRS r3, primask
 1958              	@ 0 "" 2
 1959              	.LVL42:
 1960              		.loc 2 1209 3 view .LVU545
 1961              		.loc 2 1209 3 is_stmt 0 view .LVU546
 1962              		.thumb
 1963              		.syntax unified
 1964              	.LBE643:
 1965              	.LBE642:
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1966              		.loc 1 233 5 is_stmt 1 discriminator 2 view .LVU547
 1967              	.LBB644:
 1968              	.LBI644:
 960:Core/cmsis_gcc.h **** {
 1969              		.loc 2 960 27 view .LVU548
 1970              	.LBB645:
 962:Core/cmsis_gcc.h **** }
 1971              		.loc 2 962 3 view .LVU549
 1972              		.syntax divided
 1973              	@ 962 "Core/cmsis_gcc.h" 1
 1974 002c 72B6     		cpsid i
 1975              	@ 0 "" 2
 1976              		.thumb
 1977              		.syntax unified
 1978              	.LBE645:
 1979              	.LBE644:
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1980              		.loc 1 233 5 discriminator 3 view .LVU550
 1981 002e 044B     		ldr	r3, .L35
 1982 0030 044A     		ldr	r2, .L35+4
 234:Library/src/lcm32f06x_pwr.c ****   }
 1983              		.loc 1 234 33 is_stmt 0 view .LVU551
 1984 0032 0649     		ldr	r1, .L35+12
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1985              		.loc 1 233 5 discriminator 3 view .LVU552
 1986 0034 1A60     		str	r2, [r3]
 233:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.AOUT_EN = 0;
 1987              		.loc 1 233 22 is_stmt 1 discriminator 3 view .LVU553
 234:Library/src/lcm32f06x_pwr.c ****   }
 1988              		.loc 1 234 5 view .LVU554
 234:Library/src/lcm32f06x_pwr.c ****   }
 1989              		.loc 1 234 33 is_stmt 0 view .LVU555
 1990 0036 044A     		ldr	r2, .L35+8
 1991 0038 5368     		ldr	r3, [r2, #4]
 1992 003a 0B40     		ands	r3, r1
 1993 003c 5360     		str	r3, [r2, #4]
 1994 003e EFE7     		b	.L34
 1995              	.L36:
 1996              		.align	2
ARM GAS  /tmp/cckWj3Ij.s 			page 74


 1997              	.L35:
 1998 0040 20700140 		.word	1073836064
 1999 0044 65432187 		.word	-2027863195
 2000 0048 00700140 		.word	1073836032
 2001 004c FFDFFFFF 		.word	-8193
 2002              		.cfi_endproc
 2003              	.LFE51:
 2005              		.section	.text.PWR_LVDConfig,"ax",%progbits
 2006              		.align	1
 2007              		.p2align 2,,3
 2008              		.global	PWR_LVDConfig
 2009              		.syntax unified
 2010              		.code	16
 2011              		.thumb_func
 2013              	PWR_LVDConfig:
 2014              	.LVL43:
 2015              	.LFB52:
 252:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVDIE(IE));
 2016              		.loc 1 252 1 is_stmt 1 view -0
 2017              		.cfi_startproc
 2018              		@ args = 0, pretend = 0, frame = 0
 2019              		@ frame_needed = 0, uses_anonymous_args = 0
 253:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVDInternal_MODE(PWR_LVDLevel));
 2020              		.loc 1 253 3 view .LVU557
 254:Library/src/lcm32f06x_pwr.c ****   if (!IE) // if internal
 2021              		.loc 1 254 3 view .LVU558
 255:Library/src/lcm32f06x_pwr.c ****   {
 2022              		.loc 1 255 3 view .LVU559
 252:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVDIE(IE));
 2023              		.loc 1 252 1 is_stmt 0 view .LVU560
 2024 0000 30B5     		push	{r4, r5, lr}
 2025              	.LCFI4:
 2026              		.cfi_def_cfa_offset 12
 2027              		.cfi_offset 4, -12
 2028              		.cfi_offset 5, -8
 2029              		.cfi_offset 14, -4
 260:Library/src/lcm32f06x_pwr.c ****   }
 2030              		.loc 1 260 30 view .LVU561
 2031 0002 0724     		movs	r4, #7
 2032 0004 0C40     		ands	r4, r1
 255:Library/src/lcm32f06x_pwr.c ****   {
 2033              		.loc 1 255 6 view .LVU562
 2034 0006 0028     		cmp	r0, #0
 2035 0008 1AD1     		bne	.L38
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2036              		.loc 1 257 5 is_stmt 1 view .LVU563
 2037              	.LBB646:
 2038              	.LBI646:
 258:Core/cmsis_gcc.h **** {
 2039              		.loc 2 258 27 view .LVU564
 2040              	.LBB647:
 260:Core/cmsis_gcc.h **** }
 2041              		.loc 2 260 3 view .LVU565
 2042              		.syntax divided
 2043              	@ 260 "Core/cmsis_gcc.h" 1
 2044 000a BFF36F8F 		isb 0xF
 2045              	@ 0 "" 2
ARM GAS  /tmp/cckWj3Ij.s 			page 75


 2046              		.thumb
 2047              		.syntax unified
 2048              	.LBE647:
 2049              	.LBE646:
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2050              		.loc 1 257 5 discriminator 1 view .LVU566
 2051              	.LBB648:
 2052              	.LBI648:
1204:Core/cmsis_gcc.h **** {
 2053              		.loc 2 1204 31 view .LVU567
 2054              	.LBB649:
1206:Core/cmsis_gcc.h **** 
 2055              		.loc 2 1206 3 view .LVU568
1208:Core/cmsis_gcc.h ****   return(result);
 2056              		.loc 2 1208 3 view .LVU569
 2057              		.syntax divided
 2058              	@ 1208 "Core/cmsis_gcc.h" 1
 2059 000e EFF31083 		MRS r3, primask
 2060              	@ 0 "" 2
 2061              	.LVL44:
 2062              		.loc 2 1209 3 view .LVU570
 2063              		.loc 2 1209 3 is_stmt 0 view .LVU571
 2064              		.thumb
 2065              		.syntax unified
 2066              	.LBE649:
 2067              	.LBE648:
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2068              		.loc 1 257 5 is_stmt 1 discriminator 2 view .LVU572
 2069              	.LBB650:
 2070              	.LBI650:
 960:Core/cmsis_gcc.h **** {
 2071              		.loc 2 960 27 view .LVU573
 2072              	.LBB651:
 962:Core/cmsis_gcc.h **** }
 2073              		.loc 2 962 3 view .LVU574
 2074              		.syntax divided
 2075              	@ 962 "Core/cmsis_gcc.h" 1
 2076 0012 72B6     		cpsid i
 2077              	@ 0 "" 2
 2078              		.thumb
 2079              		.syntax unified
 2080              	.LBE651:
 2081              	.LBE650:
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2082              		.loc 1 257 5 discriminator 3 view .LVU575
 2083 0014 184B     		ldr	r3, .L40
 2084 0016 1949     		ldr	r1, .L40+4
 2085              	.LVL45:
 258:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2086              		.loc 1 258 31 is_stmt 0 view .LVU576
 2087 0018 194A     		ldr	r2, .L40+8
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2088              		.loc 1 257 5 discriminator 3 view .LVU577
 2089 001a 1960     		str	r1, [r3]
 257:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 0;
 2090              		.loc 1 257 22 is_stmt 1 discriminator 3 view .LVU578
 258:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
ARM GAS  /tmp/cckWj3Ij.s 			page 76


 2091              		.loc 1 258 5 view .LVU579
 258:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2092              		.loc 1 258 31 is_stmt 0 view .LVU580
 2093 001c 5068     		ldr	r0, [r2, #4]
 2094              	.LVL46:
 258:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2095              		.loc 1 258 31 view .LVU581
 2096 001e 194D     		ldr	r5, .L40+12
 2097 0020 2840     		ands	r0, r5
 2098 0022 5060     		str	r0, [r2, #4]
 259:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2099              		.loc 1 259 5 is_stmt 1 view .LVU582
 2100              	.LBB652:
 2101              	.LBI652:
 258:Core/cmsis_gcc.h **** {
 2102              		.loc 2 258 27 view .LVU583
 2103              	.LBB653:
 260:Core/cmsis_gcc.h **** }
 2104              		.loc 2 260 3 view .LVU584
 2105              		.syntax divided
 2106              	@ 260 "Core/cmsis_gcc.h" 1
 2107 0024 BFF36F8F 		isb 0xF
 2108              	@ 0 "" 2
 2109              		.thumb
 2110              		.syntax unified
 2111              	.LBE653:
 2112              	.LBE652:
 259:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2113              		.loc 1 259 5 discriminator 1 view .LVU585
 2114              	.LBB654:
 2115              	.LBI654:
1204:Core/cmsis_gcc.h **** {
 2116              		.loc 2 1204 31 view .LVU586
 2117              	.LBB655:
1206:Core/cmsis_gcc.h **** 
 2118              		.loc 2 1206 3 view .LVU587
1208:Core/cmsis_gcc.h ****   return(result);
 2119              		.loc 2 1208 3 view .LVU588
 2120              		.syntax divided
 2121              	@ 1208 "Core/cmsis_gcc.h" 1
 2122 0028 EFF31080 		MRS r0, primask
 2123              	@ 0 "" 2
 2124              	.LVL47:
 2125              		.loc 2 1209 3 view .LVU589
 2126              		.loc 2 1209 3 is_stmt 0 view .LVU590
 2127              		.thumb
 2128              		.syntax unified
 2129              	.LBE655:
 2130              	.LBE654:
 259:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2131              		.loc 1 259 5 is_stmt 1 discriminator 2 view .LVU591
 2132              	.LBB656:
 2133              	.LBI656:
 960:Core/cmsis_gcc.h **** {
 2134              		.loc 2 960 27 view .LVU592
 2135              	.LBB657:
 962:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 77


 2136              		.loc 2 962 3 view .LVU593
 2137              		.syntax divided
 2138              	@ 962 "Core/cmsis_gcc.h" 1
 2139 002c 72B6     		cpsid i
 2140              	@ 0 "" 2
 2141              		.thumb
 2142              		.syntax unified
 2143              	.LBE657:
 2144              	.LBE656:
 259:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2145              		.loc 1 259 5 discriminator 3 view .LVU594
 2146 002e 1960     		str	r1, [r3]
 259:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2147              		.loc 1 259 22 discriminator 3 view .LVU595
 260:Library/src/lcm32f06x_pwr.c ****   }
 2148              		.loc 1 260 5 view .LVU596
 260:Library/src/lcm32f06x_pwr.c ****   }
 2149              		.loc 1 260 30 is_stmt 0 view .LVU597
 2150 0030 5368     		ldr	r3, [r2, #4]
 2151 0032 1549     		ldr	r1, .L40+16
 2152 0034 A402     		lsls	r4, r4, #10
 2153 0036 0B40     		ands	r3, r1
 2154 0038 2343     		orrs	r3, r4
 2155 003a 5360     		str	r3, [r2, #4]
 2156              	.L39:
 269:Library/src/lcm32f06x_pwr.c **** }
 2157              		.loc 1 269 3 is_stmt 1 view .LVU598
 2158              	.LBB658:
 2159              	.LBI658:
 949:Core/cmsis_gcc.h **** {
 2160              		.loc 2 949 27 view .LVU599
 2161              	.LBB659:
 951:Core/cmsis_gcc.h **** }
 2162              		.loc 2 951 3 view .LVU600
 2163              		.syntax divided
 2164              	@ 951 "Core/cmsis_gcc.h" 1
 2165 003c 62B6     		cpsie i
 2166              	@ 0 "" 2
 2167              		.thumb
 2168              		.syntax unified
 2169              	.LBE659:
 2170              	.LBE658:
 269:Library/src/lcm32f06x_pwr.c **** }
 2171              		.loc 1 269 12 discriminator 1 view .LVU601
 270:Library/src/lcm32f06x_pwr.c **** 
 2172              		.loc 1 270 1 is_stmt 0 view .LVU602
 2173              		@ sp needed
 2174 003e 30BD     		pop	{r4, r5, pc}
 2175              	.LVL48:
 2176              	.L38:
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2177              		.loc 1 264 5 is_stmt 1 view .LVU603
 2178              	.LBB660:
 2179              	.LBI660:
 258:Core/cmsis_gcc.h **** {
 2180              		.loc 2 258 27 view .LVU604
 2181              	.LBB661:
ARM GAS  /tmp/cckWj3Ij.s 			page 78


 260:Core/cmsis_gcc.h **** }
 2182              		.loc 2 260 3 view .LVU605
 2183              		.syntax divided
 2184              	@ 260 "Core/cmsis_gcc.h" 1
 2185 0040 BFF36F8F 		isb 0xF
 2186              	@ 0 "" 2
 2187              		.thumb
 2188              		.syntax unified
 2189              	.LBE661:
 2190              	.LBE660:
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2191              		.loc 1 264 5 discriminator 1 view .LVU606
 2192              	.LBB662:
 2193              	.LBI662:
1204:Core/cmsis_gcc.h **** {
 2194              		.loc 2 1204 31 view .LVU607
 2195              	.LBB663:
1206:Core/cmsis_gcc.h **** 
 2196              		.loc 2 1206 3 view .LVU608
1208:Core/cmsis_gcc.h ****   return(result);
 2197              		.loc 2 1208 3 view .LVU609
 2198              		.syntax divided
 2199              	@ 1208 "Core/cmsis_gcc.h" 1
 2200 0044 EFF31083 		MRS r3, primask
 2201              	@ 0 "" 2
 2202              	.LVL49:
 2203              		.loc 2 1209 3 view .LVU610
 2204              		.loc 2 1209 3 is_stmt 0 view .LVU611
 2205              		.thumb
 2206              		.syntax unified
 2207              	.LBE663:
 2208              	.LBE662:
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2209              		.loc 1 264 5 is_stmt 1 discriminator 2 view .LVU612
 2210              	.LBB664:
 2211              	.LBI664:
 960:Core/cmsis_gcc.h **** {
 2212              		.loc 2 960 27 view .LVU613
 2213              	.LBB665:
 962:Core/cmsis_gcc.h **** }
 2214              		.loc 2 962 3 view .LVU614
 2215              		.syntax divided
 2216              	@ 962 "Core/cmsis_gcc.h" 1
 2217 0048 72B6     		cpsid i
 2218              	@ 0 "" 2
 2219              		.thumb
 2220              		.syntax unified
 2221              	.LBE665:
 2222              	.LBE664:
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2223              		.loc 1 264 5 discriminator 3 view .LVU615
 265:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2224              		.loc 1 265 31 is_stmt 0 view .LVU616
 2225 004a 8020     		movs	r0, #128
 2226              	.LVL50:
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2227              		.loc 1 264 5 discriminator 3 view .LVU617
ARM GAS  /tmp/cckWj3Ij.s 			page 79


 2228 004c 0A4B     		ldr	r3, .L40
 2229 004e 0B49     		ldr	r1, .L40+4
 2230              	.LVL51:
 265:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2231              		.loc 1 265 31 view .LVU618
 2232 0050 0B4A     		ldr	r2, .L40+8
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2233              		.loc 1 264 5 discriminator 3 view .LVU619
 2234 0052 1960     		str	r1, [r3]
 264:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDES = 1;
 2235              		.loc 1 264 22 is_stmt 1 discriminator 3 view .LVU620
 265:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2236              		.loc 1 265 5 view .LVU621
 265:Library/src/lcm32f06x_pwr.c ****     chipctrl_access();
 2237              		.loc 1 265 31 is_stmt 0 view .LVU622
 2238 0054 5568     		ldr	r5, [r2, #4]
 2239 0056 8000     		lsls	r0, r0, #2
 2240 0058 2843     		orrs	r0, r5
 2241 005a 5060     		str	r0, [r2, #4]
 266:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2242              		.loc 1 266 5 is_stmt 1 view .LVU623
 2243              	.LBB666:
 2244              	.LBI666:
 258:Core/cmsis_gcc.h **** {
 2245              		.loc 2 258 27 view .LVU624
 2246              	.LBB667:
 260:Core/cmsis_gcc.h **** }
 2247              		.loc 2 260 3 view .LVU625
 2248              		.syntax divided
 2249              	@ 260 "Core/cmsis_gcc.h" 1
 2250 005c BFF36F8F 		isb 0xF
 2251              	@ 0 "" 2
 2252              		.thumb
 2253              		.syntax unified
 2254              	.LBE667:
 2255              	.LBE666:
 266:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2256              		.loc 1 266 5 discriminator 1 view .LVU626
 2257              	.LBB668:
 2258              	.LBI668:
1204:Core/cmsis_gcc.h **** {
 2259              		.loc 2 1204 31 view .LVU627
 2260              	.LBB669:
1206:Core/cmsis_gcc.h **** 
 2261              		.loc 2 1206 3 view .LVU628
1208:Core/cmsis_gcc.h ****   return(result);
 2262              		.loc 2 1208 3 view .LVU629
 2263              		.syntax divided
 2264              	@ 1208 "Core/cmsis_gcc.h" 1
 2265 0060 EFF31080 		MRS r0, primask
 2266              	@ 0 "" 2
 2267              	.LVL52:
 2268              		.loc 2 1209 3 view .LVU630
 2269              		.loc 2 1209 3 is_stmt 0 view .LVU631
 2270              		.thumb
 2271              		.syntax unified
 2272              	.LBE669:
ARM GAS  /tmp/cckWj3Ij.s 			page 80


 2273              	.LBE668:
 266:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2274              		.loc 1 266 5 is_stmt 1 discriminator 2 view .LVU632
 2275              	.LBB670:
 2276              	.LBI670:
 960:Core/cmsis_gcc.h **** {
 2277              		.loc 2 960 27 view .LVU633
 2278              	.LBB671:
 962:Core/cmsis_gcc.h **** }
 2279              		.loc 2 962 3 view .LVU634
 2280              		.syntax divided
 2281              	@ 962 "Core/cmsis_gcc.h" 1
 2282 0064 72B6     		cpsid i
 2283              	@ 0 "" 2
 2284              		.thumb
 2285              		.syntax unified
 2286              	.LBE671:
 2287              	.LBE670:
 266:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2288              		.loc 1 266 5 discriminator 3 view .LVU635
 2289 0066 1960     		str	r1, [r3]
 266:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDS = PWR_LVDLevel;
 2290              		.loc 1 266 22 discriminator 3 view .LVU636
 267:Library/src/lcm32f06x_pwr.c ****   }
 2291              		.loc 1 267 5 view .LVU637
 267:Library/src/lcm32f06x_pwr.c ****   }
 2292              		.loc 1 267 30 is_stmt 0 view .LVU638
 2293 0068 5168     		ldr	r1, [r2, #4]
 2294 006a 0748     		ldr	r0, .L40+16
 2295 006c A402     		lsls	r4, r4, #10
 2296 006e 0140     		ands	r1, r0
 2297 0070 2143     		orrs	r1, r4
 2298 0072 5160     		str	r1, [r2, #4]
 2299 0074 E2E7     		b	.L39
 2300              	.L41:
 2301 0076 C046     		.align	2
 2302              	.L40:
 2303 0078 20700140 		.word	1073836064
 2304 007c 65432187 		.word	-2027863195
 2305 0080 00700140 		.word	1073836032
 2306 0084 FFFDFFFF 		.word	-513
 2307 0088 FFE3FFFF 		.word	-7169
 2308              		.cfi_endproc
 2309              	.LFE52:
 2311              		.section	.text.PWR_LVDCmd,"ax",%progbits
 2312              		.align	1
 2313              		.p2align 2,,3
 2314              		.global	PWR_LVDCmd
 2315              		.syntax unified
 2316              		.code	16
 2317              		.thumb_func
 2319              	PWR_LVDCmd:
 2320              	.LVL53:
 2321              	.LFB53:
 284:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 2322              		.loc 1 284 1 is_stmt 1 view -0
 2323              		.cfi_startproc
ARM GAS  /tmp/cckWj3Ij.s 			page 81


 2324              		@ args = 0, pretend = 0, frame = 0
 2325              		@ frame_needed = 0, uses_anonymous_args = 0
 2326              		@ link register save eliminated.
 285:Library/src/lcm32f06x_pwr.c ****   {
 2327              		.loc 1 285 3 view .LVU640
 285:Library/src/lcm32f06x_pwr.c ****   {
 2328              		.loc 1 285 6 is_stmt 0 view .LVU641
 2329 0000 0028     		cmp	r0, #0
 2330 0002 0FD0     		beq	.L43
 287:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 2331              		.loc 1 287 5 is_stmt 1 view .LVU642
 2332              	.LBB672:
 2333              	.LBI672:
 258:Core/cmsis_gcc.h **** {
 2334              		.loc 2 258 27 view .LVU643
 2335              	.LBB673:
 260:Core/cmsis_gcc.h **** }
 2336              		.loc 2 260 3 view .LVU644
 2337              		.syntax divided
 2338              	@ 260 "Core/cmsis_gcc.h" 1
 2339 0004 BFF36F8F 		isb 0xF
 2340              	@ 0 "" 2
 2341              		.thumb
 2342              		.syntax unified
 2343              	.LBE673:
 2344              	.LBE672:
 287:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 2345              		.loc 1 287 5 discriminator 1 view .LVU645
 2346              	.LBB674:
 2347              	.LBI674:
1204:Core/cmsis_gcc.h **** {
 2348              		.loc 2 1204 31 view .LVU646
 2349              	.LBB675:
1206:Core/cmsis_gcc.h **** 
 2350              		.loc 2 1206 3 view .LVU647
1208:Core/cmsis_gcc.h ****   return(result);
 2351              		.loc 2 1208 3 view .LVU648
 2352              		.syntax divided
 2353              	@ 1208 "Core/cmsis_gcc.h" 1
 2354 0008 EFF31083 		MRS r3, primask
 2355              	@ 0 "" 2
 2356              	.LVL54:
 2357              		.loc 2 1209 3 view .LVU649
 2358              		.loc 2 1209 3 is_stmt 0 view .LVU650
 2359              		.thumb
 2360              		.syntax unified
 2361              	.LBE675:
 2362              	.LBE674:
 287:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 2363              		.loc 1 287 5 is_stmt 1 discriminator 2 view .LVU651
 2364              	.LBB676:
 2365              	.LBI676:
 960:Core/cmsis_gcc.h **** {
 2366              		.loc 2 960 27 view .LVU652
 2367              	.LBB677:
 962:Core/cmsis_gcc.h **** }
 2368              		.loc 2 962 3 view .LVU653
ARM GAS  /tmp/cckWj3Ij.s 			page 82


 2369              		.syntax divided
 2370              	@ 962 "Core/cmsis_gcc.h" 1
 2371 000c 72B6     		cpsid i
 2372              	@ 0 "" 2
 2373              		.thumb
 2374              		.syntax unified
 2375              	.LBE677:
 2376              	.LBE676:
 287:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 2377              		.loc 1 287 5 discriminator 3 view .LVU654
 2378 000e 0C4B     		ldr	r3, .L45
 2379 0010 0C4A     		ldr	r2, .L45+4
 2380 0012 1A60     		str	r2, [r3]
 287:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 1;
 2381              		.loc 1 287 22 discriminator 3 view .LVU655
 288:Library/src/lcm32f06x_pwr.c ****   }
 2382              		.loc 1 288 5 view .LVU656
 288:Library/src/lcm32f06x_pwr.c ****   }
 2383              		.loc 1 288 31 is_stmt 0 view .LVU657
 2384 0014 8023     		movs	r3, #128
 2385 0016 0C4A     		ldr	r2, .L45+8
 2386 0018 5B00     		lsls	r3, r3, #1
 2387 001a 5168     		ldr	r1, [r2, #4]
 2388 001c 0B43     		orrs	r3, r1
 2389 001e 5360     		str	r3, [r2, #4]
 2390              	.L44:
 295:Library/src/lcm32f06x_pwr.c **** }
 2391              		.loc 1 295 3 is_stmt 1 view .LVU658
 2392              	.LBB678:
 2393              	.LBI678:
 949:Core/cmsis_gcc.h **** {
 2394              		.loc 2 949 27 view .LVU659
 2395              	.LBB679:
 951:Core/cmsis_gcc.h **** }
 2396              		.loc 2 951 3 view .LVU660
 2397              		.syntax divided
 2398              	@ 951 "Core/cmsis_gcc.h" 1
 2399 0020 62B6     		cpsie i
 2400              	@ 0 "" 2
 2401              		.thumb
 2402              		.syntax unified
 2403              	.LBE679:
 2404              	.LBE678:
 295:Library/src/lcm32f06x_pwr.c **** }
 2405              		.loc 1 295 12 discriminator 1 view .LVU661
 296:Library/src/lcm32f06x_pwr.c **** 
 2406              		.loc 1 296 1 is_stmt 0 view .LVU662
 2407              		@ sp needed
 2408 0022 7047     		bx	lr
 2409              	.L43:
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 2410              		.loc 1 292 5 is_stmt 1 view .LVU663
 2411              	.LBB680:
 2412              	.LBI680:
 258:Core/cmsis_gcc.h **** {
 2413              		.loc 2 258 27 view .LVU664
 2414              	.LBB681:
ARM GAS  /tmp/cckWj3Ij.s 			page 83


 260:Core/cmsis_gcc.h **** }
 2415              		.loc 2 260 3 view .LVU665
 2416              		.syntax divided
 2417              	@ 260 "Core/cmsis_gcc.h" 1
 2418 0024 BFF36F8F 		isb 0xF
 2419              	@ 0 "" 2
 2420              		.thumb
 2421              		.syntax unified
 2422              	.LBE681:
 2423              	.LBE680:
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 2424              		.loc 1 292 5 discriminator 1 view .LVU666
 2425              	.LBB682:
 2426              	.LBI682:
1204:Core/cmsis_gcc.h **** {
 2427              		.loc 2 1204 31 view .LVU667
 2428              	.LBB683:
1206:Core/cmsis_gcc.h **** 
 2429              		.loc 2 1206 3 view .LVU668
1208:Core/cmsis_gcc.h ****   return(result);
 2430              		.loc 2 1208 3 view .LVU669
 2431              		.syntax divided
 2432              	@ 1208 "Core/cmsis_gcc.h" 1
 2433 0028 EFF31083 		MRS r3, primask
 2434              	@ 0 "" 2
 2435              	.LVL55:
 2436              		.loc 2 1209 3 view .LVU670
 2437              		.loc 2 1209 3 is_stmt 0 view .LVU671
 2438              		.thumb
 2439              		.syntax unified
 2440              	.LBE683:
 2441              	.LBE682:
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 2442              		.loc 1 292 5 is_stmt 1 discriminator 2 view .LVU672
 2443              	.LBB684:
 2444              	.LBI684:
 960:Core/cmsis_gcc.h **** {
 2445              		.loc 2 960 27 view .LVU673
 2446              	.LBB685:
 962:Core/cmsis_gcc.h **** }
 2447              		.loc 2 962 3 view .LVU674
 2448              		.syntax divided
 2449              	@ 962 "Core/cmsis_gcc.h" 1
 2450 002c 72B6     		cpsid i
 2451              	@ 0 "" 2
 2452              		.thumb
 2453              		.syntax unified
 2454              	.LBE685:
 2455              	.LBE684:
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 2456              		.loc 1 292 5 discriminator 3 view .LVU675
 2457 002e 044B     		ldr	r3, .L45
 2458 0030 044A     		ldr	r2, .L45+4
 293:Library/src/lcm32f06x_pwr.c ****   }
 2459              		.loc 1 293 31 is_stmt 0 view .LVU676
 2460 0032 0649     		ldr	r1, .L45+12
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
ARM GAS  /tmp/cckWj3Ij.s 			page 84


 2461              		.loc 1 292 5 discriminator 3 view .LVU677
 2462 0034 1A60     		str	r2, [r3]
 292:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVDEN = 0;
 2463              		.loc 1 292 22 is_stmt 1 discriminator 3 view .LVU678
 293:Library/src/lcm32f06x_pwr.c ****   }
 2464              		.loc 1 293 5 view .LVU679
 293:Library/src/lcm32f06x_pwr.c ****   }
 2465              		.loc 1 293 31 is_stmt 0 view .LVU680
 2466 0036 044A     		ldr	r2, .L45+8
 2467 0038 5368     		ldr	r3, [r2, #4]
 2468 003a 0B40     		ands	r3, r1
 2469 003c 5360     		str	r3, [r2, #4]
 2470 003e EFE7     		b	.L44
 2471              	.L46:
 2472              		.align	2
 2473              	.L45:
 2474 0040 20700140 		.word	1073836064
 2475 0044 65432187 		.word	-2027863195
 2476 0048 00700140 		.word	1073836032
 2477 004c FFFEFFFF 		.word	-257
 2478              		.cfi_endproc
 2479              	.LFE53:
 2481              		.section	.text.PWR_LVRConfig,"ax",%progbits
 2482              		.align	1
 2483              		.p2align 2,,3
 2484              		.global	PWR_LVRConfig
 2485              		.syntax unified
 2486              		.code	16
 2487              		.thumb_func
 2489              	PWR_LVRConfig:
 2490              	.LVL56:
 2491              	.LFB54:
 308:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVRLevel(PWR_LVRLevel));
 2492              		.loc 1 308 1 is_stmt 1 view -0
 2493              		.cfi_startproc
 2494              		@ args = 0, pretend = 0, frame = 0
 2495              		@ frame_needed = 0, uses_anonymous_args = 0
 2496              		@ link register save eliminated.
 309:Library/src/lcm32f06x_pwr.c **** 
 2497              		.loc 1 309 3 view .LVU682
 311:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 2498              		.loc 1 311 3 view .LVU683
 2499              	.LBB686:
 2500              	.LBI686:
 258:Core/cmsis_gcc.h **** {
 2501              		.loc 2 258 27 view .LVU684
 2502              	.LBB687:
 260:Core/cmsis_gcc.h **** }
 2503              		.loc 2 260 3 view .LVU685
 2504              	.LBE687:
 2505              	.LBE686:
 308:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_PWR_LVRLevel(PWR_LVRLevel));
 2506              		.loc 1 308 1 is_stmt 0 view .LVU686
 2507 0000 0200     		movs	r2, r0
 2508              	.LBB689:
 2509              	.LBB688:
 260:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 85


 2510              		.loc 2 260 3 view .LVU687
 2511              		.syntax divided
 2512              	@ 260 "Core/cmsis_gcc.h" 1
 2513 0002 BFF36F8F 		isb 0xF
 2514              	@ 0 "" 2
 2515              		.thumb
 2516              		.syntax unified
 2517              	.LBE688:
 2518              	.LBE689:
 311:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 2519              		.loc 1 311 3 is_stmt 1 discriminator 1 view .LVU688
 2520              	.LBB690:
 2521              	.LBI690:
1204:Core/cmsis_gcc.h **** {
 2522              		.loc 2 1204 31 view .LVU689
 2523              	.LBB691:
1206:Core/cmsis_gcc.h **** 
 2524              		.loc 2 1206 3 view .LVU690
1208:Core/cmsis_gcc.h ****   return(result);
 2525              		.loc 2 1208 3 view .LVU691
 2526              		.syntax divided
 2527              	@ 1208 "Core/cmsis_gcc.h" 1
 2528 0006 EFF31083 		MRS r3, primask
 2529              	@ 0 "" 2
 2530              	.LVL57:
 2531              		.loc 2 1209 3 view .LVU692
 2532              		.loc 2 1209 3 is_stmt 0 view .LVU693
 2533              		.thumb
 2534              		.syntax unified
 2535              	.LBE691:
 2536              	.LBE690:
 311:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 2537              		.loc 1 311 3 is_stmt 1 discriminator 2 view .LVU694
 2538              	.LBB692:
 2539              	.LBI692:
 960:Core/cmsis_gcc.h **** {
 2540              		.loc 2 960 27 view .LVU695
 2541              	.LBB693:
 962:Core/cmsis_gcc.h **** }
 2542              		.loc 2 962 3 view .LVU696
 2543              		.syntax divided
 2544              	@ 962 "Core/cmsis_gcc.h" 1
 2545 000a 72B6     		cpsid i
 2546              	@ 0 "" 2
 2547              		.thumb
 2548              		.syntax unified
 2549              	.LBE693:
 2550              	.LBE692:
 311:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 2551              		.loc 1 311 3 discriminator 3 view .LVU697
 2552 000c 064B     		ldr	r3, .L48
 2553 000e 0749     		ldr	r1, .L48+4
 2554 0010 1960     		str	r1, [r3]
 311:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_CFG_b.LVRS = PWR_LVRLevel;
 2555              		.loc 1 311 20 discriminator 3 view .LVU698
 312:Library/src/lcm32f06x_pwr.c ****   __dekey();
 2556              		.loc 1 312 3 view .LVU699
ARM GAS  /tmp/cckWj3Ij.s 			page 86


 312:Library/src/lcm32f06x_pwr.c ****   __dekey();
 2557              		.loc 1 312 28 is_stmt 0 view .LVU700
 2558 0012 0723     		movs	r3, #7
 2559 0014 1340     		ands	r3, r2
 2560 0016 0E22     		movs	r2, #14
 2561 0018 0549     		ldr	r1, .L48+8
 2562 001a 5B00     		lsls	r3, r3, #1
 2563 001c 4868     		ldr	r0, [r1, #4]
 2564              	.LVL58:
 312:Library/src/lcm32f06x_pwr.c ****   __dekey();
 2565              		.loc 1 312 28 view .LVU701
 2566 001e 9043     		bics	r0, r2
 2567 0020 1843     		orrs	r0, r3
 2568 0022 4860     		str	r0, [r1, #4]
 313:Library/src/lcm32f06x_pwr.c **** }
 2569              		.loc 1 313 3 is_stmt 1 view .LVU702
 2570              	.LBB694:
 2571              	.LBI694:
 949:Core/cmsis_gcc.h **** {
 2572              		.loc 2 949 27 view .LVU703
 2573              	.LBB695:
 951:Core/cmsis_gcc.h **** }
 2574              		.loc 2 951 3 view .LVU704
 2575              		.syntax divided
 2576              	@ 951 "Core/cmsis_gcc.h" 1
 2577 0024 62B6     		cpsie i
 2578              	@ 0 "" 2
 2579              		.thumb
 2580              		.syntax unified
 2581              	.LBE695:
 2582              	.LBE694:
 313:Library/src/lcm32f06x_pwr.c **** }
 2583              		.loc 1 313 12 discriminator 1 view .LVU705
 314:Library/src/lcm32f06x_pwr.c **** 
 2584              		.loc 1 314 1 is_stmt 0 view .LVU706
 2585              		@ sp needed
 2586 0026 7047     		bx	lr
 2587              	.L49:
 2588              		.align	2
 2589              	.L48:
 2590 0028 20700140 		.word	1073836064
 2591 002c 65432187 		.word	-2027863195
 2592 0030 00700140 		.word	1073836032
 2593              		.cfi_endproc
 2594              	.LFE54:
 2596              		.section	.text.PWR_LVRCmd,"ax",%progbits
 2597              		.align	1
 2598              		.p2align 2,,3
 2599              		.global	PWR_LVRCmd
 2600              		.syntax unified
 2601              		.code	16
 2602              		.thumb_func
 2604              	PWR_LVRCmd:
 2605              	.LVL59:
 2606              	.LFB55:
 328:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 2607              		.loc 1 328 1 is_stmt 1 view -0
ARM GAS  /tmp/cckWj3Ij.s 			page 87


 2608              		.cfi_startproc
 2609              		@ args = 0, pretend = 0, frame = 0
 2610              		@ frame_needed = 0, uses_anonymous_args = 0
 2611              		@ link register save eliminated.
 329:Library/src/lcm32f06x_pwr.c ****   {
 2612              		.loc 1 329 3 view .LVU708
 329:Library/src/lcm32f06x_pwr.c ****   {
 2613              		.loc 1 329 6 is_stmt 0 view .LVU709
 2614 0000 0028     		cmp	r0, #0
 2615 0002 0ED0     		beq	.L51
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2616              		.loc 1 331 5 is_stmt 1 view .LVU710
 2617              	.LBB696:
 2618              	.LBI696:
 258:Core/cmsis_gcc.h **** {
 2619              		.loc 2 258 27 view .LVU711
 2620              	.LBB697:
 260:Core/cmsis_gcc.h **** }
 2621              		.loc 2 260 3 view .LVU712
 2622              		.syntax divided
 2623              	@ 260 "Core/cmsis_gcc.h" 1
 2624 0004 BFF36F8F 		isb 0xF
 2625              	@ 0 "" 2
 2626              		.thumb
 2627              		.syntax unified
 2628              	.LBE697:
 2629              	.LBE696:
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2630              		.loc 1 331 5 discriminator 1 view .LVU713
 2631              	.LBB698:
 2632              	.LBI698:
1204:Core/cmsis_gcc.h **** {
 2633              		.loc 2 1204 31 view .LVU714
 2634              	.LBB699:
1206:Core/cmsis_gcc.h **** 
 2635              		.loc 2 1206 3 view .LVU715
1208:Core/cmsis_gcc.h ****   return(result);
 2636              		.loc 2 1208 3 view .LVU716
 2637              		.syntax divided
 2638              	@ 1208 "Core/cmsis_gcc.h" 1
 2639 0008 EFF31083 		MRS r3, primask
 2640              	@ 0 "" 2
 2641              	.LVL60:
 2642              		.loc 2 1209 3 view .LVU717
 2643              		.loc 2 1209 3 is_stmt 0 view .LVU718
 2644              		.thumb
 2645              		.syntax unified
 2646              	.LBE699:
 2647              	.LBE698:
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2648              		.loc 1 331 5 is_stmt 1 discriminator 2 view .LVU719
 2649              	.LBB700:
 2650              	.LBI700:
 960:Core/cmsis_gcc.h **** {
 2651              		.loc 2 960 27 view .LVU720
 2652              	.LBB701:
 962:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 88


 2653              		.loc 2 962 3 view .LVU721
 2654              		.syntax divided
 2655              	@ 962 "Core/cmsis_gcc.h" 1
 2656 000c 72B6     		cpsid i
 2657              	@ 0 "" 2
 2658              		.thumb
 2659              		.syntax unified
 2660              	.LBE701:
 2661              	.LBE700:
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2662              		.loc 1 331 5 discriminator 3 view .LVU722
 332:Library/src/lcm32f06x_pwr.c ****   }
 2663              		.loc 1 332 31 is_stmt 0 view .LVU723
 2664 000e 0121     		movs	r1, #1
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2665              		.loc 1 331 5 discriminator 3 view .LVU724
 2666 0010 0B4B     		ldr	r3, .L53
 2667 0012 0C4A     		ldr	r2, .L53+4
 2668 0014 1A60     		str	r2, [r3]
 331:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 1;
 2669              		.loc 1 331 22 is_stmt 1 discriminator 3 view .LVU725
 332:Library/src/lcm32f06x_pwr.c ****   }
 2670              		.loc 1 332 5 view .LVU726
 332:Library/src/lcm32f06x_pwr.c ****   }
 2671              		.loc 1 332 31 is_stmt 0 view .LVU727
 2672 0016 0C4A     		ldr	r2, .L53+8
 2673 0018 5368     		ldr	r3, [r2, #4]
 2674 001a 0B43     		orrs	r3, r1
 2675 001c 5360     		str	r3, [r2, #4]
 2676              	.L52:
 339:Library/src/lcm32f06x_pwr.c **** }
 2677              		.loc 1 339 3 is_stmt 1 view .LVU728
 2678              	.LBB702:
 2679              	.LBI702:
 949:Core/cmsis_gcc.h **** {
 2680              		.loc 2 949 27 view .LVU729
 2681              	.LBB703:
 951:Core/cmsis_gcc.h **** }
 2682              		.loc 2 951 3 view .LVU730
 2683              		.syntax divided
 2684              	@ 951 "Core/cmsis_gcc.h" 1
 2685 001e 62B6     		cpsie i
 2686              	@ 0 "" 2
 2687              		.thumb
 2688              		.syntax unified
 2689              	.LBE703:
 2690              	.LBE702:
 339:Library/src/lcm32f06x_pwr.c **** }
 2691              		.loc 1 339 12 discriminator 1 view .LVU731
 340:Library/src/lcm32f06x_pwr.c **** #if defined (LCM32F067) || defined (LCM32F063)  || defined (LCM32CF6990)
 2692              		.loc 1 340 1 is_stmt 0 view .LVU732
 2693              		@ sp needed
 2694 0020 7047     		bx	lr
 2695              	.L51:
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2696              		.loc 1 336 5 is_stmt 1 view .LVU733
 2697              	.LBB704:
ARM GAS  /tmp/cckWj3Ij.s 			page 89


 2698              	.LBI704:
 258:Core/cmsis_gcc.h **** {
 2699              		.loc 2 258 27 view .LVU734
 2700              	.LBB705:
 260:Core/cmsis_gcc.h **** }
 2701              		.loc 2 260 3 view .LVU735
 2702              		.syntax divided
 2703              	@ 260 "Core/cmsis_gcc.h" 1
 2704 0022 BFF36F8F 		isb 0xF
 2705              	@ 0 "" 2
 2706              		.thumb
 2707              		.syntax unified
 2708              	.LBE705:
 2709              	.LBE704:
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2710              		.loc 1 336 5 discriminator 1 view .LVU736
 2711              	.LBB706:
 2712              	.LBI706:
1204:Core/cmsis_gcc.h **** {
 2713              		.loc 2 1204 31 view .LVU737
 2714              	.LBB707:
1206:Core/cmsis_gcc.h **** 
 2715              		.loc 2 1206 3 view .LVU738
1208:Core/cmsis_gcc.h ****   return(result);
 2716              		.loc 2 1208 3 view .LVU739
 2717              		.syntax divided
 2718              	@ 1208 "Core/cmsis_gcc.h" 1
 2719 0026 EFF31083 		MRS r3, primask
 2720              	@ 0 "" 2
 2721              	.LVL61:
 2722              		.loc 2 1209 3 view .LVU740
 2723              		.loc 2 1209 3 is_stmt 0 view .LVU741
 2724              		.thumb
 2725              		.syntax unified
 2726              	.LBE707:
 2727              	.LBE706:
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2728              		.loc 1 336 5 is_stmt 1 discriminator 2 view .LVU742
 2729              	.LBB708:
 2730              	.LBI708:
 960:Core/cmsis_gcc.h **** {
 2731              		.loc 2 960 27 view .LVU743
 2732              	.LBB709:
 962:Core/cmsis_gcc.h **** }
 2733              		.loc 2 962 3 view .LVU744
 2734              		.syntax divided
 2735              	@ 962 "Core/cmsis_gcc.h" 1
 2736 002a 72B6     		cpsid i
 2737              	@ 0 "" 2
 2738              		.thumb
 2739              		.syntax unified
 2740              	.LBE709:
 2741              	.LBE708:
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2742              		.loc 1 336 5 discriminator 3 view .LVU745
 337:Library/src/lcm32f06x_pwr.c ****   }
 2743              		.loc 1 337 31 is_stmt 0 view .LVU746
ARM GAS  /tmp/cckWj3Ij.s 			page 90


 2744 002c 0121     		movs	r1, #1
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2745              		.loc 1 336 5 discriminator 3 view .LVU747
 2746 002e 044B     		ldr	r3, .L53
 2747 0030 044A     		ldr	r2, .L53+4
 2748 0032 1A60     		str	r2, [r3]
 336:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CFG_b.LVREN = 0;
 2749              		.loc 1 336 22 is_stmt 1 discriminator 3 view .LVU748
 337:Library/src/lcm32f06x_pwr.c ****   }
 2750              		.loc 1 337 5 view .LVU749
 337:Library/src/lcm32f06x_pwr.c ****   }
 2751              		.loc 1 337 31 is_stmt 0 view .LVU750
 2752 0034 044A     		ldr	r2, .L53+8
 2753 0036 5368     		ldr	r3, [r2, #4]
 2754 0038 8B43     		bics	r3, r1
 2755 003a 5360     		str	r3, [r2, #4]
 2756 003c EFE7     		b	.L52
 2757              	.L54:
 2758 003e C046     		.align	2
 2759              	.L53:
 2760 0040 20700140 		.word	1073836064
 2761 0044 65432187 		.word	-2027863195
 2762 0048 00700140 		.word	1073836032
 2763              		.cfi_endproc
 2764              	.LFE55:
 2766              		.section	.text.PWR_OPA_BiasCurrentSel,"ax",%progbits
 2767              		.align	1
 2768              		.p2align 2,,3
 2769              		.global	PWR_OPA_BiasCurrentSel
 2770              		.syntax unified
 2771              		.code	16
 2772              		.thumb_func
 2774              	PWR_OPA_BiasCurrentSel:
 2775              	.LVL62:
 2776              	.LFB56:
 352:Library/src/lcm32f06x_pwr.c ****     if(OPAx == OPA0)
 2777              		.loc 1 352 1 is_stmt 1 view -0
 2778              		.cfi_startproc
 2779              		@ args = 0, pretend = 0, frame = 0
 2780              		@ frame_needed = 0, uses_anonymous_args = 0
 2781              		@ link register save eliminated.
 353:Library/src/lcm32f06x_pwr.c ****     {
 2782              		.loc 1 353 5 view .LVU752
 353:Library/src/lcm32f06x_pwr.c ****     {
 2783              		.loc 1 353 7 is_stmt 0 view .LVU753
 2784 0000 1E4B     		ldr	r3, .L63
 2785 0002 9842     		cmp	r0, r3
 2786 0004 1BD0     		beq	.L60
 359:Library/src/lcm32f06x_pwr.c ****     {
 2787              		.loc 1 359 10 is_stmt 1 view .LVU754
 359:Library/src/lcm32f06x_pwr.c ****     {
 2788              		.loc 1 359 12 is_stmt 0 view .LVU755
 2789 0006 1E4B     		ldr	r3, .L63+4
 2790 0008 9842     		cmp	r0, r3
 2791 000a 03D0     		beq	.L61
 365:Library/src/lcm32f06x_pwr.c ****     {
 2792              		.loc 1 365 10 is_stmt 1 view .LVU756
ARM GAS  /tmp/cckWj3Ij.s 			page 91


 365:Library/src/lcm32f06x_pwr.c ****     {
 2793              		.loc 1 365 12 is_stmt 0 view .LVU757
 2794 000c 1D4B     		ldr	r3, .L63+8
 2795 000e 9842     		cmp	r0, r3
 2796 0010 28D0     		beq	.L62
 2797              	.LVL63:
 2798              	.L55:
 371:Library/src/lcm32f06x_pwr.c **** #elif defined (LCM32F062)
 2799              		.loc 1 371 1 view .LVU758
 2800              		@ sp needed
 2801 0012 7047     		bx	lr
 2802              	.LVL64:
 2803              	.L61:
 361:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 2804              		.loc 1 361 7 is_stmt 1 view .LVU759
 2805              	.LBB710:
 2806              	.LBI710:
 258:Core/cmsis_gcc.h **** {
 2807              		.loc 2 258 27 view .LVU760
 2808              	.LBB711:
 260:Core/cmsis_gcc.h **** }
 2809              		.loc 2 260 3 view .LVU761
 2810              		.syntax divided
 2811              	@ 260 "Core/cmsis_gcc.h" 1
 2812 0014 BFF36F8F 		isb 0xF
 2813              	@ 0 "" 2
 2814              		.thumb
 2815              		.syntax unified
 2816              	.LBE711:
 2817              	.LBE710:
 361:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 2818              		.loc 1 361 7 discriminator 1 view .LVU762
 2819              	.LBB712:
 2820              	.LBI712:
1204:Core/cmsis_gcc.h **** {
 2821              		.loc 2 1204 31 view .LVU763
 2822              	.LBB713:
1206:Core/cmsis_gcc.h **** 
 2823              		.loc 2 1206 3 view .LVU764
1208:Core/cmsis_gcc.h ****   return(result);
 2824              		.loc 2 1208 3 view .LVU765
 2825              		.syntax divided
 2826              	@ 1208 "Core/cmsis_gcc.h" 1
 2827 0018 EFF31083 		MRS r3, primask
 2828              	@ 0 "" 2
 2829              	.LVL65:
 2830              		.loc 2 1209 3 view .LVU766
 2831              		.loc 2 1209 3 is_stmt 0 view .LVU767
 2832              		.thumb
 2833              		.syntax unified
 2834              	.LBE713:
 2835              	.LBE712:
 361:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 2836              		.loc 1 361 7 is_stmt 1 discriminator 2 view .LVU768
 2837              	.LBB714:
 2838              	.LBI714:
 960:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/cckWj3Ij.s 			page 92


 2839              		.loc 2 960 27 view .LVU769
 2840              	.LBB715:
 962:Core/cmsis_gcc.h **** }
 2841              		.loc 2 962 3 view .LVU770
 2842              		.syntax divided
 2843              	@ 962 "Core/cmsis_gcc.h" 1
 2844 001c 72B6     		cpsid i
 2845              	@ 0 "" 2
 2846              		.thumb
 2847              		.syntax unified
 2848              	.LBE715:
 2849              	.LBE714:
 361:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 2850              		.loc 1 361 7 discriminator 3 view .LVU771
 2851 001e 1A4B     		ldr	r3, .L63+12
 2852 0020 1A4A     		ldr	r2, .L63+16
 2853 0022 1A60     		str	r2, [r3]
 361:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 1;
 2854              		.loc 1 361 24 discriminator 3 view .LVU772
 362:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2855              		.loc 1 362 7 view .LVU773
 362:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2856              		.loc 1 362 50 is_stmt 0 view .LVU774
 2857 0024 0723     		movs	r3, #7
 2858 0026 1940     		ands	r1, r3
 2859              	.LVL66:
 362:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2860              		.loc 1 362 50 view .LVU775
 2861 0028 4900     		lsls	r1, r1, #1
 2862              	.L59:
 368:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2863              		.loc 1 368 35 view .LVU776
 2864 002a 1948     		ldr	r0, .L63+20
 2865              	.LVL67:
 368:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2866              		.loc 1 368 35 view .LVU777
 2867 002c 0B40     		ands	r3, r1
 2868 002e 4268     		ldr	r2, [r0, #4]
 2869 0030 1849     		ldr	r1, .L63+24
 2870 0032 1B07     		lsls	r3, r3, #28
 2871 0034 0A40     		ands	r2, r1
 2872 0036 1343     		orrs	r3, r2
 2873 0038 4360     		str	r3, [r0, #4]
 369:Library/src/lcm32f06x_pwr.c ****     }
 2874              		.loc 1 369 7 is_stmt 1 view .LVU778
 2875              	.LBB716:
 2876              	.LBI716:
 949:Core/cmsis_gcc.h **** {
 2877              		.loc 2 949 27 view .LVU779
 2878              	.LBB717:
 951:Core/cmsis_gcc.h **** }
 2879              		.loc 2 951 3 view .LVU780
 2880              		.syntax divided
 2881              	@ 951 "Core/cmsis_gcc.h" 1
 2882 003a 62B6     		cpsie i
 2883              	@ 0 "" 2
 2884              		.thumb
ARM GAS  /tmp/cckWj3Ij.s 			page 93


 2885              		.syntax unified
 2886              	.LBE717:
 2887              	.LBE716:
 369:Library/src/lcm32f06x_pwr.c ****     }
 2888              		.loc 1 369 16 view .LVU781
 371:Library/src/lcm32f06x_pwr.c **** #elif defined (LCM32F062)
 2889              		.loc 1 371 1 is_stmt 0 view .LVU782
 2890 003c E9E7     		b	.L55
 2891              	.LVL68:
 2892              	.L60:
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2893              		.loc 1 355 7 is_stmt 1 view .LVU783
 2894              	.LBB718:
 2895              	.LBI718:
 258:Core/cmsis_gcc.h **** {
 2896              		.loc 2 258 27 view .LVU784
 2897              	.LBB719:
 260:Core/cmsis_gcc.h **** }
 2898              		.loc 2 260 3 view .LVU785
 2899              		.syntax divided
 2900              	@ 260 "Core/cmsis_gcc.h" 1
 2901 003e BFF36F8F 		isb 0xF
 2902              	@ 0 "" 2
 2903              		.thumb
 2904              		.syntax unified
 2905              	.LBE719:
 2906              	.LBE718:
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2907              		.loc 1 355 7 discriminator 1 view .LVU786
 2908              	.LBB720:
 2909              	.LBI720:
1204:Core/cmsis_gcc.h **** {
 2910              		.loc 2 1204 31 view .LVU787
 2911              	.LBB721:
1206:Core/cmsis_gcc.h **** 
 2912              		.loc 2 1206 3 view .LVU788
1208:Core/cmsis_gcc.h ****   return(result);
 2913              		.loc 2 1208 3 view .LVU789
 2914              		.syntax divided
 2915              	@ 1208 "Core/cmsis_gcc.h" 1
 2916 0042 EFF31083 		MRS r3, primask
 2917              	@ 0 "" 2
 2918              	.LVL69:
 2919              		.loc 2 1209 3 view .LVU790
 2920              		.loc 2 1209 3 is_stmt 0 view .LVU791
 2921              		.thumb
 2922              		.syntax unified
 2923              	.LBE721:
 2924              	.LBE720:
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2925              		.loc 1 355 7 is_stmt 1 discriminator 2 view .LVU792
 2926              	.LBB722:
 2927              	.LBI722:
 960:Core/cmsis_gcc.h **** {
 2928              		.loc 2 960 27 view .LVU793
 2929              	.LBB723:
 962:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 94


 2930              		.loc 2 962 3 view .LVU794
 2931              		.syntax divided
 2932              	@ 962 "Core/cmsis_gcc.h" 1
 2933 0046 72B6     		cpsid i
 2934              	@ 0 "" 2
 2935              		.thumb
 2936              		.syntax unified
 2937              	.LBE723:
 2938              	.LBE722:
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2939              		.loc 1 355 7 discriminator 3 view .LVU795
 2940 0048 0F4B     		ldr	r3, .L63+12
 2941 004a 104A     		ldr	r2, .L63+16
 356:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2942              		.loc 1 356 35 is_stmt 0 view .LVU796
 2943 004c 1048     		ldr	r0, .L63+20
 2944              	.LVL70:
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2945              		.loc 1 355 7 discriminator 3 view .LVU797
 2946 004e 1A60     		str	r2, [r3]
 355:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 0;
 2947              		.loc 1 355 24 is_stmt 1 discriminator 3 view .LVU798
 356:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2948              		.loc 1 356 7 view .LVU799
 356:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2949              		.loc 1 356 35 is_stmt 0 view .LVU800
 2950 0050 0722     		movs	r2, #7
 2951 0052 4368     		ldr	r3, [r0, #4]
 2952 0054 0A40     		ands	r2, r1
 2953 0056 0F49     		ldr	r1, .L63+24
 2954              	.LVL71:
 356:Library/src/lcm32f06x_pwr.c ****       __dekey();
 2955              		.loc 1 356 35 view .LVU801
 2956 0058 1207     		lsls	r2, r2, #28
 2957 005a 0B40     		ands	r3, r1
 2958 005c 1343     		orrs	r3, r2
 2959 005e 4360     		str	r3, [r0, #4]
 357:Library/src/lcm32f06x_pwr.c ****     }
 2960              		.loc 1 357 7 is_stmt 1 view .LVU802
 2961              	.LBB724:
 2962              	.LBI724:
 949:Core/cmsis_gcc.h **** {
 2963              		.loc 2 949 27 view .LVU803
 2964              	.LBB725:
 951:Core/cmsis_gcc.h **** }
 2965              		.loc 2 951 3 view .LVU804
 2966              		.syntax divided
 2967              	@ 951 "Core/cmsis_gcc.h" 1
 2968 0060 62B6     		cpsie i
 2969              	@ 0 "" 2
 2970              		.thumb
 2971              		.syntax unified
 2972              	.LBE725:
 2973              	.LBE724:
 357:Library/src/lcm32f06x_pwr.c ****     }
 2974              		.loc 1 357 16 discriminator 1 view .LVU805
 2975              	.LBB727:
ARM GAS  /tmp/cckWj3Ij.s 			page 95


 2976              	.LBB726:
 952:Core/cmsis_gcc.h **** 
 2977              		.loc 2 952 1 is_stmt 0 view .LVU806
 2978 0062 D6E7     		b	.L55
 2979              	.LVL72:
 2980              	.L62:
 952:Core/cmsis_gcc.h **** 
 2981              		.loc 2 952 1 view .LVU807
 2982              	.LBE726:
 2983              	.LBE727:
 367:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 2984              		.loc 1 367 7 is_stmt 1 view .LVU808
 2985              	.LBB728:
 2986              	.LBI728:
 258:Core/cmsis_gcc.h **** {
 2987              		.loc 2 258 27 view .LVU809
 2988              	.LBB729:
 260:Core/cmsis_gcc.h **** }
 2989              		.loc 2 260 3 view .LVU810
 2990              		.syntax divided
 2991              	@ 260 "Core/cmsis_gcc.h" 1
 2992 0064 BFF36F8F 		isb 0xF
 2993              	@ 0 "" 2
 2994              		.thumb
 2995              		.syntax unified
 2996              	.LBE729:
 2997              	.LBE728:
 367:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 2998              		.loc 1 367 7 discriminator 1 view .LVU811
 2999              	.LBB730:
 3000              	.LBI730:
1204:Core/cmsis_gcc.h **** {
 3001              		.loc 2 1204 31 view .LVU812
 3002              	.LBB731:
1206:Core/cmsis_gcc.h **** 
 3003              		.loc 2 1206 3 view .LVU813
1208:Core/cmsis_gcc.h ****   return(result);
 3004              		.loc 2 1208 3 view .LVU814
 3005              		.syntax divided
 3006              	@ 1208 "Core/cmsis_gcc.h" 1
 3007 0068 EFF31083 		MRS r3, primask
 3008              	@ 0 "" 2
 3009              	.LVL73:
 3010              		.loc 2 1209 3 view .LVU815
 3011              		.loc 2 1209 3 is_stmt 0 view .LVU816
 3012              		.thumb
 3013              		.syntax unified
 3014              	.LBE731:
 3015              	.LBE730:
 367:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 3016              		.loc 1 367 7 is_stmt 1 discriminator 2 view .LVU817
 3017              	.LBB732:
 3018              	.LBI732:
 960:Core/cmsis_gcc.h **** {
 3019              		.loc 2 960 27 view .LVU818
 3020              	.LBB733:
 962:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/cckWj3Ij.s 			page 96


 3021              		.loc 2 962 3 view .LVU819
 3022              		.syntax divided
 3023              	@ 962 "Core/cmsis_gcc.h" 1
 3024 006c 72B6     		cpsid i
 3025              	@ 0 "" 2
 3026              		.thumb
 3027              		.syntax unified
 3028              	.LBE733:
 3029              	.LBE732:
 367:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 3030              		.loc 1 367 7 discriminator 3 view .LVU820
 3031 006e 064B     		ldr	r3, .L63+12
 3032 0070 064A     		ldr	r2, .L63+16
 3033 0072 1A60     		str	r2, [r3]
 367:Library/src/lcm32f06x_pwr.c ****       CHIPCTRL->PWR_CFG_b.OP_ISEL = Bisa_current << 2;
 3034              		.loc 1 367 24 discriminator 3 view .LVU821
 368:Library/src/lcm32f06x_pwr.c ****       __dekey();
 3035              		.loc 1 368 7 view .LVU822
 368:Library/src/lcm32f06x_pwr.c ****       __dekey();
 3036              		.loc 1 368 50 is_stmt 0 view .LVU823
 3037 0074 0723     		movs	r3, #7
 3038 0076 1940     		ands	r1, r3
 3039              	.LVL74:
 368:Library/src/lcm32f06x_pwr.c ****       __dekey();
 3040              		.loc 1 368 50 view .LVU824
 3041 0078 8900     		lsls	r1, r1, #2
 3042 007a D6E7     		b	.L59
 3043              	.L64:
 3044              		.align	2
 3045              	.L63:
 3046 007c 007C0140 		.word	1073839104
 3047 0080 047C0140 		.word	1073839108
 3048 0084 087C0140 		.word	1073839112
 3049 0088 20700140 		.word	1073836064
 3050 008c 65432187 		.word	-2027863195
 3051 0090 00700140 		.word	1073836032
 3052 0094 FFFFFF8F 		.word	-1879048193
 3053              		.cfi_endproc
 3054              	.LFE56:
 3056              		.section	.text.PWR_LVRClearFlag,"ax",%progbits
 3057              		.align	1
 3058              		.p2align 2,,3
 3059              		.global	PWR_LVRClearFlag
 3060              		.syntax unified
 3061              		.code	16
 3062              		.thumb_func
 3064              	PWR_LVRClearFlag:
 3065              	.LFB57:
 383:Library/src/lcm32f06x_pwr.c ****   assert_param();
 3066              		.loc 1 383 1 is_stmt 1 view -0
 3067              		.cfi_startproc
 3068              		@ args = 0, pretend = 0, frame = 0
 3069              		@ frame_needed = 0, uses_anonymous_args = 0
 3070              		@ link register save eliminated.
 384:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 3071              		.loc 1 384 3 view .LVU826
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
ARM GAS  /tmp/cckWj3Ij.s 			page 97


 3072              		.loc 1 385 3 view .LVU827
 3073              	.LBB734:
 3074              	.LBI734:
 258:Core/cmsis_gcc.h **** {
 3075              		.loc 2 258 27 view .LVU828
 3076              	.LBB735:
 260:Core/cmsis_gcc.h **** }
 3077              		.loc 2 260 3 view .LVU829
 3078              		.syntax divided
 3079              	@ 260 "Core/cmsis_gcc.h" 1
 3080 0000 BFF36F8F 		isb 0xF
 3081              	@ 0 "" 2
 3082              		.thumb
 3083              		.syntax unified
 3084              	.LBE735:
 3085              	.LBE734:
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 3086              		.loc 1 385 3 discriminator 1 view .LVU830
 3087              	.LBB736:
 3088              	.LBI736:
1204:Core/cmsis_gcc.h **** {
 3089              		.loc 2 1204 31 view .LVU831
 3090              	.LBB737:
1206:Core/cmsis_gcc.h **** 
 3091              		.loc 2 1206 3 view .LVU832
1208:Core/cmsis_gcc.h ****   return(result);
 3092              		.loc 2 1208 3 view .LVU833
 3093              		.syntax divided
 3094              	@ 1208 "Core/cmsis_gcc.h" 1
 3095 0004 EFF31083 		MRS r3, primask
 3096              	@ 0 "" 2
 3097              	.LVL75:
 3098              		.loc 2 1209 3 view .LVU834
 3099              		.loc 2 1209 3 is_stmt 0 view .LVU835
 3100              		.thumb
 3101              		.syntax unified
 3102              	.LBE737:
 3103              	.LBE736:
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 3104              		.loc 1 385 3 is_stmt 1 discriminator 2 view .LVU836
 3105              	.LBB738:
 3106              	.LBI738:
 960:Core/cmsis_gcc.h **** {
 3107              		.loc 2 960 27 view .LVU837
 3108              	.LBB739:
 962:Core/cmsis_gcc.h **** }
 3109              		.loc 2 962 3 view .LVU838
 3110              		.syntax divided
 3111              	@ 962 "Core/cmsis_gcc.h" 1
 3112 0008 72B6     		cpsid i
 3113              	@ 0 "" 2
 3114              		.thumb
 3115              		.syntax unified
 3116              	.LBE739:
 3117              	.LBE738:
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 3118              		.loc 1 385 3 discriminator 3 view .LVU839
ARM GAS  /tmp/cckWj3Ij.s 			page 98


 386:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3119              		.loc 1 386 32 is_stmt 0 view .LVU840
 3120 000a 0221     		movs	r1, #2
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 3121              		.loc 1 385 3 discriminator 3 view .LVU841
 3122 000c 044B     		ldr	r3, .L66
 3123 000e 054A     		ldr	r2, .L66+4
 3124 0010 1A60     		str	r2, [r3]
 385:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.LVR_FLAG = 1;
 3125              		.loc 1 385 20 is_stmt 1 discriminator 3 view .LVU842
 386:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3126              		.loc 1 386 3 view .LVU843
 386:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3127              		.loc 1 386 32 is_stmt 0 view .LVU844
 3128 0012 054A     		ldr	r2, .L66+8
 3129 0014 938B     		ldrh	r3, [r2, #28]
 3130 0016 0B43     		orrs	r3, r1
 3131 0018 9383     		strh	r3, [r2, #28]
 387:Library/src/lcm32f06x_pwr.c **** }
 3132              		.loc 1 387 3 is_stmt 1 view .LVU845
 3133              	.LBB740:
 3134              	.LBI740:
 949:Core/cmsis_gcc.h **** {
 3135              		.loc 2 949 27 view .LVU846
 3136              	.LBB741:
 951:Core/cmsis_gcc.h **** }
 3137              		.loc 2 951 3 view .LVU847
 3138              		.syntax divided
 3139              	@ 951 "Core/cmsis_gcc.h" 1
 3140 001a 62B6     		cpsie i
 3141              	@ 0 "" 2
 3142              		.thumb
 3143              		.syntax unified
 3144              	.LBE741:
 3145              	.LBE740:
 387:Library/src/lcm32f06x_pwr.c **** }
 3146              		.loc 1 387 12 discriminator 1 view .LVU848
 388:Library/src/lcm32f06x_pwr.c **** /**
 3147              		.loc 1 388 1 is_stmt 0 view .LVU849
 3148              		@ sp needed
 3149 001c 7047     		bx	lr
 3150              	.L67:
 3151 001e C046     		.align	2
 3152              	.L66:
 3153 0020 20700140 		.word	1073836064
 3154 0024 65432187 		.word	-2027863195
 3155 0028 00700140 		.word	1073836032
 3156              		.cfi_endproc
 3157              	.LFE57:
 3159              		.section	.text.PWR_POR_PDRClearFlag,"ax",%progbits
 3160              		.align	1
 3161              		.p2align 2,,3
 3162              		.global	PWR_POR_PDRClearFlag
 3163              		.syntax unified
 3164              		.code	16
 3165              		.thumb_func
 3167              	PWR_POR_PDRClearFlag:
ARM GAS  /tmp/cckWj3Ij.s 			page 99


 3168              	.LFB58:
 396:Library/src/lcm32f06x_pwr.c ****   assert_param();
 3169              		.loc 1 396 1 is_stmt 1 view -0
 3170              		.cfi_startproc
 3171              		@ args = 0, pretend = 0, frame = 0
 3172              		@ frame_needed = 0, uses_anonymous_args = 0
 3173              		@ link register save eliminated.
 397:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 3174              		.loc 1 397 3 view .LVU851
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3175              		.loc 1 398 3 view .LVU852
 3176              	.LBB742:
 3177              	.LBI742:
 258:Core/cmsis_gcc.h **** {
 3178              		.loc 2 258 27 view .LVU853
 3179              	.LBB743:
 260:Core/cmsis_gcc.h **** }
 3180              		.loc 2 260 3 view .LVU854
 3181              		.syntax divided
 3182              	@ 260 "Core/cmsis_gcc.h" 1
 3183 0000 BFF36F8F 		isb 0xF
 3184              	@ 0 "" 2
 3185              		.thumb
 3186              		.syntax unified
 3187              	.LBE743:
 3188              	.LBE742:
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3189              		.loc 1 398 3 discriminator 1 view .LVU855
 3190              	.LBB744:
 3191              	.LBI744:
1204:Core/cmsis_gcc.h **** {
 3192              		.loc 2 1204 31 view .LVU856
 3193              	.LBB745:
1206:Core/cmsis_gcc.h **** 
 3194              		.loc 2 1206 3 view .LVU857
1208:Core/cmsis_gcc.h ****   return(result);
 3195              		.loc 2 1208 3 view .LVU858
 3196              		.syntax divided
 3197              	@ 1208 "Core/cmsis_gcc.h" 1
 3198 0004 EFF31083 		MRS r3, primask
 3199              	@ 0 "" 2
 3200              	.LVL76:
 3201              		.loc 2 1209 3 view .LVU859
 3202              		.loc 2 1209 3 is_stmt 0 view .LVU860
 3203              		.thumb
 3204              		.syntax unified
 3205              	.LBE745:
 3206              	.LBE744:
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3207              		.loc 1 398 3 is_stmt 1 discriminator 2 view .LVU861
 3208              	.LBB746:
 3209              	.LBI746:
 960:Core/cmsis_gcc.h **** {
 3210              		.loc 2 960 27 view .LVU862
 3211              	.LBB747:
 962:Core/cmsis_gcc.h **** }
 3212              		.loc 2 962 3 view .LVU863
ARM GAS  /tmp/cckWj3Ij.s 			page 100


 3213              		.syntax divided
 3214              	@ 962 "Core/cmsis_gcc.h" 1
 3215 0008 72B6     		cpsid i
 3216              	@ 0 "" 2
 3217              		.thumb
 3218              		.syntax unified
 3219              	.LBE747:
 3220              	.LBE746:
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3221              		.loc 1 398 3 discriminator 3 view .LVU864
 399:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3222              		.loc 1 399 32 is_stmt 0 view .LVU865
 3223 000a 0121     		movs	r1, #1
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3224              		.loc 1 398 3 discriminator 3 view .LVU866
 3225 000c 044B     		ldr	r3, .L69
 3226 000e 054A     		ldr	r2, .L69+4
 3227 0010 1A60     		str	r2, [r3]
 398:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->RST_CSR_b.POR_FLAG = 1;
 3228              		.loc 1 398 20 is_stmt 1 discriminator 3 view .LVU867
 399:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3229              		.loc 1 399 3 view .LVU868
 399:Library/src/lcm32f06x_pwr.c ****   __dekey();
 3230              		.loc 1 399 32 is_stmt 0 view .LVU869
 3231 0012 054A     		ldr	r2, .L69+8
 3232 0014 938B     		ldrh	r3, [r2, #28]
 3233 0016 0B43     		orrs	r3, r1
 3234 0018 9383     		strh	r3, [r2, #28]
 400:Library/src/lcm32f06x_pwr.c **** }
 3235              		.loc 1 400 3 is_stmt 1 view .LVU870
 3236              	.LBB748:
 3237              	.LBI748:
 949:Core/cmsis_gcc.h **** {
 3238              		.loc 2 949 27 view .LVU871
 3239              	.LBB749:
 951:Core/cmsis_gcc.h **** }
 3240              		.loc 2 951 3 view .LVU872
 3241              		.syntax divided
 3242              	@ 951 "Core/cmsis_gcc.h" 1
 3243 001a 62B6     		cpsie i
 3244              	@ 0 "" 2
 3245              		.thumb
 3246              		.syntax unified
 3247              	.LBE749:
 3248              	.LBE748:
 400:Library/src/lcm32f06x_pwr.c **** }
 3249              		.loc 1 400 12 discriminator 1 view .LVU873
 401:Library/src/lcm32f06x_pwr.c **** 
 3250              		.loc 1 401 1 is_stmt 0 view .LVU874
 3251              		@ sp needed
 3252 001c 7047     		bx	lr
 3253              	.L70:
 3254 001e C046     		.align	2
 3255              	.L69:
 3256 0020 20700140 		.word	1073836064
 3257 0024 65432187 		.word	-2027863195
 3258 0028 00700140 		.word	1073836032
ARM GAS  /tmp/cckWj3Ij.s 			page 101


 3259              		.cfi_endproc
 3260              	.LFE58:
 3262              		.section	.text.PWR_UltraLowPowerDeepSleep,"ax",%progbits
 3263              		.align	1
 3264              		.p2align 2,,3
 3265              		.global	PWR_UltraLowPowerDeepSleep
 3266              		.syntax unified
 3267              		.code	16
 3268              		.thumb_func
 3270              	PWR_UltraLowPowerDeepSleep:
 3271              	.LVL77:
 3272              	.LFB59:
 415:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 3273              		.loc 1 415 1 is_stmt 1 view -0
 3274              		.cfi_startproc
 3275              		@ args = 0, pretend = 0, frame = 0
 3276              		@ frame_needed = 0, uses_anonymous_args = 0
 3277              		@ link register save eliminated.
 416:Library/src/lcm32f06x_pwr.c ****   {
 3278              		.loc 1 416 3 view .LVU876
 416:Library/src/lcm32f06x_pwr.c ****   {
 3279              		.loc 1 416 6 is_stmt 0 view .LVU877
 3280 0000 0028     		cmp	r0, #0
 3281 0002 0FD0     		beq	.L72
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3282              		.loc 1 418 5 is_stmt 1 view .LVU878
 3283              	.LBB750:
 3284              	.LBI750:
 258:Core/cmsis_gcc.h **** {
 3285              		.loc 2 258 27 view .LVU879
 3286              	.LBB751:
 260:Core/cmsis_gcc.h **** }
 3287              		.loc 2 260 3 view .LVU880
 3288              		.syntax divided
 3289              	@ 260 "Core/cmsis_gcc.h" 1
 3290 0004 BFF36F8F 		isb 0xF
 3291              	@ 0 "" 2
 3292              		.thumb
 3293              		.syntax unified
 3294              	.LBE751:
 3295              	.LBE750:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3296              		.loc 1 418 5 discriminator 1 view .LVU881
 3297              	.LBB752:
 3298              	.LBI752:
1204:Core/cmsis_gcc.h **** {
 3299              		.loc 2 1204 31 view .LVU882
 3300              	.LBB753:
1206:Core/cmsis_gcc.h **** 
 3301              		.loc 2 1206 3 view .LVU883
1208:Core/cmsis_gcc.h ****   return(result);
 3302              		.loc 2 1208 3 view .LVU884
 3303              		.syntax divided
 3304              	@ 1208 "Core/cmsis_gcc.h" 1
 3305 0008 EFF31083 		MRS r3, primask
 3306              	@ 0 "" 2
 3307              	.LVL78:
ARM GAS  /tmp/cckWj3Ij.s 			page 102


 3308              		.loc 2 1209 3 view .LVU885
 3309              		.loc 2 1209 3 is_stmt 0 view .LVU886
 3310              		.thumb
 3311              		.syntax unified
 3312              	.LBE753:
 3313              	.LBE752:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3314              		.loc 1 418 5 is_stmt 1 discriminator 2 view .LVU887
 3315              	.LBB754:
 3316              	.LBI754:
 960:Core/cmsis_gcc.h **** {
 3317              		.loc 2 960 27 view .LVU888
 3318              	.LBB755:
 962:Core/cmsis_gcc.h **** }
 3319              		.loc 2 962 3 view .LVU889
 3320              		.syntax divided
 3321              	@ 962 "Core/cmsis_gcc.h" 1
 3322 000c 72B6     		cpsid i
 3323              	@ 0 "" 2
 3324              		.thumb
 3325              		.syntax unified
 3326              	.LBE755:
 3327              	.LBE754:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3328              		.loc 1 418 5 discriminator 3 view .LVU890
 3329 000e 0D4B     		ldr	r3, .L74
 3330 0010 0D4A     		ldr	r2, .L74+4
 419:Library/src/lcm32f06x_pwr.c ****   }
 3331              		.loc 1 419 30 is_stmt 0 view .LVU891
 3332 0012 1020     		movs	r0, #16
 3333              	.LVL79:
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3334              		.loc 1 418 5 discriminator 3 view .LVU892
 3335 0014 1A60     		str	r2, [r3]
 418:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 1;
 3336              		.loc 1 418 22 is_stmt 1 discriminator 3 view .LVU893
 419:Library/src/lcm32f06x_pwr.c ****   }
 3337              		.loc 1 419 5 view .LVU894
 419:Library/src/lcm32f06x_pwr.c ****   }
 3338              		.loc 1 419 30 is_stmt 0 view .LVU895
 3339 0016 3022     		movs	r2, #48
 3340 0018 0C49     		ldr	r1, .L74+8
 3341 001a 8B5C     		ldrb	r3, [r1, r2]
 3342 001c 0343     		orrs	r3, r0
 3343 001e 8B54     		strb	r3, [r1, r2]
 3344              	.L73:
 426:Library/src/lcm32f06x_pwr.c **** }
 3345              		.loc 1 426 3 is_stmt 1 view .LVU896
 3346              	.LBB756:
 3347              	.LBI756:
 949:Core/cmsis_gcc.h **** {
 3348              		.loc 2 949 27 view .LVU897
 3349              	.LBB757:
 951:Core/cmsis_gcc.h **** }
 3350              		.loc 2 951 3 view .LVU898
 3351              		.syntax divided
 3352              	@ 951 "Core/cmsis_gcc.h" 1
ARM GAS  /tmp/cckWj3Ij.s 			page 103


 3353 0020 62B6     		cpsie i
 3354              	@ 0 "" 2
 3355              		.thumb
 3356              		.syntax unified
 3357              	.LBE757:
 3358              	.LBE756:
 426:Library/src/lcm32f06x_pwr.c **** }
 3359              		.loc 1 426 12 discriminator 1 view .LVU899
 427:Library/src/lcm32f06x_pwr.c **** 
 3360              		.loc 1 427 1 is_stmt 0 view .LVU900
 3361              		@ sp needed
 3362 0022 7047     		bx	lr
 3363              	.LVL80:
 3364              	.L72:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3365              		.loc 1 423 5 is_stmt 1 view .LVU901
 3366              	.LBB758:
 3367              	.LBI758:
 258:Core/cmsis_gcc.h **** {
 3368              		.loc 2 258 27 view .LVU902
 3369              	.LBB759:
 260:Core/cmsis_gcc.h **** }
 3370              		.loc 2 260 3 view .LVU903
 3371              		.syntax divided
 3372              	@ 260 "Core/cmsis_gcc.h" 1
 3373 0024 BFF36F8F 		isb 0xF
 3374              	@ 0 "" 2
 3375              		.thumb
 3376              		.syntax unified
 3377              	.LBE759:
 3378              	.LBE758:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3379              		.loc 1 423 5 discriminator 1 view .LVU904
 3380              	.LBB760:
 3381              	.LBI760:
1204:Core/cmsis_gcc.h **** {
 3382              		.loc 2 1204 31 view .LVU905
 3383              	.LBB761:
1206:Core/cmsis_gcc.h **** 
 3384              		.loc 2 1206 3 view .LVU906
1208:Core/cmsis_gcc.h ****   return(result);
 3385              		.loc 2 1208 3 view .LVU907
 3386              		.syntax divided
 3387              	@ 1208 "Core/cmsis_gcc.h" 1
 3388 0028 EFF31083 		MRS r3, primask
 3389              	@ 0 "" 2
 3390              	.LVL81:
 3391              		.loc 2 1209 3 view .LVU908
 3392              		.loc 2 1209 3 is_stmt 0 view .LVU909
 3393              		.thumb
 3394              		.syntax unified
 3395              	.LBE761:
 3396              	.LBE760:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3397              		.loc 1 423 5 is_stmt 1 discriminator 2 view .LVU910
 3398              	.LBB762:
 3399              	.LBI762:
ARM GAS  /tmp/cckWj3Ij.s 			page 104


 960:Core/cmsis_gcc.h **** {
 3400              		.loc 2 960 27 view .LVU911
 3401              	.LBB763:
 962:Core/cmsis_gcc.h **** }
 3402              		.loc 2 962 3 view .LVU912
 3403              		.syntax divided
 3404              	@ 962 "Core/cmsis_gcc.h" 1
 3405 002c 72B6     		cpsid i
 3406              	@ 0 "" 2
 3407              		.thumb
 3408              		.syntax unified
 3409              	.LBE763:
 3410              	.LBE762:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3411              		.loc 1 423 5 discriminator 3 view .LVU913
 3412 002e 054B     		ldr	r3, .L74
 3413 0030 054A     		ldr	r2, .L74+4
 424:Library/src/lcm32f06x_pwr.c ****   }
 3414              		.loc 1 424 30 is_stmt 0 view .LVU914
 3415 0032 1020     		movs	r0, #16
 3416              	.LVL82:
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3417              		.loc 1 423 5 discriminator 3 view .LVU915
 3418 0034 1A60     		str	r2, [r3]
 423:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.ULPDS = 0;
 3419              		.loc 1 423 22 is_stmt 1 discriminator 3 view .LVU916
 424:Library/src/lcm32f06x_pwr.c ****   }
 3420              		.loc 1 424 5 view .LVU917
 424:Library/src/lcm32f06x_pwr.c ****   }
 3421              		.loc 1 424 30 is_stmt 0 view .LVU918
 3422 0036 3022     		movs	r2, #48
 3423 0038 0449     		ldr	r1, .L74+8
 3424 003a 8B5C     		ldrb	r3, [r1, r2]
 3425 003c 8343     		bics	r3, r0
 3426 003e 8B54     		strb	r3, [r1, r2]
 3427 0040 EEE7     		b	.L73
 3428              	.L75:
 3429 0042 C046     		.align	2
 3430              	.L74:
 3431 0044 20700140 		.word	1073836064
 3432 0048 65432187 		.word	-2027863195
 3433 004c 00700140 		.word	1073836032
 3434              		.cfi_endproc
 3435              	.LFE59:
 3437              		.section	.text.PWR_FlashPowerDownDeepSleep,"ax",%progbits
 3438              		.align	1
 3439              		.p2align 2,,3
 3440              		.global	PWR_FlashPowerDownDeepSleep
 3441              		.syntax unified
 3442              		.code	16
 3443              		.thumb_func
 3445              	PWR_FlashPowerDownDeepSleep:
 3446              	.LVL83:
 3447              	.LFB60:
 441:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 3448              		.loc 1 441 1 is_stmt 1 view -0
 3449              		.cfi_startproc
ARM GAS  /tmp/cckWj3Ij.s 			page 105


 3450              		@ args = 0, pretend = 0, frame = 0
 3451              		@ frame_needed = 0, uses_anonymous_args = 0
 3452              		@ link register save eliminated.
 442:Library/src/lcm32f06x_pwr.c ****   {
 3453              		.loc 1 442 3 view .LVU920
 442:Library/src/lcm32f06x_pwr.c ****   {
 3454              		.loc 1 442 6 is_stmt 0 view .LVU921
 3455 0000 0028     		cmp	r0, #0
 3456 0002 0FD0     		beq	.L77
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3457              		.loc 1 444 5 is_stmt 1 view .LVU922
 3458              	.LBB764:
 3459              	.LBI764:
 258:Core/cmsis_gcc.h **** {
 3460              		.loc 2 258 27 view .LVU923
 3461              	.LBB765:
 260:Core/cmsis_gcc.h **** }
 3462              		.loc 2 260 3 view .LVU924
 3463              		.syntax divided
 3464              	@ 260 "Core/cmsis_gcc.h" 1
 3465 0004 BFF36F8F 		isb 0xF
 3466              	@ 0 "" 2
 3467              		.thumb
 3468              		.syntax unified
 3469              	.LBE765:
 3470              	.LBE764:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3471              		.loc 1 444 5 discriminator 1 view .LVU925
 3472              	.LBB766:
 3473              	.LBI766:
1204:Core/cmsis_gcc.h **** {
 3474              		.loc 2 1204 31 view .LVU926
 3475              	.LBB767:
1206:Core/cmsis_gcc.h **** 
 3476              		.loc 2 1206 3 view .LVU927
1208:Core/cmsis_gcc.h ****   return(result);
 3477              		.loc 2 1208 3 view .LVU928
 3478              		.syntax divided
 3479              	@ 1208 "Core/cmsis_gcc.h" 1
 3480 0008 EFF31083 		MRS r3, primask
 3481              	@ 0 "" 2
 3482              	.LVL84:
 3483              		.loc 2 1209 3 view .LVU929
 3484              		.loc 2 1209 3 is_stmt 0 view .LVU930
 3485              		.thumb
 3486              		.syntax unified
 3487              	.LBE767:
 3488              	.LBE766:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3489              		.loc 1 444 5 is_stmt 1 discriminator 2 view .LVU931
 3490              	.LBB768:
 3491              	.LBI768:
 960:Core/cmsis_gcc.h **** {
 3492              		.loc 2 960 27 view .LVU932
 3493              	.LBB769:
 962:Core/cmsis_gcc.h **** }
 3494              		.loc 2 962 3 view .LVU933
ARM GAS  /tmp/cckWj3Ij.s 			page 106


 3495              		.syntax divided
 3496              	@ 962 "Core/cmsis_gcc.h" 1
 3497 000c 72B6     		cpsid i
 3498              	@ 0 "" 2
 3499              		.thumb
 3500              		.syntax unified
 3501              	.LBE769:
 3502              	.LBE768:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3503              		.loc 1 444 5 discriminator 3 view .LVU934
 3504 000e 0D4B     		ldr	r3, .L79
 3505 0010 0D4A     		ldr	r2, .L79+4
 445:Library/src/lcm32f06x_pwr.c ****   }
 3506              		.loc 1 445 29 is_stmt 0 view .LVU935
 3507 0012 0820     		movs	r0, #8
 3508              	.LVL85:
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3509              		.loc 1 444 5 discriminator 3 view .LVU936
 3510 0014 1A60     		str	r2, [r3]
 444:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 1;
 3511              		.loc 1 444 22 is_stmt 1 discriminator 3 view .LVU937
 445:Library/src/lcm32f06x_pwr.c ****   }
 3512              		.loc 1 445 5 view .LVU938
 445:Library/src/lcm32f06x_pwr.c ****   }
 3513              		.loc 1 445 29 is_stmt 0 view .LVU939
 3514 0016 3022     		movs	r2, #48
 3515 0018 0C49     		ldr	r1, .L79+8
 3516 001a 8B5C     		ldrb	r3, [r1, r2]
 3517 001c 0343     		orrs	r3, r0
 3518 001e 8B54     		strb	r3, [r1, r2]
 3519              	.L78:
 452:Library/src/lcm32f06x_pwr.c **** }
 3520              		.loc 1 452 3 is_stmt 1 view .LVU940
 3521              	.LBB770:
 3522              	.LBI770:
 949:Core/cmsis_gcc.h **** {
 3523              		.loc 2 949 27 view .LVU941
 3524              	.LBB771:
 951:Core/cmsis_gcc.h **** }
 3525              		.loc 2 951 3 view .LVU942
 3526              		.syntax divided
 3527              	@ 951 "Core/cmsis_gcc.h" 1
 3528 0020 62B6     		cpsie i
 3529              	@ 0 "" 2
 3530              		.thumb
 3531              		.syntax unified
 3532              	.LBE771:
 3533              	.LBE770:
 452:Library/src/lcm32f06x_pwr.c **** }
 3534              		.loc 1 452 12 discriminator 1 view .LVU943
 453:Library/src/lcm32f06x_pwr.c **** 
 3535              		.loc 1 453 1 is_stmt 0 view .LVU944
 3536              		@ sp needed
 3537 0022 7047     		bx	lr
 3538              	.LVL86:
 3539              	.L77:
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
ARM GAS  /tmp/cckWj3Ij.s 			page 107


 3540              		.loc 1 449 5 is_stmt 1 view .LVU945
 3541              	.LBB772:
 3542              	.LBI772:
 258:Core/cmsis_gcc.h **** {
 3543              		.loc 2 258 27 view .LVU946
 3544              	.LBB773:
 260:Core/cmsis_gcc.h **** }
 3545              		.loc 2 260 3 view .LVU947
 3546              		.syntax divided
 3547              	@ 260 "Core/cmsis_gcc.h" 1
 3548 0024 BFF36F8F 		isb 0xF
 3549              	@ 0 "" 2
 3550              		.thumb
 3551              		.syntax unified
 3552              	.LBE773:
 3553              	.LBE772:
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 3554              		.loc 1 449 5 discriminator 1 view .LVU948
 3555              	.LBB774:
 3556              	.LBI774:
1204:Core/cmsis_gcc.h **** {
 3557              		.loc 2 1204 31 view .LVU949
 3558              	.LBB775:
1206:Core/cmsis_gcc.h **** 
 3559              		.loc 2 1206 3 view .LVU950
1208:Core/cmsis_gcc.h ****   return(result);
 3560              		.loc 2 1208 3 view .LVU951
 3561              		.syntax divided
 3562              	@ 1208 "Core/cmsis_gcc.h" 1
 3563 0028 EFF31083 		MRS r3, primask
 3564              	@ 0 "" 2
 3565              	.LVL87:
 3566              		.loc 2 1209 3 view .LVU952
 3567              		.loc 2 1209 3 is_stmt 0 view .LVU953
 3568              		.thumb
 3569              		.syntax unified
 3570              	.LBE775:
 3571              	.LBE774:
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 3572              		.loc 1 449 5 is_stmt 1 discriminator 2 view .LVU954
 3573              	.LBB776:
 3574              	.LBI776:
 960:Core/cmsis_gcc.h **** {
 3575              		.loc 2 960 27 view .LVU955
 3576              	.LBB777:
 962:Core/cmsis_gcc.h **** }
 3577              		.loc 2 962 3 view .LVU956
 3578              		.syntax divided
 3579              	@ 962 "Core/cmsis_gcc.h" 1
 3580 002c 72B6     		cpsid i
 3581              	@ 0 "" 2
 3582              		.thumb
 3583              		.syntax unified
 3584              	.LBE777:
 3585              	.LBE776:
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 3586              		.loc 1 449 5 discriminator 3 view .LVU957
ARM GAS  /tmp/cckWj3Ij.s 			page 108


 3587 002e 054B     		ldr	r3, .L79
 3588 0030 054A     		ldr	r2, .L79+4
 450:Library/src/lcm32f06x_pwr.c ****   }
 3589              		.loc 1 450 29 is_stmt 0 view .LVU958
 3590 0032 0820     		movs	r0, #8
 3591              	.LVL88:
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 3592              		.loc 1 449 5 discriminator 3 view .LVU959
 3593 0034 1A60     		str	r2, [r3]
 449:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.FPDS = 0;
 3594              		.loc 1 449 22 is_stmt 1 discriminator 3 view .LVU960
 450:Library/src/lcm32f06x_pwr.c ****   }
 3595              		.loc 1 450 5 view .LVU961
 450:Library/src/lcm32f06x_pwr.c ****   }
 3596              		.loc 1 450 29 is_stmt 0 view .LVU962
 3597 0036 3022     		movs	r2, #48
 3598 0038 0449     		ldr	r1, .L79+8
 3599 003a 8B5C     		ldrb	r3, [r1, r2]
 3600 003c 8343     		bics	r3, r0
 3601 003e 8B54     		strb	r3, [r1, r2]
 3602 0040 EEE7     		b	.L78
 3603              	.L80:
 3604 0042 C046     		.align	2
 3605              	.L79:
 3606 0044 20700140 		.word	1073836064
 3607 0048 65432187 		.word	-2027863195
 3608 004c 00700140 		.word	1073836032
 3609              		.cfi_endproc
 3610              	.LFE60:
 3612              		.section	.text.PWR_LowPowerCmd,"ax",%progbits
 3613              		.align	1
 3614              		.p2align 2,,3
 3615              		.global	PWR_LowPowerCmd
 3616              		.syntax unified
 3617              		.code	16
 3618              		.thumb_func
 3620              	PWR_LowPowerCmd:
 3621              	.LVL89:
 3622              	.LFB61:
 467:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 3623              		.loc 1 467 1 is_stmt 1 view -0
 3624              		.cfi_startproc
 3625              		@ args = 0, pretend = 0, frame = 0
 3626              		@ frame_needed = 0, uses_anonymous_args = 0
 3627              		@ link register save eliminated.
 468:Library/src/lcm32f06x_pwr.c ****   {
 3628              		.loc 1 468 3 view .LVU964
 468:Library/src/lcm32f06x_pwr.c ****   {
 3629              		.loc 1 468 6 is_stmt 0 view .LVU965
 3630 0000 0028     		cmp	r0, #0
 3631 0002 0FD0     		beq	.L82
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3632              		.loc 1 470 5 is_stmt 1 view .LVU966
 3633              	.LBB778:
 3634              	.LBI778:
 258:Core/cmsis_gcc.h **** {
 3635              		.loc 2 258 27 view .LVU967
ARM GAS  /tmp/cckWj3Ij.s 			page 109


 3636              	.LBB779:
 260:Core/cmsis_gcc.h **** }
 3637              		.loc 2 260 3 view .LVU968
 3638              		.syntax divided
 3639              	@ 260 "Core/cmsis_gcc.h" 1
 3640 0004 BFF36F8F 		isb 0xF
 3641              	@ 0 "" 2
 3642              		.thumb
 3643              		.syntax unified
 3644              	.LBE779:
 3645              	.LBE778:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3646              		.loc 1 470 5 discriminator 1 view .LVU969
 3647              	.LBB780:
 3648              	.LBI780:
1204:Core/cmsis_gcc.h **** {
 3649              		.loc 2 1204 31 view .LVU970
 3650              	.LBB781:
1206:Core/cmsis_gcc.h **** 
 3651              		.loc 2 1206 3 view .LVU971
1208:Core/cmsis_gcc.h ****   return(result);
 3652              		.loc 2 1208 3 view .LVU972
 3653              		.syntax divided
 3654              	@ 1208 "Core/cmsis_gcc.h" 1
 3655 0008 EFF31083 		MRS r3, primask
 3656              	@ 0 "" 2
 3657              	.LVL90:
 3658              		.loc 2 1209 3 view .LVU973
 3659              		.loc 2 1209 3 is_stmt 0 view .LVU974
 3660              		.thumb
 3661              		.syntax unified
 3662              	.LBE781:
 3663              	.LBE780:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3664              		.loc 1 470 5 is_stmt 1 discriminator 2 view .LVU975
 3665              	.LBB782:
 3666              	.LBI782:
 960:Core/cmsis_gcc.h **** {
 3667              		.loc 2 960 27 view .LVU976
 3668              	.LBB783:
 962:Core/cmsis_gcc.h **** }
 3669              		.loc 2 962 3 view .LVU977
 3670              		.syntax divided
 3671              	@ 962 "Core/cmsis_gcc.h" 1
 3672 000c 72B6     		cpsid i
 3673              	@ 0 "" 2
 3674              		.thumb
 3675              		.syntax unified
 3676              	.LBE783:
 3677              	.LBE782:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3678              		.loc 1 470 5 discriminator 3 view .LVU978
 3679 000e 0D4B     		ldr	r3, .L84
 3680 0010 0D4A     		ldr	r2, .L84+4
 471:Library/src/lcm32f06x_pwr.c ****   }
 3681              		.loc 1 471 30 is_stmt 0 view .LVU979
 3682 0012 0420     		movs	r0, #4
ARM GAS  /tmp/cckWj3Ij.s 			page 110


 3683              	.LVL91:
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3684              		.loc 1 470 5 discriminator 3 view .LVU980
 3685 0014 1A60     		str	r2, [r3]
 470:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 1;
 3686              		.loc 1 470 22 is_stmt 1 discriminator 3 view .LVU981
 471:Library/src/lcm32f06x_pwr.c ****   }
 3687              		.loc 1 471 5 view .LVU982
 471:Library/src/lcm32f06x_pwr.c ****   }
 3688              		.loc 1 471 30 is_stmt 0 view .LVU983
 3689 0016 3022     		movs	r2, #48
 3690 0018 0C49     		ldr	r1, .L84+8
 3691 001a 8B5C     		ldrb	r3, [r1, r2]
 3692 001c 0343     		orrs	r3, r0
 3693 001e 8B54     		strb	r3, [r1, r2]
 3694              	.L83:
 478:Library/src/lcm32f06x_pwr.c **** }
 3695              		.loc 1 478 3 is_stmt 1 view .LVU984
 3696              	.LBB784:
 3697              	.LBI784:
 949:Core/cmsis_gcc.h **** {
 3698              		.loc 2 949 27 view .LVU985
 3699              	.LBB785:
 951:Core/cmsis_gcc.h **** }
 3700              		.loc 2 951 3 view .LVU986
 3701              		.syntax divided
 3702              	@ 951 "Core/cmsis_gcc.h" 1
 3703 0020 62B6     		cpsie i
 3704              	@ 0 "" 2
 3705              		.thumb
 3706              		.syntax unified
 3707              	.LBE785:
 3708              	.LBE784:
 478:Library/src/lcm32f06x_pwr.c **** }
 3709              		.loc 1 478 12 discriminator 1 view .LVU987
 479:Library/src/lcm32f06x_pwr.c **** 
 3710              		.loc 1 479 1 is_stmt 0 view .LVU988
 3711              		@ sp needed
 3712 0022 7047     		bx	lr
 3713              	.LVL92:
 3714              	.L82:
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3715              		.loc 1 475 5 is_stmt 1 view .LVU989
 3716              	.LBB786:
 3717              	.LBI786:
 258:Core/cmsis_gcc.h **** {
 3718              		.loc 2 258 27 view .LVU990
 3719              	.LBB787:
 260:Core/cmsis_gcc.h **** }
 3720              		.loc 2 260 3 view .LVU991
 3721              		.syntax divided
 3722              	@ 260 "Core/cmsis_gcc.h" 1
 3723 0024 BFF36F8F 		isb 0xF
 3724              	@ 0 "" 2
 3725              		.thumb
 3726              		.syntax unified
 3727              	.LBE787:
ARM GAS  /tmp/cckWj3Ij.s 			page 111


 3728              	.LBE786:
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3729              		.loc 1 475 5 discriminator 1 view .LVU992
 3730              	.LBB788:
 3731              	.LBI788:
1204:Core/cmsis_gcc.h **** {
 3732              		.loc 2 1204 31 view .LVU993
 3733              	.LBB789:
1206:Core/cmsis_gcc.h **** 
 3734              		.loc 2 1206 3 view .LVU994
1208:Core/cmsis_gcc.h ****   return(result);
 3735              		.loc 2 1208 3 view .LVU995
 3736              		.syntax divided
 3737              	@ 1208 "Core/cmsis_gcc.h" 1
 3738 0028 EFF31083 		MRS r3, primask
 3739              	@ 0 "" 2
 3740              	.LVL93:
 3741              		.loc 2 1209 3 view .LVU996
 3742              		.loc 2 1209 3 is_stmt 0 view .LVU997
 3743              		.thumb
 3744              		.syntax unified
 3745              	.LBE789:
 3746              	.LBE788:
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3747              		.loc 1 475 5 is_stmt 1 discriminator 2 view .LVU998
 3748              	.LBB790:
 3749              	.LBI790:
 960:Core/cmsis_gcc.h **** {
 3750              		.loc 2 960 27 view .LVU999
 3751              	.LBB791:
 962:Core/cmsis_gcc.h **** }
 3752              		.loc 2 962 3 view .LVU1000
 3753              		.syntax divided
 3754              	@ 962 "Core/cmsis_gcc.h" 1
 3755 002c 72B6     		cpsid i
 3756              	@ 0 "" 2
 3757              		.thumb
 3758              		.syntax unified
 3759              	.LBE791:
 3760              	.LBE790:
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3761              		.loc 1 475 5 discriminator 3 view .LVU1001
 3762 002e 054B     		ldr	r3, .L84
 3763 0030 054A     		ldr	r2, .L84+4
 476:Library/src/lcm32f06x_pwr.c ****   }
 3764              		.loc 1 476 30 is_stmt 0 view .LVU1002
 3765 0032 0420     		movs	r0, #4
 3766              	.LVL94:
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3767              		.loc 1 475 5 discriminator 3 view .LVU1003
 3768 0034 1A60     		str	r2, [r3]
 475:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.PMUEN = 0;
 3769              		.loc 1 475 22 is_stmt 1 discriminator 3 view .LVU1004
 476:Library/src/lcm32f06x_pwr.c ****   }
 3770              		.loc 1 476 5 view .LVU1005
 476:Library/src/lcm32f06x_pwr.c ****   }
 3771              		.loc 1 476 30 is_stmt 0 view .LVU1006
ARM GAS  /tmp/cckWj3Ij.s 			page 112


 3772 0036 3022     		movs	r2, #48
 3773 0038 0449     		ldr	r1, .L84+8
 3774 003a 8B5C     		ldrb	r3, [r1, r2]
 3775 003c 8343     		bics	r3, r0
 3776 003e 8B54     		strb	r3, [r1, r2]
 3777 0040 EEE7     		b	.L83
 3778              	.L85:
 3779 0042 C046     		.align	2
 3780              	.L84:
 3781 0044 20700140 		.word	1073836064
 3782 0048 65432187 		.word	-2027863195
 3783 004c 00700140 		.word	1073836032
 3784              		.cfi_endproc
 3785              	.LFE61:
 3787              		.section	.text.PWR_LowPowerDeepSleep,"ax",%progbits
 3788              		.align	1
 3789              		.p2align 2,,3
 3790              		.global	PWR_LowPowerDeepSleep
 3791              		.syntax unified
 3792              		.code	16
 3793              		.thumb_func
 3795              	PWR_LowPowerDeepSleep:
 3796              	.LVL95:
 3797              	.LFB62:
 493:Library/src/lcm32f06x_pwr.c ****   if (NewState != DISABLE)
 3798              		.loc 1 493 1 is_stmt 1 view -0
 3799              		.cfi_startproc
 3800              		@ args = 0, pretend = 0, frame = 0
 3801              		@ frame_needed = 0, uses_anonymous_args = 0
 3802              		@ link register save eliminated.
 494:Library/src/lcm32f06x_pwr.c ****   {
 3803              		.loc 1 494 3 view .LVU1008
 494:Library/src/lcm32f06x_pwr.c ****   {
 3804              		.loc 1 494 6 is_stmt 0 view .LVU1009
 3805 0000 0028     		cmp	r0, #0
 3806 0002 0FD0     		beq	.L87
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3807              		.loc 1 496 5 is_stmt 1 view .LVU1010
 3808              	.LBB792:
 3809              	.LBI792:
 258:Core/cmsis_gcc.h **** {
 3810              		.loc 2 258 27 view .LVU1011
 3811              	.LBB793:
 260:Core/cmsis_gcc.h **** }
 3812              		.loc 2 260 3 view .LVU1012
 3813              		.syntax divided
 3814              	@ 260 "Core/cmsis_gcc.h" 1
 3815 0004 BFF36F8F 		isb 0xF
 3816              	@ 0 "" 2
 3817              		.thumb
 3818              		.syntax unified
 3819              	.LBE793:
 3820              	.LBE792:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3821              		.loc 1 496 5 discriminator 1 view .LVU1013
 3822              	.LBB794:
 3823              	.LBI794:
ARM GAS  /tmp/cckWj3Ij.s 			page 113


1204:Core/cmsis_gcc.h **** {
 3824              		.loc 2 1204 31 view .LVU1014
 3825              	.LBB795:
1206:Core/cmsis_gcc.h **** 
 3826              		.loc 2 1206 3 view .LVU1015
1208:Core/cmsis_gcc.h ****   return(result);
 3827              		.loc 2 1208 3 view .LVU1016
 3828              		.syntax divided
 3829              	@ 1208 "Core/cmsis_gcc.h" 1
 3830 0008 EFF31083 		MRS r3, primask
 3831              	@ 0 "" 2
 3832              	.LVL96:
 3833              		.loc 2 1209 3 view .LVU1017
 3834              		.loc 2 1209 3 is_stmt 0 view .LVU1018
 3835              		.thumb
 3836              		.syntax unified
 3837              	.LBE795:
 3838              	.LBE794:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3839              		.loc 1 496 5 is_stmt 1 discriminator 2 view .LVU1019
 3840              	.LBB796:
 3841              	.LBI796:
 960:Core/cmsis_gcc.h **** {
 3842              		.loc 2 960 27 view .LVU1020
 3843              	.LBB797:
 962:Core/cmsis_gcc.h **** }
 3844              		.loc 2 962 3 view .LVU1021
 3845              		.syntax divided
 3846              	@ 962 "Core/cmsis_gcc.h" 1
 3847 000c 72B6     		cpsid i
 3848              	@ 0 "" 2
 3849              		.thumb
 3850              		.syntax unified
 3851              	.LBE797:
 3852              	.LBE796:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3853              		.loc 1 496 5 discriminator 3 view .LVU1022
 3854 000e 0D4B     		ldr	r3, .L89
 3855 0010 0D4A     		ldr	r2, .L89+4
 497:Library/src/lcm32f06x_pwr.c ****   }
 3856              		.loc 1 497 29 is_stmt 0 view .LVU1023
 3857 0012 0120     		movs	r0, #1
 3858              	.LVL97:
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3859              		.loc 1 496 5 discriminator 3 view .LVU1024
 3860 0014 1A60     		str	r2, [r3]
 496:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 1;
 3861              		.loc 1 496 22 is_stmt 1 discriminator 3 view .LVU1025
 497:Library/src/lcm32f06x_pwr.c ****   }
 3862              		.loc 1 497 5 view .LVU1026
 497:Library/src/lcm32f06x_pwr.c ****   }
 3863              		.loc 1 497 29 is_stmt 0 view .LVU1027
 3864 0016 3022     		movs	r2, #48
 3865 0018 0C49     		ldr	r1, .L89+8
 3866 001a 8B5C     		ldrb	r3, [r1, r2]
 3867 001c 0343     		orrs	r3, r0
 3868 001e 8B54     		strb	r3, [r1, r2]
ARM GAS  /tmp/cckWj3Ij.s 			page 114


 3869              	.L88:
 3870              		.loc 1 504 3 is_stmt 1 view .LVU1028
 3871              	.LBB798:
 3872              	.LBI798:
 949:Core/cmsis_gcc.h **** {
 3873              		.loc 2 949 27 view .LVU1029
 3874              	.LBB799:
 951:Core/cmsis_gcc.h **** }
 3875              		.loc 2 951 3 view .LVU1030
 3876              		.syntax divided
 3877              	@ 951 "Core/cmsis_gcc.h" 1
 3878 0020 62B6     		cpsie i
 3879              	@ 0 "" 2
 3880              		.thumb
 3881              		.syntax unified
 3882              	.LBE799:
 3883              	.LBE798:
 3884              		.loc 1 504 12 discriminator 1 view .LVU1031
 505:Library/src/lcm32f06x_pwr.c **** }
 3885              		.loc 1 505 1 is_stmt 0 view .LVU1032
 3886              		@ sp needed
 3887 0022 7047     		bx	lr
 3888              	.LVL98:
 3889              	.L87:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3890              		.loc 1 501 5 is_stmt 1 view .LVU1033
 3891              	.LBB800:
 3892              	.LBI800:
 258:Core/cmsis_gcc.h **** {
 3893              		.loc 2 258 27 view .LVU1034
 3894              	.LBB801:
 260:Core/cmsis_gcc.h **** }
 3895              		.loc 2 260 3 view .LVU1035
 3896              		.syntax divided
 3897              	@ 260 "Core/cmsis_gcc.h" 1
 3898 0024 BFF36F8F 		isb 0xF
 3899              	@ 0 "" 2
 3900              		.thumb
 3901              		.syntax unified
 3902              	.LBE801:
 3903              	.LBE800:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3904              		.loc 1 501 5 discriminator 1 view .LVU1036
 3905              	.LBB802:
 3906              	.LBI802:
1204:Core/cmsis_gcc.h **** {
 3907              		.loc 2 1204 31 view .LVU1037
 3908              	.LBB803:
1206:Core/cmsis_gcc.h **** 
 3909              		.loc 2 1206 3 view .LVU1038
1208:Core/cmsis_gcc.h ****   return(result);
 3910              		.loc 2 1208 3 view .LVU1039
 3911              		.syntax divided
 3912              	@ 1208 "Core/cmsis_gcc.h" 1
 3913 0028 EFF31083 		MRS r3, primask
 3914              	@ 0 "" 2
 3915              	.LVL99:
ARM GAS  /tmp/cckWj3Ij.s 			page 115


 3916              		.loc 2 1209 3 view .LVU1040
 3917              		.loc 2 1209 3 is_stmt 0 view .LVU1041
 3918              		.thumb
 3919              		.syntax unified
 3920              	.LBE803:
 3921              	.LBE802:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3922              		.loc 1 501 5 is_stmt 1 discriminator 2 view .LVU1042
 3923              	.LBB804:
 3924              	.LBI804:
 960:Core/cmsis_gcc.h **** {
 3925              		.loc 2 960 27 view .LVU1043
 3926              	.LBB805:
 962:Core/cmsis_gcc.h **** }
 3927              		.loc 2 962 3 view .LVU1044
 3928              		.syntax divided
 3929              	@ 962 "Core/cmsis_gcc.h" 1
 3930 002c 72B6     		cpsid i
 3931              	@ 0 "" 2
 3932              		.thumb
 3933              		.syntax unified
 3934              	.LBE805:
 3935              	.LBE804:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3936              		.loc 1 501 5 discriminator 3 view .LVU1045
 3937 002e 054B     		ldr	r3, .L89
 3938 0030 054A     		ldr	r2, .L89+4
 502:Library/src/lcm32f06x_pwr.c ****   }
 3939              		.loc 1 502 29 is_stmt 0 view .LVU1046
 3940 0032 0120     		movs	r0, #1
 3941              	.LVL100:
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3942              		.loc 1 501 5 discriminator 3 view .LVU1047
 3943 0034 1A60     		str	r2, [r3]
 501:Library/src/lcm32f06x_pwr.c ****     CHIPCTRL->PWR_CR_b.LPDS = 0;
 3944              		.loc 1 501 22 is_stmt 1 discriminator 3 view .LVU1048
 502:Library/src/lcm32f06x_pwr.c ****   }
 3945              		.loc 1 502 5 view .LVU1049
 502:Library/src/lcm32f06x_pwr.c ****   }
 3946              		.loc 1 502 29 is_stmt 0 view .LVU1050
 3947 0036 3022     		movs	r2, #48
 3948 0038 0449     		ldr	r1, .L89+8
 3949 003a 8B5C     		ldrb	r3, [r1, r2]
 3950 003c 8343     		bics	r3, r0
 3951 003e 8B54     		strb	r3, [r1, r2]
 3952 0040 EEE7     		b	.L88
 3953              	.L90:
 3954 0042 C046     		.align	2
 3955              	.L89:
 3956 0044 20700140 		.word	1073836064
 3957 0048 65432187 		.word	-2027863195
 3958 004c 00700140 		.word	1073836032
 3959              		.cfi_endproc
 3960              	.LFE62:
 3962              		.section	.text.PWR_LDODriverLevel,"ax",%progbits
 3963              		.align	1
 3964              		.p2align 2,,3
ARM GAS  /tmp/cckWj3Ij.s 			page 116


 3965              		.global	PWR_LDODriverLevel
 3966              		.syntax unified
 3967              		.code	16
 3968              		.thumb_func
 3970              	PWR_LDODriverLevel:
 3971              	.LVL101:
 3972              	.LFB63:
 506:Library/src/lcm32f06x_pwr.c **** 
 507:Library/src/lcm32f06x_pwr.c **** /**
 508:Library/src/lcm32f06x_pwr.c ****   * @name   PWR_LDODriverLevel
 509:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: LDO output drive current capacity mode selection.
 510:Library/src/lcm32f06x_pwr.c ****   *         CN: LDO 输出驱动电流能力模式选择。
 511:Library/src/lcm32f06x_pwr.c ****   * @param  PWR_DRV: 
 512:Library/src/lcm32f06x_pwr.c ****   *         EN: Specify the LDO driver mode to be configured.
 513:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定要配置的LDO驱动模式。
 514:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_LDODRV_10uA
 515:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_LDODRV_50uA
 516:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_LDODRV_150uA
 517:Library/src/lcm32f06x_pwr.c ****   *             @arg PWR_LDODRV_200uA
 518:Library/src/lcm32f06x_pwr.c ****   * @retval None
 519:Library/src/lcm32f06x_pwr.c ****   */
 520:Library/src/lcm32f06x_pwr.c **** void PWR_LDODriverLevel(uint8_t PWR_DRV)
 521:Library/src/lcm32f06x_pwr.c **** {
 3973              		.loc 1 521 1 is_stmt 1 view -0
 3974              		.cfi_startproc
 3975              		@ args = 0, pretend = 0, frame = 0
 3976              		@ frame_needed = 0, uses_anonymous_args = 0
 522:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 3977              		.loc 1 522 3 view .LVU1052
 3978              	.LBB806:
 3979              	.LBI806:
 258:Core/cmsis_gcc.h **** {
 3980              		.loc 2 258 27 view .LVU1053
 3981              	.LBB807:
 260:Core/cmsis_gcc.h **** }
 3982              		.loc 2 260 3 view .LVU1054
 3983              	.LBE807:
 3984              	.LBE806:
 521:Library/src/lcm32f06x_pwr.c ****   chipctrl_access();
 3985              		.loc 1 521 1 is_stmt 0 view .LVU1055
 3986 0000 10B5     		push	{r4, lr}
 3987              	.LCFI5:
 3988              		.cfi_def_cfa_offset 8
 3989              		.cfi_offset 4, -8
 3990              		.cfi_offset 14, -4
 3991              	.LBB809:
 3992              	.LBB808:
 260:Core/cmsis_gcc.h **** }
 3993              		.loc 2 260 3 view .LVU1056
 3994              		.syntax divided
 3995              	@ 260 "Core/cmsis_gcc.h" 1
 3996 0002 BFF36F8F 		isb 0xF
 3997              	@ 0 "" 2
 3998              		.thumb
 3999              		.syntax unified
 4000              	.LBE808:
 4001              	.LBE809:
ARM GAS  /tmp/cckWj3Ij.s 			page 117


 4002              		.loc 1 522 3 is_stmt 1 discriminator 1 view .LVU1057
 4003              	.LBB810:
 4004              	.LBI810:
1204:Core/cmsis_gcc.h **** {
 4005              		.loc 2 1204 31 view .LVU1058
 4006              	.LBB811:
1206:Core/cmsis_gcc.h **** 
 4007              		.loc 2 1206 3 view .LVU1059
1208:Core/cmsis_gcc.h ****   return(result);
 4008              		.loc 2 1208 3 view .LVU1060
 4009              		.syntax divided
 4010              	@ 1208 "Core/cmsis_gcc.h" 1
 4011 0006 EFF31083 		MRS r3, primask
 4012              	@ 0 "" 2
 4013              	.LVL102:
 4014              		.loc 2 1209 3 view .LVU1061
 4015              		.loc 2 1209 3 is_stmt 0 view .LVU1062
 4016              		.thumb
 4017              		.syntax unified
 4018              	.LBE811:
 4019              	.LBE810:
 4020              		.loc 1 522 3 is_stmt 1 discriminator 2 view .LVU1063
 4021              	.LBB812:
 4022              	.LBI812:
 960:Core/cmsis_gcc.h **** {
 4023              		.loc 2 960 27 view .LVU1064
 4024              	.LBB813:
 962:Core/cmsis_gcc.h **** }
 4025              		.loc 2 962 3 view .LVU1065
 4026              		.syntax divided
 4027              	@ 962 "Core/cmsis_gcc.h" 1
 4028 000a 72B6     		cpsid i
 4029              	@ 0 "" 2
 4030              		.thumb
 4031              		.syntax unified
 4032              	.LBE813:
 4033              	.LBE812:
 4034              		.loc 1 522 3 discriminator 3 view .LVU1066
 4035 000c 074B     		ldr	r3, .L92
 4036 000e 084A     		ldr	r2, .L92+4
 523:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_LDOCR_b.DRV = PWR_DRV;
 4037              		.loc 1 523 29 is_stmt 0 view .LVU1067
 4038 0010 3C21     		movs	r1, #60
 522:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_LDOCR_b.DRV = PWR_DRV;
 4039              		.loc 1 522 3 discriminator 3 view .LVU1068
 4040 0012 1A60     		str	r2, [r3]
 522:Library/src/lcm32f06x_pwr.c ****   CHIPCTRL->PWR_LDOCR_b.DRV = PWR_DRV;
 4041              		.loc 1 522 20 is_stmt 1 discriminator 3 view .LVU1069
 4042              		.loc 1 523 3 view .LVU1070
 4043              		.loc 1 523 29 is_stmt 0 view .LVU1071
 4044 0014 0323     		movs	r3, #3
 4045 0016 0C24     		movs	r4, #12
 4046 0018 064A     		ldr	r2, .L92+8
 4047 001a 0340     		ands	r3, r0
 4048 001c 505C     		ldrb	r0, [r2, r1]
 4049              	.LVL103:
 4050              		.loc 1 523 29 view .LVU1072
ARM GAS  /tmp/cckWj3Ij.s 			page 118


 4051 001e 9B00     		lsls	r3, r3, #2
 4052 0020 A043     		bics	r0, r4
 4053 0022 1843     		orrs	r0, r3
 4054 0024 5054     		strb	r0, [r2, r1]
 524:Library/src/lcm32f06x_pwr.c ****   __dekey();
 4055              		.loc 1 524 3 is_stmt 1 view .LVU1073
 4056              	.LBB814:
 4057              	.LBI814:
 949:Core/cmsis_gcc.h **** {
 4058              		.loc 2 949 27 view .LVU1074
 4059              	.LBB815:
 951:Core/cmsis_gcc.h **** }
 4060              		.loc 2 951 3 view .LVU1075
 4061              		.syntax divided
 4062              	@ 951 "Core/cmsis_gcc.h" 1
 4063 0026 62B6     		cpsie i
 4064              	@ 0 "" 2
 4065              		.thumb
 4066              		.syntax unified
 4067              	.LBE815:
 4068              	.LBE814:
 4069              		.loc 1 524 12 discriminator 1 view .LVU1076
 525:Library/src/lcm32f06x_pwr.c **** }
 4070              		.loc 1 525 1 is_stmt 0 view .LVU1077
 4071              		@ sp needed
 4072 0028 10BD     		pop	{r4, pc}
 4073              	.L93:
 4074 002a C046     		.align	2
 4075              	.L92:
 4076 002c 20700140 		.word	1073836064
 4077 0030 65432187 		.word	-2027863195
 4078 0034 00700140 		.word	1073836032
 4079              		.cfi_endproc
 4080              	.LFE63:
 4082              		.section	.text.Chipctrl_ReadFLAG,"ax",%progbits
 4083              		.align	1
 4084              		.p2align 2,,3
 4085              		.global	Chipctrl_ReadFLAG
 4086              		.syntax unified
 4087              		.code	16
 4088              		.thumb_func
 4090              	Chipctrl_ReadFLAG:
 4091              	.LVL104:
 4092              	.LFB64:
 526:Library/src/lcm32f06x_pwr.c **** 
 527:Library/src/lcm32f06x_pwr.c **** /**
 528:Library/src/lcm32f06x_pwr.c ****   * @name   Chipctrl_ReadFLAG
 529:Library/src/lcm32f06x_pwr.c ****   * @brief  EN: Read LVR POR LVD flag.
 530:Library/src/lcm32f06x_pwr.c ****   *         CN: 读取LVR POR LVD标志。
 531:Library/src/lcm32f06x_pwr.c ****   * @param  FLAG: 
 532:Library/src/lcm32f06x_pwr.c ****   *         EN: Specify the system status flag to be read.
 533:Library/src/lcm32f06x_pwr.c ****   *         CN: 指定要读取的系统状态标志。
 534:Library/src/lcm32f06x_pwr.c ****   *             @arg ChipCtrl_FLAG_LVD
 535:Library/src/lcm32f06x_pwr.c ****   *             @arg ChipCtrl_FLAG_LVR
 536:Library/src/lcm32f06x_pwr.c ****   *             @arg ChipCtrl_FLAG_POR
 537:Library/src/lcm32f06x_pwr.c ****   * @retval None
 538:Library/src/lcm32f06x_pwr.c ****   */
ARM GAS  /tmp/cckWj3Ij.s 			page 119


 539:Library/src/lcm32f06x_pwr.c **** uint8_t Chipctrl_ReadFLAG(uint32_t FLAG)
 540:Library/src/lcm32f06x_pwr.c **** {
 4093              		.loc 1 540 1 is_stmt 1 view -0
 4094              		.cfi_startproc
 4095              		@ args = 0, pretend = 0, frame = 0
 4096              		@ frame_needed = 0, uses_anonymous_args = 0
 4097              		@ link register save eliminated.
 541:Library/src/lcm32f06x_pwr.c ****   uint8_t status = 0x00;
 4098              		.loc 1 541 3 view .LVU1079
 542:Library/src/lcm32f06x_pwr.c **** 
 543:Library/src/lcm32f06x_pwr.c ****   /* Check the parameters */
 544:Library/src/lcm32f06x_pwr.c ****   assert_param(IS_ChipCtrl_FLAG(FLAG));
 4099              		.loc 1 544 3 view .LVU1080
 545:Library/src/lcm32f06x_pwr.c **** 
 546:Library/src/lcm32f06x_pwr.c ****   if (FLAG == ChipCtrl_FLAG_LVD)
 4100              		.loc 1 546 3 view .LVU1081
 540:Library/src/lcm32f06x_pwr.c ****   uint8_t status = 0x00;
 4101              		.loc 1 540 1 is_stmt 0 view .LVU1082
 4102 0000 0300     		movs	r3, r0
 4103              		.loc 1 546 6 view .LVU1083
 4104 0002 0128     		cmp	r0, #1
 4105 0004 0ED0     		beq	.L99
 547:Library/src/lcm32f06x_pwr.c ****   {
 548:Library/src/lcm32f06x_pwr.c ****     status = (uint8_t)CHIPCTRL->STS_b.LVDFLG;
 549:Library/src/lcm32f06x_pwr.c ****   }
 550:Library/src/lcm32f06x_pwr.c ****   else if (FLAG == ChipCtrl_FLAG_LVR)
 4106              		.loc 1 550 8 is_stmt 1 view .LVU1084
 4107              		.loc 1 550 11 is_stmt 0 view .LVU1085
 4108 0006 0228     		cmp	r0, #2
 4109 0008 07D0     		beq	.L100
 551:Library/src/lcm32f06x_pwr.c ****   {
 552:Library/src/lcm32f06x_pwr.c ****     status = (uint8_t)CHIPCTRL->RST_CSR_b.LVR_FLAG;
 553:Library/src/lcm32f06x_pwr.c ****     
 554:Library/src/lcm32f06x_pwr.c ****   }
 555:Library/src/lcm32f06x_pwr.c ****   else if (FLAG == ChipCtrl_FLAG_POR)
 4110              		.loc 1 555 8 is_stmt 1 view .LVU1086
 541:Library/src/lcm32f06x_pwr.c **** 
 4111              		.loc 1 541 11 is_stmt 0 view .LVU1087
 4112 000a 0020     		movs	r0, #0
 4113              	.LVL105:
 4114              		.loc 1 555 11 view .LVU1088
 4115 000c 032B     		cmp	r3, #3
 4116 000e 08D1     		bne	.L96
 556:Library/src/lcm32f06x_pwr.c ****   {
 557:Library/src/lcm32f06x_pwr.c ****     status = (uint8_t)CHIPCTRL->RST_CSR_b.POR_FLAG;
 4117              		.loc 1 557 5 is_stmt 1 view .LVU1089
 4118              		.loc 1 557 42 is_stmt 0 view .LVU1090
 4119 0010 074B     		ldr	r3, .L101
 4120              	.LVL106:
 4121              		.loc 1 557 42 view .LVU1091
 4122 0012 D869     		ldr	r0, [r3, #28]
 4123 0014 C007     		lsls	r0, r0, #31
 4124 0016 C00F     		lsrs	r0, r0, #31
 4125 0018 03E0     		b	.L96
 4126              	.LVL107:
 4127              	.L100:
 552:Library/src/lcm32f06x_pwr.c ****     
ARM GAS  /tmp/cckWj3Ij.s 			page 120


 4128              		.loc 1 552 5 is_stmt 1 view .LVU1092
 552:Library/src/lcm32f06x_pwr.c ****     
 4129              		.loc 1 552 42 is_stmt 0 view .LVU1093
 4130 001a 054B     		ldr	r3, .L101
 4131 001c D869     		ldr	r0, [r3, #28]
 4132              	.LVL108:
 552:Library/src/lcm32f06x_pwr.c ****     
 4133              		.loc 1 552 42 view .LVU1094
 4134 001e 8007     		lsls	r0, r0, #30
 4135 0020 C00F     		lsrs	r0, r0, #31
 4136              	.LVL109:
 4137              	.L96:
 558:Library/src/lcm32f06x_pwr.c ****     
 559:Library/src/lcm32f06x_pwr.c ****   }
 560:Library/src/lcm32f06x_pwr.c ****   return status;
 4138              		.loc 1 560 3 is_stmt 1 view .LVU1095
 561:Library/src/lcm32f06x_pwr.c **** }
 4139              		.loc 1 561 1 is_stmt 0 view .LVU1096
 4140              		@ sp needed
 4141 0022 7047     		bx	lr
 4142              	.LVL110:
 4143              	.L99:
 548:Library/src/lcm32f06x_pwr.c ****   }
 4144              		.loc 1 548 5 is_stmt 1 view .LVU1097
 548:Library/src/lcm32f06x_pwr.c ****   }
 4145              		.loc 1 548 38 is_stmt 0 view .LVU1098
 4146 0024 024B     		ldr	r3, .L101
 4147 0026 9869     		ldr	r0, [r3, #24]
 4148              	.LVL111:
 548:Library/src/lcm32f06x_pwr.c ****   }
 4149              		.loc 1 548 38 view .LVU1099
 4150 0028 C001     		lsls	r0, r0, #7
 4151 002a C00F     		lsrs	r0, r0, #31
 4152              	.LVL112:
 548:Library/src/lcm32f06x_pwr.c ****   }
 4153              		.loc 1 548 38 view .LVU1100
 4154 002c F9E7     		b	.L96
 4155              	.L102:
 4156 002e C046     		.align	2
 4157              	.L101:
 4158 0030 00700140 		.word	1073836032
 4159              		.cfi_endproc
 4160              	.LFE64:
 4162              		.text
 4163              	.Letext0:
 4164              		.file 3 "Library/inc/lcm32f06x.h"
 4165              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 4166              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 4167              		.file 6 "Core/core_cm0.h"
ARM GAS  /tmp/cckWj3Ij.s 			page 121


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_pwr.c
     /tmp/cckWj3Ij.s:17     .text.PWR_EnterSleepMode:00000000 $t
     /tmp/cckWj3Ij.s:24     .text.PWR_EnterSleepMode:00000000 PWR_EnterSleepMode
     /tmp/cckWj3Ij.s:69     .text.PWR_EnterSleepMode:00000018 $d
     /tmp/cckWj3Ij.s:74     .text.PWR_EnterUR_STOPMode:00000000 $t
     /tmp/cckWj3Ij.s:81     .text.PWR_EnterUR_STOPMode:00000000 PWR_EnterUR_STOPMode
     /tmp/cckWj3Ij.s:487    .text.PWR_EnterUR_STOPMode:00000084 $d
     /tmp/cckWj3Ij.s:495    .text.PWR_EnterSTOPMode:00000000 $t
     /tmp/cckWj3Ij.s:502    .text.PWR_EnterSTOPMode:00000000 PWR_EnterSTOPMode
     /tmp/cckWj3Ij.s:904    .text.PWR_EnterSTOPMode:00000084 $d
     /tmp/cckWj3Ij.s:912    .text.PWR_EnterLowPowerSTOPMode:00000000 $t
     /tmp/cckWj3Ij.s:919    .text.PWR_EnterLowPowerSTOPMode:00000000 PWR_EnterLowPowerSTOPMode
     /tmp/cckWj3Ij.s:1321   .text.PWR_EnterLowPowerSTOPMode:00000084 $d
     /tmp/cckWj3Ij.s:1329   .text.PWR_EnterSTANDBYMode:00000000 $t
     /tmp/cckWj3Ij.s:1336   .text.PWR_EnterSTANDBYMode:00000000 PWR_EnterSTANDBYMode
     /tmp/cckWj3Ij.s:1713   .text.PWR_EnterSTANDBYMode:00000070 $d
     /tmp/cckWj3Ij.s:1721   .text.PWR_AOUTConfig:00000000 $t
     /tmp/cckWj3Ij.s:1728   .text.PWR_AOUTConfig:00000000 PWR_AOUTConfig
     /tmp/cckWj3Ij.s:1829   .text.PWR_AOUTConfig:00000028 $d
     /tmp/cckWj3Ij.s:1836   .text.PWR_AOUTcmd:00000000 $t
     /tmp/cckWj3Ij.s:1843   .text.PWR_AOUTcmd:00000000 PWR_AOUTcmd
     /tmp/cckWj3Ij.s:1998   .text.PWR_AOUTcmd:00000040 $d
     /tmp/cckWj3Ij.s:2006   .text.PWR_LVDConfig:00000000 $t
     /tmp/cckWj3Ij.s:2013   .text.PWR_LVDConfig:00000000 PWR_LVDConfig
     /tmp/cckWj3Ij.s:2303   .text.PWR_LVDConfig:00000078 $d
     /tmp/cckWj3Ij.s:2312   .text.PWR_LVDCmd:00000000 $t
     /tmp/cckWj3Ij.s:2319   .text.PWR_LVDCmd:00000000 PWR_LVDCmd
     /tmp/cckWj3Ij.s:2474   .text.PWR_LVDCmd:00000040 $d
     /tmp/cckWj3Ij.s:2482   .text.PWR_LVRConfig:00000000 $t
     /tmp/cckWj3Ij.s:2489   .text.PWR_LVRConfig:00000000 PWR_LVRConfig
     /tmp/cckWj3Ij.s:2590   .text.PWR_LVRConfig:00000028 $d
     /tmp/cckWj3Ij.s:2597   .text.PWR_LVRCmd:00000000 $t
     /tmp/cckWj3Ij.s:2604   .text.PWR_LVRCmd:00000000 PWR_LVRCmd
     /tmp/cckWj3Ij.s:2760   .text.PWR_LVRCmd:00000040 $d
     /tmp/cckWj3Ij.s:2767   .text.PWR_OPA_BiasCurrentSel:00000000 $t
     /tmp/cckWj3Ij.s:2774   .text.PWR_OPA_BiasCurrentSel:00000000 PWR_OPA_BiasCurrentSel
     /tmp/cckWj3Ij.s:3046   .text.PWR_OPA_BiasCurrentSel:0000007c $d
     /tmp/cckWj3Ij.s:3057   .text.PWR_LVRClearFlag:00000000 $t
     /tmp/cckWj3Ij.s:3064   .text.PWR_LVRClearFlag:00000000 PWR_LVRClearFlag
     /tmp/cckWj3Ij.s:3153   .text.PWR_LVRClearFlag:00000020 $d
     /tmp/cckWj3Ij.s:3160   .text.PWR_POR_PDRClearFlag:00000000 $t
     /tmp/cckWj3Ij.s:3167   .text.PWR_POR_PDRClearFlag:00000000 PWR_POR_PDRClearFlag
     /tmp/cckWj3Ij.s:3256   .text.PWR_POR_PDRClearFlag:00000020 $d
     /tmp/cckWj3Ij.s:3263   .text.PWR_UltraLowPowerDeepSleep:00000000 $t
     /tmp/cckWj3Ij.s:3270   .text.PWR_UltraLowPowerDeepSleep:00000000 PWR_UltraLowPowerDeepSleep
     /tmp/cckWj3Ij.s:3431   .text.PWR_UltraLowPowerDeepSleep:00000044 $d
     /tmp/cckWj3Ij.s:3438   .text.PWR_FlashPowerDownDeepSleep:00000000 $t
     /tmp/cckWj3Ij.s:3445   .text.PWR_FlashPowerDownDeepSleep:00000000 PWR_FlashPowerDownDeepSleep
     /tmp/cckWj3Ij.s:3606   .text.PWR_FlashPowerDownDeepSleep:00000044 $d
     /tmp/cckWj3Ij.s:3613   .text.PWR_LowPowerCmd:00000000 $t
     /tmp/cckWj3Ij.s:3620   .text.PWR_LowPowerCmd:00000000 PWR_LowPowerCmd
     /tmp/cckWj3Ij.s:3781   .text.PWR_LowPowerCmd:00000044 $d
     /tmp/cckWj3Ij.s:3788   .text.PWR_LowPowerDeepSleep:00000000 $t
     /tmp/cckWj3Ij.s:3795   .text.PWR_LowPowerDeepSleep:00000000 PWR_LowPowerDeepSleep
     /tmp/cckWj3Ij.s:3956   .text.PWR_LowPowerDeepSleep:00000044 $d
     /tmp/cckWj3Ij.s:3963   .text.PWR_LDODriverLevel:00000000 $t
ARM GAS  /tmp/cckWj3Ij.s 			page 122


     /tmp/cckWj3Ij.s:3970   .text.PWR_LDODriverLevel:00000000 PWR_LDODriverLevel
     /tmp/cckWj3Ij.s:4076   .text.PWR_LDODriverLevel:0000002c $d
     /tmp/cckWj3Ij.s:4083   .text.Chipctrl_ReadFLAG:00000000 $t
     /tmp/cckWj3Ij.s:4090   .text.Chipctrl_ReadFLAG:00000000 Chipctrl_ReadFLAG
     /tmp/cckWj3Ij.s:4158   .text.Chipctrl_ReadFLAG:00000030 $d

NO UNDEFINED SYMBOLS
