ARM GAS  /tmp/ccSm0G8b.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"bsp.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "User/bsp.c"
  16              		.section	.text.bsp_init,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	bsp_init
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	bsp_init:
  25              	.LFB45:
   1:User/bsp.c    **** #include "string.h"
   2:User/bsp.c    **** #include "stddef.h"
   3:User/bsp.c    **** #include "lcm32f06x_conf.h"
   4:User/bsp.c    **** 
   5:User/bsp.c    **** #include "dji.h"
   6:User/bsp.c    **** #include "task.h"
   7:User/bsp.c    **** #include "bsp.h"
   8:User/bsp.c    **** 
   9:User/bsp.c    **** #include "adc.h"
  10:User/bsp.c    **** #include "opa.h"
  11:User/bsp.c    **** #include "pwm.h"
  12:User/bsp.c    **** #include "uart.h"
  13:User/bsp.c    **** #include "flash.h"
  14:User/bsp.c    **** 
  15:User/bsp.c    **** #include "motor.h"
  16:User/bsp.c    **** #include "protocol.h"
  17:User/bsp.c    **** 
  18:User/bsp.c    **** void bsp_init(void)
  19:User/bsp.c    **** {
  26              		.loc 1 19 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 0
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  20:User/bsp.c    **** 
  21:User/bsp.c    ****   RCC_APB0PeriphClockCmd(RCC_APB0Periph_CORDIC, ENABLE); // 必须分开写
  30              		.loc 1 21 3 view .LVU1
  19:User/bsp.c    **** 
  31              		.loc 1 19 1 is_stmt 0 view .LVU2
  32 0000 10B5     		push	{r4, lr}
  33              	.LCFI0:
  34              		.cfi_def_cfa_offset 8
  35              		.cfi_offset 4, -8
  36              		.cfi_offset 14, -4
ARM GAS  /tmp/ccSm0G8b.s 			page 2


  37              		.loc 1 21 3 view .LVU3
  38 0002 0121     		movs	r1, #1
  39 0004 8020     		movs	r0, #128
  40 0006 FFF7FEFF 		bl	RCC_APB0PeriphClockCmd
  41              	.LVL0:
  22:User/bsp.c    ****   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_RAM0 | RCC_AHBPeriph_RAM1, ENABLE);
  42              		.loc 1 22 3 is_stmt 1 view .LVU4
  43 000a C020     		movs	r0, #192
  44 000c 0121     		movs	r1, #1
  45 000e C002     		lsls	r0, r0, #11
  46 0010 FFF7FEFF 		bl	RCC_AHBPeriphClockCmd
  47              	.LVL1:
  23:User/bsp.c    **** 
  24:User/bsp.c    ****   // 系统初始化
  25:User/bsp.c    ****   SetSysClock();
  48              		.loc 1 25 3 view .LVU5
  49 0014 FFF7FEFF 		bl	SetSysClock
  50              	.LVL2:
  26:User/bsp.c    ****   SysTick_Config(96000);
  51              		.loc 1 26 3 view .LVU6
  52              	.LBB16:
  53              	.LBI16:
  54              		.file 2 "Core/core_cm0.h"
   1:Core/core_cm0.h **** /**************************************************************************//**
   2:Core/core_cm0.h ****  * @file     core_cm0.h
   3:Core/core_cm0.h ****  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
   4:Core/core_cm0.h ****  * @version  V5.0.8
   5:Core/core_cm0.h ****  * @date     21. August 2019
   6:Core/core_cm0.h ****  ******************************************************************************/
   7:Core/core_cm0.h **** /*
   8:Core/core_cm0.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Core/core_cm0.h ****  *
  10:Core/core_cm0.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/core_cm0.h ****  *
  12:Core/core_cm0.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/core_cm0.h ****  * not use this file except in compliance with the License.
  14:Core/core_cm0.h ****  * You may obtain a copy of the License at
  15:Core/core_cm0.h ****  *
  16:Core/core_cm0.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/core_cm0.h ****  *
  18:Core/core_cm0.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/core_cm0.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/core_cm0.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/core_cm0.h ****  * See the License for the specific language governing permissions and
  22:Core/core_cm0.h ****  * limitations under the License.
  23:Core/core_cm0.h ****  */
  24:Core/core_cm0.h **** 
  25:Core/core_cm0.h **** #if   defined ( __ICCARM__ )
  26:Core/core_cm0.h ****   #pragma system_include         /* treat file as system include file for MISRA check */
  27:Core/core_cm0.h **** #elif defined (__clang__)
  28:Core/core_cm0.h ****   #pragma clang system_header   /* treat file as system include file */
  29:Core/core_cm0.h **** #endif
  30:Core/core_cm0.h **** 
  31:Core/core_cm0.h **** #ifndef __CORE_CM0_H_GENERIC
  32:Core/core_cm0.h **** #define __CORE_CM0_H_GENERIC
  33:Core/core_cm0.h **** 
  34:Core/core_cm0.h **** #include <stdint.h>
ARM GAS  /tmp/ccSm0G8b.s 			page 3


  35:Core/core_cm0.h **** 
  36:Core/core_cm0.h **** #ifdef __cplusplus
  37:Core/core_cm0.h ****  extern "C" {
  38:Core/core_cm0.h **** #endif
  39:Core/core_cm0.h **** 
  40:Core/core_cm0.h **** /**
  41:Core/core_cm0.h ****   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
  42:Core/core_cm0.h ****   CMSIS violates the following MISRA-C:2004 rules:
  43:Core/core_cm0.h **** 
  44:Core/core_cm0.h ****    \li Required Rule 8.5, object/function definition in header file.<br>
  45:Core/core_cm0.h ****      Function definitions in header files are used to allow 'inlining'.
  46:Core/core_cm0.h **** 
  47:Core/core_cm0.h ****    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
  48:Core/core_cm0.h ****      Unions are used for effective representation of core registers.
  49:Core/core_cm0.h **** 
  50:Core/core_cm0.h ****    \li Advisory Rule 19.7, Function-like macro defined.<br>
  51:Core/core_cm0.h ****      Function-like macros are used to allow more efficient code.
  52:Core/core_cm0.h ****  */
  53:Core/core_cm0.h **** 
  54:Core/core_cm0.h **** 
  55:Core/core_cm0.h **** /*******************************************************************************
  56:Core/core_cm0.h ****  *                 CMSIS definitions
  57:Core/core_cm0.h ****  ******************************************************************************/
  58:Core/core_cm0.h **** /**
  59:Core/core_cm0.h ****   \ingroup Cortex_M0
  60:Core/core_cm0.h ****   @{
  61:Core/core_cm0.h ****  */
  62:Core/core_cm0.h **** 
  63:Core/core_cm0.h **** #include "cmsis_version.h"
  64:Core/core_cm0.h ****  
  65:Core/core_cm0.h **** /*  CMSIS CM0 definitions */
  66:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] C
  67:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  C
  68:Core/core_cm0.h **** #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
  69:Core/core_cm0.h ****                                     __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL
  70:Core/core_cm0.h **** 
  71:Core/core_cm0.h **** #define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
  72:Core/core_cm0.h **** 
  73:Core/core_cm0.h **** /** __FPU_USED indicates whether an FPU is used or not.
  74:Core/core_cm0.h ****     This core does not support an FPU at all
  75:Core/core_cm0.h **** */
  76:Core/core_cm0.h **** #define __FPU_USED       0U
  77:Core/core_cm0.h **** 
  78:Core/core_cm0.h **** #if defined ( __CC_ARM )
  79:Core/core_cm0.h ****   #if defined __TARGET_FPU_VFP
  80:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  81:Core/core_cm0.h ****   #endif
  82:Core/core_cm0.h **** 
  83:Core/core_cm0.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  84:Core/core_cm0.h ****   #if defined __ARM_FP
  85:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  86:Core/core_cm0.h ****   #endif
  87:Core/core_cm0.h **** 
  88:Core/core_cm0.h **** #elif defined ( __GNUC__ )
  89:Core/core_cm0.h ****   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
  90:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  91:Core/core_cm0.h ****   #endif
ARM GAS  /tmp/ccSm0G8b.s 			page 4


  92:Core/core_cm0.h **** 
  93:Core/core_cm0.h **** #elif defined ( __ICCARM__ )
  94:Core/core_cm0.h ****   #if defined __ARMVFP__
  95:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
  96:Core/core_cm0.h ****   #endif
  97:Core/core_cm0.h **** 
  98:Core/core_cm0.h **** #elif defined ( __TI_ARM__ )
  99:Core/core_cm0.h ****   #if defined __TI_VFP_SUPPORT__
 100:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 101:Core/core_cm0.h ****   #endif
 102:Core/core_cm0.h **** 
 103:Core/core_cm0.h **** #elif defined ( __TASKING__ )
 104:Core/core_cm0.h ****   #if defined __FPU_VFP__
 105:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 106:Core/core_cm0.h ****   #endif
 107:Core/core_cm0.h **** 
 108:Core/core_cm0.h **** #elif defined ( __CSMC__ )
 109:Core/core_cm0.h ****   #if ( __CSMC__ & 0x400U)
 110:Core/core_cm0.h ****     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
 111:Core/core_cm0.h ****   #endif
 112:Core/core_cm0.h **** 
 113:Core/core_cm0.h **** #endif
 114:Core/core_cm0.h **** 
 115:Core/core_cm0.h **** #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
 116:Core/core_cm0.h **** 
 117:Core/core_cm0.h **** 
 118:Core/core_cm0.h **** #ifdef __cplusplus
 119:Core/core_cm0.h **** }
 120:Core/core_cm0.h **** #endif
 121:Core/core_cm0.h **** 
 122:Core/core_cm0.h **** #endif /* __CORE_CM0_H_GENERIC */
 123:Core/core_cm0.h **** 
 124:Core/core_cm0.h **** #ifndef __CMSIS_GENERIC
 125:Core/core_cm0.h **** 
 126:Core/core_cm0.h **** #ifndef __CORE_CM0_H_DEPENDANT
 127:Core/core_cm0.h **** #define __CORE_CM0_H_DEPENDANT
 128:Core/core_cm0.h **** 
 129:Core/core_cm0.h **** #ifdef __cplusplus
 130:Core/core_cm0.h ****  extern "C" {
 131:Core/core_cm0.h **** #endif
 132:Core/core_cm0.h **** 
 133:Core/core_cm0.h **** /* check device defines and use defaults */
 134:Core/core_cm0.h **** #if defined __CHECK_DEVICE_DEFINES
 135:Core/core_cm0.h ****   #ifndef __CM0_REV
 136:Core/core_cm0.h ****     #define __CM0_REV               0x0000U
 137:Core/core_cm0.h ****     #warning "__CM0_REV not defined in device header file; using default!"
 138:Core/core_cm0.h ****   #endif
 139:Core/core_cm0.h **** 
 140:Core/core_cm0.h ****   #ifndef __NVIC_PRIO_BITS
 141:Core/core_cm0.h ****     #define __NVIC_PRIO_BITS          2U
 142:Core/core_cm0.h ****     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
 143:Core/core_cm0.h ****   #endif
 144:Core/core_cm0.h **** 
 145:Core/core_cm0.h ****   #ifndef __Vendor_SysTickConfig
 146:Core/core_cm0.h ****     #define __Vendor_SysTickConfig    0U
 147:Core/core_cm0.h ****     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
 148:Core/core_cm0.h ****   #endif
ARM GAS  /tmp/ccSm0G8b.s 			page 5


 149:Core/core_cm0.h **** #endif
 150:Core/core_cm0.h **** 
 151:Core/core_cm0.h **** /* IO definitions (access restrictions to peripheral registers) */
 152:Core/core_cm0.h **** /**
 153:Core/core_cm0.h ****     \defgroup CMSIS_glob_defs CMSIS Global Defines
 154:Core/core_cm0.h **** 
 155:Core/core_cm0.h ****     <strong>IO Type Qualifiers</strong> are used
 156:Core/core_cm0.h ****     \li to specify the access to peripheral variables.
 157:Core/core_cm0.h ****     \li for automatic generation of peripheral register debug information.
 158:Core/core_cm0.h **** */
 159:Core/core_cm0.h **** #ifdef __cplusplus
 160:Core/core_cm0.h ****   #define   __I     volatile             /*!< Defines 'read only' permissions */
 161:Core/core_cm0.h **** #else
 162:Core/core_cm0.h ****   #define   __I     volatile const       /*!< Defines 'read only' permissions */
 163:Core/core_cm0.h **** #endif
 164:Core/core_cm0.h **** #define     __O     volatile             /*!< Defines 'write only' permissions */
 165:Core/core_cm0.h **** #define     __IO    volatile             /*!< Defines 'read / write' permissions */
 166:Core/core_cm0.h **** 
 167:Core/core_cm0.h **** /* following defines should be used for structure members */
 168:Core/core_cm0.h **** #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
 169:Core/core_cm0.h **** #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
 170:Core/core_cm0.h **** #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
 171:Core/core_cm0.h **** 
 172:Core/core_cm0.h **** /*@} end of group Cortex_M0 */
 173:Core/core_cm0.h **** 
 174:Core/core_cm0.h **** 
 175:Core/core_cm0.h **** 
 176:Core/core_cm0.h **** /*******************************************************************************
 177:Core/core_cm0.h ****  *                 Register Abstraction
 178:Core/core_cm0.h ****   Core Register contain:
 179:Core/core_cm0.h ****   - Core Register
 180:Core/core_cm0.h ****   - Core NVIC Register
 181:Core/core_cm0.h ****   - Core SCB Register
 182:Core/core_cm0.h ****   - Core SysTick Register
 183:Core/core_cm0.h ****  ******************************************************************************/
 184:Core/core_cm0.h **** /**
 185:Core/core_cm0.h ****   \defgroup CMSIS_core_register Defines and Type Definitions
 186:Core/core_cm0.h ****   \brief Type definitions and defines for Cortex-M processor based devices.
 187:Core/core_cm0.h **** */
 188:Core/core_cm0.h **** 
 189:Core/core_cm0.h **** /**
 190:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 191:Core/core_cm0.h ****   \defgroup   CMSIS_CORE  Status and Control Registers
 192:Core/core_cm0.h ****   \brief      Core Register type definitions.
 193:Core/core_cm0.h ****   @{
 194:Core/core_cm0.h ****  */
 195:Core/core_cm0.h **** 
 196:Core/core_cm0.h **** /**
 197:Core/core_cm0.h ****   \brief  Union type to access the Application Program Status Register (APSR).
 198:Core/core_cm0.h ****  */
 199:Core/core_cm0.h **** typedef union
 200:Core/core_cm0.h **** {
 201:Core/core_cm0.h ****   struct
 202:Core/core_cm0.h ****   {
 203:Core/core_cm0.h ****     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
 204:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 205:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
ARM GAS  /tmp/ccSm0G8b.s 			page 6


 206:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 207:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 208:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 209:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 210:Core/core_cm0.h **** } APSR_Type;
 211:Core/core_cm0.h **** 
 212:Core/core_cm0.h **** /* APSR Register Definitions */
 213:Core/core_cm0.h **** #define APSR_N_Pos                         31U                                            /*!< APSR
 214:Core/core_cm0.h **** #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR
 215:Core/core_cm0.h **** 
 216:Core/core_cm0.h **** #define APSR_Z_Pos                         30U                                            /*!< APSR
 217:Core/core_cm0.h **** #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR
 218:Core/core_cm0.h **** 
 219:Core/core_cm0.h **** #define APSR_C_Pos                         29U                                            /*!< APSR
 220:Core/core_cm0.h **** #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR
 221:Core/core_cm0.h **** 
 222:Core/core_cm0.h **** #define APSR_V_Pos                         28U                                            /*!< APSR
 223:Core/core_cm0.h **** #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR
 224:Core/core_cm0.h **** 
 225:Core/core_cm0.h **** 
 226:Core/core_cm0.h **** /**
 227:Core/core_cm0.h ****   \brief  Union type to access the Interrupt Program Status Register (IPSR).
 228:Core/core_cm0.h ****  */
 229:Core/core_cm0.h **** typedef union
 230:Core/core_cm0.h **** {
 231:Core/core_cm0.h ****   struct
 232:Core/core_cm0.h ****   {
 233:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 234:Core/core_cm0.h ****     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
 235:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 236:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 237:Core/core_cm0.h **** } IPSR_Type;
 238:Core/core_cm0.h **** 
 239:Core/core_cm0.h **** /* IPSR Register Definitions */
 240:Core/core_cm0.h **** #define IPSR_ISR_Pos                        0U                                            /*!< IPSR
 241:Core/core_cm0.h **** #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR
 242:Core/core_cm0.h **** 
 243:Core/core_cm0.h **** 
 244:Core/core_cm0.h **** /**
 245:Core/core_cm0.h ****   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
 246:Core/core_cm0.h ****  */
 247:Core/core_cm0.h **** typedef union
 248:Core/core_cm0.h **** {
 249:Core/core_cm0.h ****   struct
 250:Core/core_cm0.h ****   {
 251:Core/core_cm0.h ****     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
 252:Core/core_cm0.h ****     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
 253:Core/core_cm0.h ****     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
 254:Core/core_cm0.h ****     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
 255:Core/core_cm0.h ****     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
 256:Core/core_cm0.h ****     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
 257:Core/core_cm0.h ****     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
 258:Core/core_cm0.h ****     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
 259:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 260:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 261:Core/core_cm0.h **** } xPSR_Type;
 262:Core/core_cm0.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 7


 263:Core/core_cm0.h **** /* xPSR Register Definitions */
 264:Core/core_cm0.h **** #define xPSR_N_Pos                         31U                                            /*!< xPSR
 265:Core/core_cm0.h **** #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR
 266:Core/core_cm0.h **** 
 267:Core/core_cm0.h **** #define xPSR_Z_Pos                         30U                                            /*!< xPSR
 268:Core/core_cm0.h **** #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR
 269:Core/core_cm0.h **** 
 270:Core/core_cm0.h **** #define xPSR_C_Pos                         29U                                            /*!< xPSR
 271:Core/core_cm0.h **** #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR
 272:Core/core_cm0.h **** 
 273:Core/core_cm0.h **** #define xPSR_V_Pos                         28U                                            /*!< xPSR
 274:Core/core_cm0.h **** #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR
 275:Core/core_cm0.h **** 
 276:Core/core_cm0.h **** #define xPSR_T_Pos                         24U                                            /*!< xPSR
 277:Core/core_cm0.h **** #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR
 278:Core/core_cm0.h **** 
 279:Core/core_cm0.h **** #define xPSR_ISR_Pos                        0U                                            /*!< xPSR
 280:Core/core_cm0.h **** #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR
 281:Core/core_cm0.h **** 
 282:Core/core_cm0.h **** 
 283:Core/core_cm0.h **** /**
 284:Core/core_cm0.h ****   \brief  Union type to access the Control Registers (CONTROL).
 285:Core/core_cm0.h ****  */
 286:Core/core_cm0.h **** typedef union
 287:Core/core_cm0.h **** {
 288:Core/core_cm0.h ****   struct
 289:Core/core_cm0.h ****   {
 290:Core/core_cm0.h ****     uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
 291:Core/core_cm0.h ****     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
 292:Core/core_cm0.h ****     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
 293:Core/core_cm0.h ****   } b;                                   /*!< Structure used for bit  access */
 294:Core/core_cm0.h ****   uint32_t w;                            /*!< Type      used for word access */
 295:Core/core_cm0.h **** } CONTROL_Type;
 296:Core/core_cm0.h **** 
 297:Core/core_cm0.h **** /* CONTROL Register Definitions */
 298:Core/core_cm0.h **** #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONT
 299:Core/core_cm0.h **** #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONT
 300:Core/core_cm0.h **** 
 301:Core/core_cm0.h **** /*@} end of group CMSIS_CORE */
 302:Core/core_cm0.h **** 
 303:Core/core_cm0.h **** 
 304:Core/core_cm0.h **** /**
 305:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 306:Core/core_cm0.h ****   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
 307:Core/core_cm0.h ****   \brief      Type definitions for the NVIC Registers
 308:Core/core_cm0.h ****   @{
 309:Core/core_cm0.h ****  */
 310:Core/core_cm0.h **** 
 311:Core/core_cm0.h **** /**
 312:Core/core_cm0.h ****   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
 313:Core/core_cm0.h ****  */
 314:Core/core_cm0.h **** typedef struct
 315:Core/core_cm0.h **** {
 316:Core/core_cm0.h ****   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
 317:Core/core_cm0.h ****         uint32_t RESERVED0[31U];
 318:Core/core_cm0.h ****   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register 
 319:Core/core_cm0.h ****         uint32_t RESERVED1[31U];
ARM GAS  /tmp/ccSm0G8b.s 			page 8


 320:Core/core_cm0.h ****   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register *
 321:Core/core_cm0.h ****         uint32_t RESERVED2[31U];
 322:Core/core_cm0.h ****   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register
 323:Core/core_cm0.h ****         uint32_t RESERVED3[31U];
 324:Core/core_cm0.h ****         uint32_t RESERVED4[64U];
 325:Core/core_cm0.h ****   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
 326:Core/core_cm0.h **** }  NVIC_Type;
 327:Core/core_cm0.h **** 
 328:Core/core_cm0.h **** /*@} end of group CMSIS_NVIC */
 329:Core/core_cm0.h **** 
 330:Core/core_cm0.h **** 
 331:Core/core_cm0.h **** /**
 332:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 333:Core/core_cm0.h ****   \defgroup CMSIS_SCB     System Control Block (SCB)
 334:Core/core_cm0.h ****   \brief    Type definitions for the System Control Block Registers
 335:Core/core_cm0.h ****   @{
 336:Core/core_cm0.h ****  */
 337:Core/core_cm0.h **** 
 338:Core/core_cm0.h **** /**
 339:Core/core_cm0.h ****   \brief  Structure type to access the System Control Block (SCB).
 340:Core/core_cm0.h ****  */
 341:Core/core_cm0.h **** typedef struct
 342:Core/core_cm0.h **** {
 343:Core/core_cm0.h ****   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
 344:Core/core_cm0.h ****   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Regi
 345:Core/core_cm0.h ****         uint32_t RESERVED0;
 346:Core/core_cm0.h ****   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset 
 347:Core/core_cm0.h ****   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
 348:Core/core_cm0.h ****   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register *
 349:Core/core_cm0.h ****         uint32_t RESERVED1;
 350:Core/core_cm0.h ****   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registe
 351:Core/core_cm0.h ****   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State
 352:Core/core_cm0.h **** } SCB_Type;
 353:Core/core_cm0.h **** 
 354:Core/core_cm0.h **** /* SCB CPUID Register Definitions */
 355:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB 
 356:Core/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB 
 357:Core/core_cm0.h **** 
 358:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB 
 359:Core/core_cm0.h **** #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB 
 360:Core/core_cm0.h **** 
 361:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB 
 362:Core/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB 
 363:Core/core_cm0.h **** 
 364:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB 
 365:Core/core_cm0.h **** #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB 
 366:Core/core_cm0.h **** 
 367:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB 
 368:Core/core_cm0.h **** #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB 
 369:Core/core_cm0.h **** 
 370:Core/core_cm0.h **** /* SCB Interrupt Control State Register Definitions */
 371:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB 
 372:Core/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB 
 373:Core/core_cm0.h **** 
 374:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB 
 375:Core/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB 
 376:Core/core_cm0.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 9


 377:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB 
 378:Core/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB 
 379:Core/core_cm0.h **** 
 380:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB 
 381:Core/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB 
 382:Core/core_cm0.h **** 
 383:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB 
 384:Core/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB 
 385:Core/core_cm0.h **** 
 386:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB 
 387:Core/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB 
 388:Core/core_cm0.h **** 
 389:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB 
 390:Core/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB 
 391:Core/core_cm0.h **** 
 392:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB 
 393:Core/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB 
 394:Core/core_cm0.h **** 
 395:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB 
 396:Core/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB 
 397:Core/core_cm0.h **** 
 398:Core/core_cm0.h **** /* SCB Application Interrupt and Reset Control Register Definitions */
 399:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB 
 400:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB 
 401:Core/core_cm0.h **** 
 402:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB 
 403:Core/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB 
 404:Core/core_cm0.h **** 
 405:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB 
 406:Core/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB 
 407:Core/core_cm0.h **** 
 408:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB 
 409:Core/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB 
 410:Core/core_cm0.h **** 
 411:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB 
 412:Core/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB 
 413:Core/core_cm0.h **** 
 414:Core/core_cm0.h **** /* SCB System Control Register Definitions */
 415:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB 
 416:Core/core_cm0.h **** #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB 
 417:Core/core_cm0.h **** 
 418:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB 
 419:Core/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB 
 420:Core/core_cm0.h **** 
 421:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB 
 422:Core/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB 
 423:Core/core_cm0.h **** 
 424:Core/core_cm0.h **** /* SCB Configuration Control Register Definitions */
 425:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB 
 426:Core/core_cm0.h **** #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB 
 427:Core/core_cm0.h **** 
 428:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB 
 429:Core/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB 
 430:Core/core_cm0.h **** 
 431:Core/core_cm0.h **** /* SCB System Handler Control and State Register Definitions */
 432:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB 
 433:Core/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB 
ARM GAS  /tmp/ccSm0G8b.s 			page 10


 434:Core/core_cm0.h **** 
 435:Core/core_cm0.h **** /*@} end of group CMSIS_SCB */
 436:Core/core_cm0.h **** 
 437:Core/core_cm0.h **** 
 438:Core/core_cm0.h **** /**
 439:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 440:Core/core_cm0.h ****   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
 441:Core/core_cm0.h ****   \brief    Type definitions for the System Timer Registers.
 442:Core/core_cm0.h ****   @{
 443:Core/core_cm0.h ****  */
 444:Core/core_cm0.h **** 
 445:Core/core_cm0.h **** /**
 446:Core/core_cm0.h ****   \brief  Structure type to access the System Timer (SysTick).
 447:Core/core_cm0.h ****  */
 448:Core/core_cm0.h **** typedef struct
 449:Core/core_cm0.h **** {
 450:Core/core_cm0.h ****   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Regis
 451:Core/core_cm0.h ****   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
 452:Core/core_cm0.h ****   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register *
 453:Core/core_cm0.h ****   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
 454:Core/core_cm0.h **** } SysTick_Type;
 455:Core/core_cm0.h **** 
 456:Core/core_cm0.h **** /* SysTick Control / Status Register Definitions */
 457:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysT
 458:Core/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysT
 459:Core/core_cm0.h **** 
 460:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysT
 461:Core/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysT
 462:Core/core_cm0.h **** 
 463:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysT
 464:Core/core_cm0.h **** #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysT
 465:Core/core_cm0.h **** 
 466:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysT
 467:Core/core_cm0.h **** #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysT
 468:Core/core_cm0.h **** 
 469:Core/core_cm0.h **** /* SysTick Reload Register Definitions */
 470:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysT
 471:Core/core_cm0.h **** #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysT
 472:Core/core_cm0.h **** 
 473:Core/core_cm0.h **** /* SysTick Current Register Definitions */
 474:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysT
 475:Core/core_cm0.h **** #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysT
 476:Core/core_cm0.h **** 
 477:Core/core_cm0.h **** /* SysTick Calibration Register Definitions */
 478:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysT
 479:Core/core_cm0.h **** #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysT
 480:Core/core_cm0.h **** 
 481:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysT
 482:Core/core_cm0.h **** #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysT
 483:Core/core_cm0.h **** 
 484:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysT
 485:Core/core_cm0.h **** #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysT
 486:Core/core_cm0.h **** 
 487:Core/core_cm0.h **** /*@} end of group CMSIS_SysTick */
 488:Core/core_cm0.h **** 
 489:Core/core_cm0.h **** 
 490:Core/core_cm0.h **** /**
ARM GAS  /tmp/ccSm0G8b.s 			page 11


 491:Core/core_cm0.h ****   \ingroup  CMSIS_core_register
 492:Core/core_cm0.h ****   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
 493:Core/core_cm0.h ****   \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ove
 494:Core/core_cm0.h ****             Therefore they are not covered by the Cortex-M0 header file.
 495:Core/core_cm0.h ****   @{
 496:Core/core_cm0.h ****  */
 497:Core/core_cm0.h **** /*@} end of group CMSIS_CoreDebug */
 498:Core/core_cm0.h **** 
 499:Core/core_cm0.h **** 
 500:Core/core_cm0.h **** /**
 501:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 502:Core/core_cm0.h ****   \defgroup   CMSIS_core_bitfield     Core register bit field macros
 503:Core/core_cm0.h ****   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
 504:Core/core_cm0.h ****   @{
 505:Core/core_cm0.h ****  */
 506:Core/core_cm0.h **** 
 507:Core/core_cm0.h **** /**
 508:Core/core_cm0.h ****   \brief   Mask and shift a bit field value for use in a register bit range.
 509:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 510:Core/core_cm0.h ****   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
 511:Core/core_cm0.h ****   \return           Masked and shifted value.
 512:Core/core_cm0.h **** */
 513:Core/core_cm0.h **** #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 514:Core/core_cm0.h **** 
 515:Core/core_cm0.h **** /**
 516:Core/core_cm0.h ****   \brief     Mask and shift a register value to extract a bit filed value.
 517:Core/core_cm0.h ****   \param[in] field  Name of the register bit field.
 518:Core/core_cm0.h ****   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
 519:Core/core_cm0.h ****   \return           Masked and shifted bit field value.
 520:Core/core_cm0.h **** */
 521:Core/core_cm0.h **** #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 522:Core/core_cm0.h **** 
 523:Core/core_cm0.h **** /*@} end of group CMSIS_core_bitfield */
 524:Core/core_cm0.h **** 
 525:Core/core_cm0.h **** 
 526:Core/core_cm0.h **** /**
 527:Core/core_cm0.h ****   \ingroup    CMSIS_core_register
 528:Core/core_cm0.h ****   \defgroup   CMSIS_core_base     Core Definitions
 529:Core/core_cm0.h ****   \brief      Definitions for base addresses, unions, and structures.
 530:Core/core_cm0.h ****   @{
 531:Core/core_cm0.h ****  */
 532:Core/core_cm0.h **** 
 533:Core/core_cm0.h **** /* Memory mapping of Core Hardware */
 534:Core/core_cm0.h **** #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Bas
 535:Core/core_cm0.h **** #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
 536:Core/core_cm0.h **** #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
 537:Core/core_cm0.h **** #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Bas
 538:Core/core_cm0.h **** 
 539:Core/core_cm0.h **** #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct
 540:Core/core_cm0.h **** #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration st
 541:Core/core_cm0.h **** #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struc
 542:Core/core_cm0.h **** 
 543:Core/core_cm0.h **** 
 544:Core/core_cm0.h **** /*@} */
 545:Core/core_cm0.h **** 
 546:Core/core_cm0.h **** 
 547:Core/core_cm0.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 12


 548:Core/core_cm0.h **** /*******************************************************************************
 549:Core/core_cm0.h ****  *                Hardware Abstraction Layer
 550:Core/core_cm0.h ****   Core Function Interface contains:
 551:Core/core_cm0.h ****   - Core NVIC Functions
 552:Core/core_cm0.h ****   - Core SysTick Functions
 553:Core/core_cm0.h ****   - Core Register Access Functions
 554:Core/core_cm0.h ****  ******************************************************************************/
 555:Core/core_cm0.h **** /**
 556:Core/core_cm0.h ****   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
 557:Core/core_cm0.h **** */
 558:Core/core_cm0.h **** 
 559:Core/core_cm0.h **** 
 560:Core/core_cm0.h **** 
 561:Core/core_cm0.h **** /* ##########################   NVIC functions  #################################### */
 562:Core/core_cm0.h **** /**
 563:Core/core_cm0.h ****   \ingroup  CMSIS_Core_FunctionInterface
 564:Core/core_cm0.h ****   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
 565:Core/core_cm0.h ****   \brief    Functions that manage interrupts and exceptions via the NVIC.
 566:Core/core_cm0.h ****   @{
 567:Core/core_cm0.h ****  */
 568:Core/core_cm0.h **** 
 569:Core/core_cm0.h **** #ifdef CMSIS_NVIC_VIRTUAL
 570:Core/core_cm0.h ****   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
 571:Core/core_cm0.h ****     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
 572:Core/core_cm0.h ****   #endif
 573:Core/core_cm0.h ****   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
 574:Core/core_cm0.h **** #else
 575:Core/core_cm0.h ****   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
 576:Core/core_cm0.h ****   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
 577:Core/core_cm0.h ****   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
 578:Core/core_cm0.h ****   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
 579:Core/core_cm0.h ****   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
 580:Core/core_cm0.h ****   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
 581:Core/core_cm0.h ****   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
 582:Core/core_cm0.h ****   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
 583:Core/core_cm0.h **** /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
 584:Core/core_cm0.h ****   #define NVIC_SetPriority            __NVIC_SetPriority
 585:Core/core_cm0.h ****   #define NVIC_GetPriority            __NVIC_GetPriority
 586:Core/core_cm0.h ****   #define NVIC_SystemReset            __NVIC_SystemReset
 587:Core/core_cm0.h **** #endif /* CMSIS_NVIC_VIRTUAL */
 588:Core/core_cm0.h **** 
 589:Core/core_cm0.h **** #ifdef CMSIS_VECTAB_VIRTUAL
 590:Core/core_cm0.h ****   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 591:Core/core_cm0.h ****     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
 592:Core/core_cm0.h ****   #endif
 593:Core/core_cm0.h ****   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
 594:Core/core_cm0.h **** #else
 595:Core/core_cm0.h ****   #define NVIC_SetVector              __NVIC_SetVector
 596:Core/core_cm0.h ****   #define NVIC_GetVector              __NVIC_GetVector
 597:Core/core_cm0.h **** #endif  /* (CMSIS_VECTAB_VIRTUAL) */
 598:Core/core_cm0.h **** 
 599:Core/core_cm0.h **** #define NVIC_USER_IRQ_OFFSET          16
 600:Core/core_cm0.h **** 
 601:Core/core_cm0.h **** 
 602:Core/core_cm0.h **** /* The following EXC_RETURN values are saved the LR on exception entry */
 603:Core/core_cm0.h **** #define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after ret
 604:Core/core_cm0.h **** #define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after retu
ARM GAS  /tmp/ccSm0G8b.s 			page 13


 605:Core/core_cm0.h **** #define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after retu
 606:Core/core_cm0.h **** 
 607:Core/core_cm0.h **** 
 608:Core/core_cm0.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M                  */
 609:Core/core_cm0.h **** /* The following MACROS handle generation of the register offset and byte masks */
 610:Core/core_cm0.h **** #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
 611:Core/core_cm0.h **** #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
 612:Core/core_cm0.h **** #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
 613:Core/core_cm0.h **** 
 614:Core/core_cm0.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X)
 615:Core/core_cm0.h **** #define __NVIC_GetPriorityGrouping()  (0U)
 616:Core/core_cm0.h **** 
 617:Core/core_cm0.h **** /**
 618:Core/core_cm0.h ****   \brief   Enable Interrupt
 619:Core/core_cm0.h ****   \details Enables a device specific interrupt in the NVIC interrupt controller.
 620:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 621:Core/core_cm0.h ****   \note    IRQn must not be negative.
 622:Core/core_cm0.h ****  */
 623:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
 624:Core/core_cm0.h **** {
 625:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 626:Core/core_cm0.h ****   {
 627:Core/core_cm0.h ****     __COMPILER_BARRIER();
 628:Core/core_cm0.h ****     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 629:Core/core_cm0.h ****     __COMPILER_BARRIER();
 630:Core/core_cm0.h ****   }
 631:Core/core_cm0.h **** }
 632:Core/core_cm0.h **** 
 633:Core/core_cm0.h **** 
 634:Core/core_cm0.h **** /**
 635:Core/core_cm0.h ****   \brief   Get Interrupt Enable status
 636:Core/core_cm0.h ****   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
 637:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 638:Core/core_cm0.h ****   \return             0  Interrupt is not enabled.
 639:Core/core_cm0.h ****   \return             1  Interrupt is enabled.
 640:Core/core_cm0.h ****   \note    IRQn must not be negative.
 641:Core/core_cm0.h ****  */
 642:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
 643:Core/core_cm0.h **** {
 644:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 645:Core/core_cm0.h ****   {
 646:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 647:Core/core_cm0.h ****   }
 648:Core/core_cm0.h ****   else
 649:Core/core_cm0.h ****   {
 650:Core/core_cm0.h ****     return(0U);
 651:Core/core_cm0.h ****   }
 652:Core/core_cm0.h **** }
 653:Core/core_cm0.h **** 
 654:Core/core_cm0.h **** 
 655:Core/core_cm0.h **** /**
 656:Core/core_cm0.h ****   \brief   Disable Interrupt
 657:Core/core_cm0.h ****   \details Disables a device specific interrupt in the NVIC interrupt controller.
 658:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 659:Core/core_cm0.h ****   \note    IRQn must not be negative.
 660:Core/core_cm0.h ****  */
 661:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
ARM GAS  /tmp/ccSm0G8b.s 			page 14


 662:Core/core_cm0.h **** {
 663:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 664:Core/core_cm0.h ****   {
 665:Core/core_cm0.h ****     NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 666:Core/core_cm0.h ****     __DSB();
 667:Core/core_cm0.h ****     __ISB();
 668:Core/core_cm0.h ****   }
 669:Core/core_cm0.h **** }
 670:Core/core_cm0.h **** 
 671:Core/core_cm0.h **** 
 672:Core/core_cm0.h **** /**
 673:Core/core_cm0.h ****   \brief   Get Pending Interrupt
 674:Core/core_cm0.h ****   \details Reads the NVIC pending register and returns the pending bit for the specified device spe
 675:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 676:Core/core_cm0.h ****   \return             0  Interrupt status is not pending.
 677:Core/core_cm0.h ****   \return             1  Interrupt status is pending.
 678:Core/core_cm0.h ****   \note    IRQn must not be negative.
 679:Core/core_cm0.h ****  */
 680:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
 681:Core/core_cm0.h **** {
 682:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 683:Core/core_cm0.h ****   {
 684:Core/core_cm0.h ****     return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)
 685:Core/core_cm0.h ****   }
 686:Core/core_cm0.h ****   else
 687:Core/core_cm0.h ****   {
 688:Core/core_cm0.h ****     return(0U);
 689:Core/core_cm0.h ****   }
 690:Core/core_cm0.h **** }
 691:Core/core_cm0.h **** 
 692:Core/core_cm0.h **** 
 693:Core/core_cm0.h **** /**
 694:Core/core_cm0.h ****   \brief   Set Pending Interrupt
 695:Core/core_cm0.h ****   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
 696:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 697:Core/core_cm0.h ****   \note    IRQn must not be negative.
 698:Core/core_cm0.h ****  */
 699:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
 700:Core/core_cm0.h **** {
 701:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 702:Core/core_cm0.h ****   {
 703:Core/core_cm0.h ****     NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 704:Core/core_cm0.h ****   }
 705:Core/core_cm0.h **** }
 706:Core/core_cm0.h **** 
 707:Core/core_cm0.h **** 
 708:Core/core_cm0.h **** /**
 709:Core/core_cm0.h ****   \brief   Clear Pending Interrupt
 710:Core/core_cm0.h ****   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
 711:Core/core_cm0.h ****   \param [in]      IRQn  Device specific interrupt number.
 712:Core/core_cm0.h ****   \note    IRQn must not be negative.
 713:Core/core_cm0.h ****  */
 714:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 715:Core/core_cm0.h **** {
 716:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 717:Core/core_cm0.h ****   {
 718:Core/core_cm0.h ****     NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
ARM GAS  /tmp/ccSm0G8b.s 			page 15


 719:Core/core_cm0.h ****   }
 720:Core/core_cm0.h **** }
 721:Core/core_cm0.h **** 
 722:Core/core_cm0.h **** 
 723:Core/core_cm0.h **** /**
 724:Core/core_cm0.h ****   \brief   Set Interrupt Priority
 725:Core/core_cm0.h ****   \details Sets the priority of a device specific interrupt or a processor exception.
 726:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 727:Core/core_cm0.h ****            or negative to specify a processor exception.
 728:Core/core_cm0.h ****   \param [in]      IRQn  Interrupt number.
 729:Core/core_cm0.h ****   \param [in]  priority  Priority to set.
 730:Core/core_cm0.h ****   \note    The priority cannot be set for every processor exception.
 731:Core/core_cm0.h ****  */
 732:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 733:Core/core_cm0.h **** {
 734:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 735:Core/core_cm0.h ****   {
 736:Core/core_cm0.h ****     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))
 737:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 738:Core/core_cm0.h ****   }
 739:Core/core_cm0.h ****   else
 740:Core/core_cm0.h ****   {
 741:Core/core_cm0.h ****     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))
 742:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 743:Core/core_cm0.h ****   }
 744:Core/core_cm0.h **** }
 745:Core/core_cm0.h **** 
 746:Core/core_cm0.h **** 
 747:Core/core_cm0.h **** /**
 748:Core/core_cm0.h ****   \brief   Get Interrupt Priority
 749:Core/core_cm0.h ****   \details Reads the priority of a device specific interrupt or a processor exception.
 750:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 751:Core/core_cm0.h ****            or negative to specify a processor exception.
 752:Core/core_cm0.h ****   \param [in]   IRQn  Interrupt number.
 753:Core/core_cm0.h ****   \return             Interrupt Priority.
 754:Core/core_cm0.h ****                       Value is aligned automatically to the implemented priority bits of the microc
 755:Core/core_cm0.h ****  */
 756:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
 757:Core/core_cm0.h **** {
 758:Core/core_cm0.h **** 
 759:Core/core_cm0.h ****   if ((int32_t)(IRQn) >= 0)
 760:Core/core_cm0.h ****   {
 761:Core/core_cm0.h ****     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 762:Core/core_cm0.h ****   }
 763:Core/core_cm0.h ****   else
 764:Core/core_cm0.h ****   {
 765:Core/core_cm0.h ****     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U -
 766:Core/core_cm0.h ****   }
 767:Core/core_cm0.h **** }
 768:Core/core_cm0.h **** 
 769:Core/core_cm0.h **** 
 770:Core/core_cm0.h **** /**
 771:Core/core_cm0.h ****   \brief   Encode Priority
 772:Core/core_cm0.h ****   \details Encodes the priority for an interrupt with the given priority group,
 773:Core/core_cm0.h ****            preemptive priority value, and subpriority value.
 774:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 775:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
ARM GAS  /tmp/ccSm0G8b.s 			page 16


 776:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 777:Core/core_cm0.h ****   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
 778:Core/core_cm0.h ****   \param [in]       SubPriority  Subpriority value (starting from 0).
 779:Core/core_cm0.h ****   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetP
 780:Core/core_cm0.h ****  */
 781:Core/core_cm0.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin
 782:Core/core_cm0.h **** {
 783:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 784:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 785:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 786:Core/core_cm0.h **** 
 787:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 788:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 789:Core/core_cm0.h **** 
 790:Core/core_cm0.h ****   return (
 791:Core/core_cm0.h ****            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits
 792:Core/core_cm0.h ****            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 793:Core/core_cm0.h ****          );
 794:Core/core_cm0.h **** }
 795:Core/core_cm0.h **** 
 796:Core/core_cm0.h **** 
 797:Core/core_cm0.h **** /**
 798:Core/core_cm0.h ****   \brief   Decode Priority
 799:Core/core_cm0.h ****   \details Decodes an interrupt priority value with a given priority group to
 800:Core/core_cm0.h ****            preemptive priority value and subpriority value.
 801:Core/core_cm0.h ****            In case of a conflict between priority grouping and available
 802:Core/core_cm0.h ****            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
 803:Core/core_cm0.h ****   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC
 804:Core/core_cm0.h ****   \param [in]     PriorityGroup  Used priority group.
 805:Core/core_cm0.h ****   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
 806:Core/core_cm0.h ****   \param [out]     pSubPriority  Subpriority value (starting from 0).
 807:Core/core_cm0.h ****  */
 808:Core/core_cm0.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons
 809:Core/core_cm0.h **** {
 810:Core/core_cm0.h ****   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used   
 811:Core/core_cm0.h ****   uint32_t PreemptPriorityBits;
 812:Core/core_cm0.h ****   uint32_t SubPriorityBits;
 813:Core/core_cm0.h **** 
 814:Core/core_cm0.h ****   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV
 815:Core/core_cm0.h ****   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint
 816:Core/core_cm0.h **** 
 817:Core/core_cm0.h ****   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1
 818:Core/core_cm0.h ****   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1
 819:Core/core_cm0.h **** }
 820:Core/core_cm0.h **** 
 821:Core/core_cm0.h **** 
 822:Core/core_cm0.h **** 
 823:Core/core_cm0.h **** /**
 824:Core/core_cm0.h ****   \brief   Set Interrupt Vector
 825:Core/core_cm0.h ****   \details Sets an interrupt vector in SRAM based interrupt vector table.
 826:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 827:Core/core_cm0.h ****            or negative to specify a processor exception.
 828:Core/core_cm0.h ****            Address 0 must be mapped to SRAM.
 829:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number
 830:Core/core_cm0.h ****   \param [in]   vector    Address of interrupt handler function
 831:Core/core_cm0.h ****  */
 832:Core/core_cm0.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
ARM GAS  /tmp/ccSm0G8b.s 			page 17


 833:Core/core_cm0.h **** {
 834:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 835:Core/core_cm0.h ****   *(vectors + (int32_t)IRQn) = vector;                              /* use pointer arithmetic to ac
 836:Core/core_cm0.h ****   /* ARM Application Note 321 states that the M0 does not require the architectural barrier */
 837:Core/core_cm0.h **** }
 838:Core/core_cm0.h **** 
 839:Core/core_cm0.h **** 
 840:Core/core_cm0.h **** /**
 841:Core/core_cm0.h ****   \brief   Get Interrupt Vector
 842:Core/core_cm0.h ****   \details Reads an interrupt vector from interrupt vector table.
 843:Core/core_cm0.h ****            The interrupt number can be positive to specify a device specific interrupt,
 844:Core/core_cm0.h ****            or negative to specify a processor exception.
 845:Core/core_cm0.h ****   \param [in]   IRQn      Interrupt number.
 846:Core/core_cm0.h ****   \return                 Address of interrupt handler function
 847:Core/core_cm0.h ****  */
 848:Core/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
 849:Core/core_cm0.h **** {
 850:Core/core_cm0.h ****   uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2);      /* point to 1st user interrupt 
 851:Core/core_cm0.h ****   return *(vectors + (int32_t)IRQn);                                /* use pointer arithmetic to ac
 852:Core/core_cm0.h **** }
 853:Core/core_cm0.h **** 
 854:Core/core_cm0.h **** 
 855:Core/core_cm0.h **** /**
 856:Core/core_cm0.h ****   \brief   System Reset
 857:Core/core_cm0.h ****   \details Initiates a system reset request to reset the MCU.
 858:Core/core_cm0.h ****  */
 859:Core/core_cm0.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
 860:Core/core_cm0.h **** {
 861:Core/core_cm0.h ****   __DSB();                                                          /* Ensure all outstanding memor
 862:Core/core_cm0.h ****                                                                        buffered write are completed
 863:Core/core_cm0.h ****   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 864:Core/core_cm0.h ****                  SCB_AIRCR_SYSRESETREQ_Msk);
 865:Core/core_cm0.h ****   __DSB();                                                          /* Ensure completion of memory 
 866:Core/core_cm0.h **** 
 867:Core/core_cm0.h ****   for(;;)                                                           /* wait until reset */
 868:Core/core_cm0.h ****   {
 869:Core/core_cm0.h ****     __NOP();
 870:Core/core_cm0.h ****   }
 871:Core/core_cm0.h **** }
 872:Core/core_cm0.h **** 
 873:Core/core_cm0.h **** /*@} end of CMSIS_Core_NVICFunctions */
 874:Core/core_cm0.h **** 
 875:Core/core_cm0.h **** 
 876:Core/core_cm0.h **** /* ##########################  FPU functions  #################################### */
 877:Core/core_cm0.h **** /**
 878:Core/core_cm0.h ****   \ingroup  CMSIS_Core_FunctionInterface
 879:Core/core_cm0.h ****   \defgroup CMSIS_Core_FpuFunctions FPU Functions
 880:Core/core_cm0.h ****   \brief    Function that provides FPU type.
 881:Core/core_cm0.h ****   @{
 882:Core/core_cm0.h ****  */
 883:Core/core_cm0.h **** 
 884:Core/core_cm0.h **** /**
 885:Core/core_cm0.h ****   \brief   get FPU type
 886:Core/core_cm0.h ****   \details returns the FPU type
 887:Core/core_cm0.h ****   \returns
 888:Core/core_cm0.h ****    - \b  0: No FPU
 889:Core/core_cm0.h ****    - \b  1: Single precision FPU
ARM GAS  /tmp/ccSm0G8b.s 			page 18


 890:Core/core_cm0.h ****    - \b  2: Double + Single precision FPU
 891:Core/core_cm0.h ****  */
 892:Core/core_cm0.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void)
 893:Core/core_cm0.h **** {
 894:Core/core_cm0.h ****     return 0U;           /* No FPU */
 895:Core/core_cm0.h **** }
 896:Core/core_cm0.h **** 
 897:Core/core_cm0.h **** 
 898:Core/core_cm0.h **** /*@} end of CMSIS_Core_FpuFunctions */
 899:Core/core_cm0.h **** 
 900:Core/core_cm0.h **** 
 901:Core/core_cm0.h **** 
 902:Core/core_cm0.h **** /* ##################################    SysTick function  ########################################
 903:Core/core_cm0.h **** /**
 904:Core/core_cm0.h ****   \ingroup  CMSIS_Core_FunctionInterface
 905:Core/core_cm0.h ****   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
 906:Core/core_cm0.h ****   \brief    Functions that configure the System.
 907:Core/core_cm0.h ****   @{
 908:Core/core_cm0.h ****  */
 909:Core/core_cm0.h **** 
 910:Core/core_cm0.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
 911:Core/core_cm0.h **** 
 912:Core/core_cm0.h **** /**
 913:Core/core_cm0.h ****   \brief   System Tick Configuration
 914:Core/core_cm0.h ****   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
 915:Core/core_cm0.h ****            Counter is in free running mode to generate periodic interrupts.
 916:Core/core_cm0.h ****   \param [in]  ticks  Number of ticks between two interrupts.
 917:Core/core_cm0.h ****   \return          0  Function succeeded.
 918:Core/core_cm0.h ****   \return          1  Function failed.
 919:Core/core_cm0.h ****   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
 920:Core/core_cm0.h ****            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.
 921:Core/core_cm0.h ****            must contain a vendor-specific implementation of this function.
 922:Core/core_cm0.h ****  */
 923:Core/core_cm0.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  55              		.loc 2 923 26 view .LVU7
  56              	.LBB17:
 924:Core/core_cm0.h **** {
 925:Core/core_cm0.h ****   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  57              		.loc 2 925 3 view .LVU8
 926:Core/core_cm0.h ****   {
 927:Core/core_cm0.h ****     return (1UL);                                                   /* Reload value impossible */
 928:Core/core_cm0.h ****   }
 929:Core/core_cm0.h **** 
 930:Core/core_cm0.h ****   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
  58              		.loc 2 930 3 view .LVU9
  59              	.LBB18:
  60              	.LBB19:
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  61              		.loc 2 741 102 is_stmt 0 view .LVU10
  62 0018 C021     		movs	r1, #192
  63              	.LBE19:
  64              	.LBE18:
  65              		.loc 2 930 18 view .LVU11
  66 001a 124A     		ldr	r2, .L3
  67 001c 124B     		ldr	r3, .L3+4
  68              	.LBB22:
  69              	.LBB20:
ARM GAS  /tmp/ccSm0G8b.s 			page 19


 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  70              		.loc 2 741 52 view .LVU12
  71 001e 1348     		ldr	r0, .L3+8
  72              	.LBE20:
  73              	.LBE22:
  74              		.loc 2 930 18 view .LVU13
  75 0020 5360     		str	r3, [r2, #4]
 931:Core/core_cm0.h ****   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int
  76              		.loc 2 931 3 is_stmt 1 view .LVU14
  77              	.LVL3:
  78              	.LBB23:
  79              	.LBI18:
 732:Core/core_cm0.h **** {
  80              		.loc 2 732 22 view .LVU15
  81              	.LBB21:
 734:Core/core_cm0.h ****   {
  82              		.loc 2 734 3 view .LVU16
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  83              		.loc 2 741 5 view .LVU17
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  84              		.loc 2 741 52 is_stmt 0 view .LVU18
  85 0022 036A     		ldr	r3, [r0, #32]
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  86              		.loc 2 741 102 view .LVU19
  87 0024 0906     		lsls	r1, r1, #24
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  88              		.loc 2 741 33 view .LVU20
  89 0026 1B02     		lsls	r3, r3, #8
  90 0028 1B0A     		lsrs	r3, r3, #8
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  91              		.loc 2 741 102 view .LVU21
  92 002a 0B43     		orrs	r3, r1
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  93              		.loc 2 741 30 view .LVU22
  94 002c 0362     		str	r3, [r0, #32]
  95              	.LVL4:
 741:Core/core_cm0.h ****        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
  96              		.loc 2 741 30 view .LVU23
  97              	.LBE21:
  98              	.LBE23:
 932:Core/core_cm0.h ****   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Val
  99              		.loc 2 932 3 is_stmt 1 view .LVU24
 100              		.loc 2 932 18 is_stmt 0 view .LVU25
 101 002e 0023     		movs	r3, #0
 102 0030 9360     		str	r3, [r2, #8]
 933:Core/core_cm0.h ****   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 103              		.loc 2 933 3 is_stmt 1 view .LVU26
 104              		.loc 2 933 18 is_stmt 0 view .LVU27
 105 0032 0733     		adds	r3, r3, #7
 106              	.LBE17:
 107              	.LBE16:
  27:User/bsp.c    ****   task_init(&g_task_handle);
 108              		.loc 1 27 3 view .LVU28
 109 0034 0E48     		ldr	r0, .L3+12
 110              	.LBB25:
 111              	.LBB24:
 112              		.loc 2 933 18 view .LVU29
ARM GAS  /tmp/ccSm0G8b.s 			page 20


 113 0036 1360     		str	r3, [r2]
 934:Core/core_cm0.h ****                    SysTick_CTRL_TICKINT_Msk   |
 935:Core/core_cm0.h ****                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTi
 936:Core/core_cm0.h ****   return (0UL);                                                     /* Function successful */
 114              		.loc 2 936 3 is_stmt 1 view .LVU30
 115              	.LVL5:
 116              		.loc 2 936 3 is_stmt 0 view .LVU31
 117              	.LBE24:
 118              	.LBE25:
 119              		.loc 1 27 3 is_stmt 1 view .LVU32
 120 0038 FFF7FEFF 		bl	task_init
 121              	.LVL6:
  28:User/bsp.c    ****   flash_init();
 122              		.loc 1 28 3 view .LVU33
 123 003c FFF7FEFF 		bl	flash_init
 124              	.LVL7:
  29:User/bsp.c    ****   save_read();
 125              		.loc 1 29 3 view .LVU34
 126 0040 FFF7FEFF 		bl	save_read
 127              	.LVL8:
  30:User/bsp.c    **** 
  31:User/bsp.c    ****   __disable_irq(); // 禁止中断
 128              		.loc 1 31 3 view .LVU35
 129              	.LBB26:
 130              	.LBI26:
 131              		.file 3 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
ARM GAS  /tmp/ccSm0G8b.s 			page 21


  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
ARM GAS  /tmp/ccSm0G8b.s 			page 22


  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 23


 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
ARM GAS  /tmp/ccSm0G8b.s 			page 24


 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 259:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccSm0G8b.s 			page 25


 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
ARM GAS  /tmp/ccSm0G8b.s 			page 26


 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
ARM GAS  /tmp/ccSm0G8b.s 			page 27


 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
ARM GAS  /tmp/ccSm0G8b.s 			page 28


 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
ARM GAS  /tmp/ccSm0G8b.s 			page 29


 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 30


 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 31


 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/ccSm0G8b.s 			page 32


 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
ARM GAS  /tmp/ccSm0G8b.s 			page 33


 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
ARM GAS  /tmp/ccSm0G8b.s 			page 34


 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
ARM GAS  /tmp/ccSm0G8b.s 			page 35


 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
ARM GAS  /tmp/ccSm0G8b.s 			page 36


 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccSm0G8b.s 			page 37


 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 132              		.loc 3 960 27 view .LVU36
 133              	.LBB27:
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 134              		.loc 3 962 3 view .LVU37
 135              		.syntax divided
 136              	@ 962 "Core/cmsis_gcc.h" 1
 137 0044 72B6     		cpsid i
 138              	@ 0 "" 2
 139              		.thumb
 140              		.syntax unified
 141              	.LBE27:
 142              	.LBE26:
  32:User/bsp.c    **** 
  33:User/bsp.c    ****   adc_init();
 143              		.loc 1 33 3 view .LVU38
 144 0046 FFF7FEFF 		bl	adc_init
 145              	.LVL9:
  34:User/bsp.c    ****   opa_init();
 146              		.loc 1 34 3 view .LVU39
 147 004a FFF7FEFF 		bl	opa_init
 148              	.LVL10:
  35:User/bsp.c    ****   pwm_init();
 149              		.loc 1 35 3 view .LVU40
 150 004e FFF7FEFF 		bl	pwm_init
 151              	.LVL11:
  36:User/bsp.c    ****   uart_init();
 152              		.loc 1 36 3 view .LVU41
 153 0052 FFF7FEFF 		bl	uart_init
 154              	.LVL12:
  37:User/bsp.c    **** 
  38:User/bsp.c    **** 
  39:User/bsp.c    ****   motor_init();
 155              		.loc 1 39 3 view .LVU42
 156 0056 FFF7FEFF 		bl	motor_init
 157              	.LVL13:
  40:User/bsp.c    ****   protocol_init();
 158              		.loc 1 40 3 view .LVU43
 159 005a FFF7FEFF 		bl	protocol_init
 160              	.LVL14:
ARM GAS  /tmp/ccSm0G8b.s 			page 38


  41:User/bsp.c    **** 
  42:User/bsp.c    ****   __enable_irq(); // 允许中断
 161              		.loc 1 42 3 view .LVU44
 162              	.LBB28:
 163              	.LBI28:
 949:Core/cmsis_gcc.h **** {
 164              		.loc 3 949 27 view .LVU45
 165              	.LBB29:
 951:Core/cmsis_gcc.h **** }
 166              		.loc 3 951 3 view .LVU46
 167              		.syntax divided
 168              	@ 951 "Core/cmsis_gcc.h" 1
 169 005e 62B6     		cpsie i
 170              	@ 0 "" 2
 171              		.thumb
 172              		.syntax unified
 173              	.LBE29:
 174              	.LBE28:
  43:User/bsp.c    **** 
  44:User/bsp.c    **** }
 175              		.loc 1 44 1 is_stmt 0 view .LVU47
 176              		@ sp needed
 177 0060 10BD     		pop	{r4, pc}
 178              	.L4:
 179 0062 C046     		.align	2
 180              	.L3:
 181 0064 10E000E0 		.word	-536813552
 182 0068 FF760100 		.word	95999
 183 006c 00ED00E0 		.word	-536810240
 184 0070 00000000 		.word	g_task_handle
 185              		.cfi_endproc
 186              	.LFE45:
 188              		.text
 189              	.Letext0:
 190              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 191              		.file 5 "Library/inc/lcm32f06x.h"
 192              		.file 6 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 193              		.file 7 "Component/task/task_define.h"
 194              		.file 8 "User/protocol.h"
 195              		.file 9 "User/motor.h"
 196              		.file 10 "Hardware/uart.h"
 197              		.file 11 "Hardware/pwm.h"
 198              		.file 12 "Hardware/opa.h"
 199              		.file 13 "Hardware/adc.h"
 200              		.file 14 "User/global.h"
 201              		.file 15 "Hardware/flash.h"
 202              		.file 16 "Library/inc/lcm32f06x_rcc.h"
 203              		.file 17 "Component/task/task.h"
ARM GAS  /tmp/ccSm0G8b.s 			page 39


DEFINED SYMBOLS
                            *ABS*:00000000 bsp.c
     /tmp/ccSm0G8b.s:17     .text.bsp_init:00000000 $t
     /tmp/ccSm0G8b.s:24     .text.bsp_init:00000000 bsp_init
     /tmp/ccSm0G8b.s:181    .text.bsp_init:00000064 $d

UNDEFINED SYMBOLS
RCC_APB0PeriphClockCmd
RCC_AHBPeriphClockCmd
SetSysClock
task_init
flash_init
save_read
adc_init
opa_init
pwm_init
uart_init
motor_init
protocol_init
g_task_handle
