ARM GAS  /tmp/ccCoaTlC.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"pwm.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Hardware/pwm.c"
  16              		.section	.text.pwm_init,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	pwm_init
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	pwm_init:
  25              	.LFB45:
   1:Hardware/pwm.c **** #include "pwm.h"
   2:Hardware/pwm.c **** #include "lcm32f06x_conf.h"
   3:Hardware/pwm.c **** 
   4:Hardware/pwm.c **** void pwm_init(void)
   5:Hardware/pwm.c **** {
  26              		.loc 1 5 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 88
  29              		@ frame_needed = 0, uses_anonymous_args = 0
   6:Hardware/pwm.c ****     RCC_APB0PeriphClockCmd(RCC_APB0Periph_TIM1, ENABLE);
  30              		.loc 1 6 5 view .LVU1
  31 0000 8020     		movs	r0, #128
   5:Hardware/pwm.c ****     RCC_APB0PeriphClockCmd(RCC_APB0Periph_TIM1, ENABLE);
  32              		.loc 1 5 1 is_stmt 0 view .LVU2
  33 0002 70B5     		push	{r4, r5, r6, lr}
  34              	.LCFI0:
  35              		.cfi_def_cfa_offset 16
  36              		.cfi_offset 4, -16
  37              		.cfi_offset 5, -12
  38              		.cfi_offset 6, -8
  39              		.cfi_offset 14, -4
  40              		.loc 1 6 5 view .LVU3
  41 0004 0121     		movs	r1, #1
   5:Hardware/pwm.c ****     RCC_APB0PeriphClockCmd(RCC_APB0Periph_TIM1, ENABLE);
  42              		.loc 1 5 1 view .LVU4
  43 0006 96B0     		sub	sp, sp, #88
  44              	.LCFI1:
  45              		.cfi_def_cfa_offset 104
  46              		.loc 1 6 5 view .LVU5
  47 0008 0003     		lsls	r0, r0, #12
  48 000a FFF7FEFF 		bl	RCC_APB0PeriphClockCmd
  49              	.LVL0:
   7:Hardware/pwm.c ****     RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB, ENABLE);
ARM GAS  /tmp/ccCoaTlC.s 			page 2


  50              		.loc 1 7 5 is_stmt 1 view .LVU6
  51 000e 0121     		movs	r1, #1
  52 0010 0320     		movs	r0, #3
  53 0012 FFF7FEFF 		bl	RCC_AHBPeriphClockCmd
  54              	.LVL1:
   8:Hardware/pwm.c **** 
   9:Hardware/pwm.c ****     GPIO_InitTypeDef GPIO_InitStructure;
  55              		.loc 1 9 5 view .LVU7
  10:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8;
  56              		.loc 1 10 5 view .LVU8
  57              		.loc 1 10 33 is_stmt 0 view .LVU9
  58 0016 F823     		movs	r3, #248
  59 0018 5B00     		lsls	r3, r3, #1
  60 001a 0093     		str	r3, [sp]
  11:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
  61              		.loc 1 11 5 is_stmt 1 view .LVU10
  12:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_2;
  62              		.loc 1 12 5 view .LVU11
  13:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
  63              		.loc 1 13 5 view .LVU12
  14:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  64              		.loc 1 14 5 view .LVU13
  11:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_2;
  65              		.loc 1 11 34 is_stmt 0 view .LVU14
  66 001c 4D4B     		ldr	r3, .L3
  15:Hardware/pwm.c ****     GPIO_Init(GPIOB, &GPIO_InitStructure);
  67              		.loc 1 15 5 view .LVU15
  68 001e 6946     		mov	r1, sp
  69 0020 4D48     		ldr	r0, .L3+4
  11:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_2;
  70              		.loc 1 11 34 view .LVU16
  71 0022 0193     		str	r3, [sp, #4]
  72              		.loc 1 15 5 is_stmt 1 view .LVU17
  73 0024 FFF7FEFF 		bl	GPIO_Init
  74              	.LVL2:
  16:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
  75              		.loc 1 16 5 view .LVU18
  17:Hardware/pwm.c ****     GPIO_Init(GPIOA, &GPIO_InitStructure);
  76              		.loc 1 17 5 is_stmt 0 view .LVU19
  77 0028 9020     		movs	r0, #144
  16:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
  78              		.loc 1 16 33 view .LVU20
  79 002a 0426     		movs	r6, #4
  80              		.loc 1 17 5 view .LVU21
  81 002c 6946     		mov	r1, sp
  82 002e C005     		lsls	r0, r0, #23
  16:Hardware/pwm.c ****     GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
  83              		.loc 1 16 33 view .LVU22
  84 0030 0096     		str	r6, [sp]
  85              		.loc 1 17 5 is_stmt 1 view .LVU23
  86 0032 FFF7FEFF 		bl	GPIO_Init
  87              	.LVL3:
  18:Hardware/pwm.c **** 
  19:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOB, GPIO_PinSource4, GPIO_AF_4); // LO3
  88              		.loc 1 19 5 view .LVU24
  89 0036 0422     		movs	r2, #4
  90 0038 0421     		movs	r1, #4
ARM GAS  /tmp/ccCoaTlC.s 			page 3


  91 003a 4748     		ldr	r0, .L3+4
  92 003c FFF7FEFF 		bl	GPIO_PinAFConfig
  93              	.LVL4:
  20:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_6); // LO2
  94              		.loc 1 20 5 view .LVU25
  95 0040 0622     		movs	r2, #6
  96 0042 0521     		movs	r1, #5
  97 0044 4448     		ldr	r0, .L3+4
  98 0046 FFF7FEFF 		bl	GPIO_PinAFConfig
  99              	.LVL5:
  21:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_4); // LO1
 100              		.loc 1 21 5 view .LVU26
 101 004a 0422     		movs	r2, #4
 102 004c 0621     		movs	r1, #6
 103 004e 4248     		ldr	r0, .L3+4
 104 0050 FFF7FEFF 		bl	GPIO_PinAFConfig
 105              	.LVL6:
  22:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOB, GPIO_PinSource7, GPIO_AF_5); // HO3
 106              		.loc 1 22 5 view .LVU27
 107 0054 0522     		movs	r2, #5
 108 0056 0721     		movs	r1, #7
 109 0058 3F48     		ldr	r0, .L3+4
 110 005a FFF7FEFF 		bl	GPIO_PinAFConfig
 111              	.LVL7:
  23:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_2); // HO2
 112              		.loc 1 23 5 view .LVU28
 113 005e 0222     		movs	r2, #2
 114 0060 0821     		movs	r1, #8
 115 0062 3D48     		ldr	r0, .L3+4
 116 0064 FFF7FEFF 		bl	GPIO_PinAFConfig
 117              	.LVL8:
  24:Hardware/pwm.c ****     GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_2); // HO1
 118              		.loc 1 24 5 view .LVU29
 119 0068 9020     		movs	r0, #144
 120 006a 0222     		movs	r2, #2
 121 006c 0221     		movs	r1, #2
 122 006e C005     		lsls	r0, r0, #23
 123 0070 FFF7FEFF 		bl	GPIO_PinAFConfig
 124              	.LVL9:
  25:Hardware/pwm.c **** 
  26:Hardware/pwm.c ****     TIM_TimeBaseInitTypeDef tim_base_struct;
 125              		.loc 1 26 5 view .LVU30
  27:Hardware/pwm.c **** 
  28:Hardware/pwm.c ****     TIM_TimeBaseStructInit(&tim_base_struct);
 126              		.loc 1 28 5 view .LVU31
 127 0074 02A8     		add	r0, sp, #8
 128 0076 FFF7FEFF 		bl	TIM_TimeBaseStructInit
 129              	.LVL10:
  29:Hardware/pwm.c ****     tim_base_struct.TIM_Prescaler = 1; // 中心对齐，24M
 130              		.loc 1 29 5 view .LVU32
  30:Hardware/pwm.c ****     tim_base_struct.TIM_Period = PWM_TIM_CNT;
 131              		.loc 1 30 32 is_stmt 0 view .LVU33
 132 007a 384B     		ldr	r3, .L3+8
  29:Hardware/pwm.c ****     tim_base_struct.TIM_Prescaler = 1; // 中心对齐，24M
 133              		.loc 1 29 35 view .LVU34
 134 007c 0125     		movs	r5, #1
 135              		.loc 1 30 32 view .LVU35
ARM GAS  /tmp/ccCoaTlC.s 			page 4


 136 007e 0493     		str	r3, [sp, #16]
  31:Hardware/pwm.c ****     tim_base_struct.TIM_CounterMode = TIM_CounterMode_CenterAligned2;
 137              		.loc 1 31 37 view .LVU36
 138 0080 4023     		movs	r3, #64
  32:Hardware/pwm.c ****     TIM_TimeBaseInit(TIM1, &tim_base_struct);
 139              		.loc 1 32 5 view .LVU37
 140 0082 374C     		ldr	r4, .L3+12
 141 0084 02A9     		add	r1, sp, #8
 142 0086 2000     		movs	r0, r4
  31:Hardware/pwm.c ****     tim_base_struct.TIM_CounterMode = TIM_CounterMode_CenterAligned2;
 143              		.loc 1 31 37 view .LVU38
 144 0088 0393     		str	r3, [sp, #12]
  29:Hardware/pwm.c ****     tim_base_struct.TIM_Period = PWM_TIM_CNT;
 145              		.loc 1 29 35 view .LVU39
 146 008a 0295     		str	r5, [sp, #8]
  30:Hardware/pwm.c ****     tim_base_struct.TIM_CounterMode = TIM_CounterMode_CenterAligned2;
 147              		.loc 1 30 5 is_stmt 1 view .LVU40
  31:Hardware/pwm.c ****     TIM_TimeBaseInit(TIM1, &tim_base_struct);
 148              		.loc 1 31 5 view .LVU41
 149              		.loc 1 32 5 view .LVU42
 150 008c FFF7FEFF 		bl	TIM_TimeBaseInit
 151              	.LVL11:
  33:Hardware/pwm.c **** 
  34:Hardware/pwm.c ****     TIM_OCInitTypeDef tim_oc_struct;
 152              		.loc 1 34 5 view .LVU43
  35:Hardware/pwm.c ****     TIM_OCStructInit(&tim_oc_struct);
 153              		.loc 1 35 5 view .LVU44
 154 0090 0EA8     		add	r0, sp, #56
 155 0092 FFF7FEFF 		bl	TIM_OCStructInit
 156              	.LVL12:
  36:Hardware/pwm.c ****     tim_oc_struct.TIM_OCMode = TIM_OCMode_PWM1;
 157              		.loc 1 36 5 view .LVU45
 158              		.loc 1 36 30 is_stmt 0 view .LVU46
 159 0096 6023     		movs	r3, #96
  37:Hardware/pwm.c ****     tim_oc_struct.TIM_OutputState = TIM_OutputState_Enable;
 160              		.loc 1 37 35 view .LVU47
 161 0098 0F95     		str	r5, [sp, #60]
  38:Hardware/pwm.c ****     tim_oc_struct.TIM_OCPolarity = TIM_OCPolarity_High;
 162              		.loc 1 38 34 view .LVU48
 163 009a 0025     		movs	r5, #0
  39:Hardware/pwm.c ****     tim_oc_struct.TIM_OCIdleState = TIM_OCIdleState_Reset; // 关闭输出时为低
  40:Hardware/pwm.c ****     tim_oc_struct.TIM_OutputNState = TIM_OutputNState_Enable;
  41:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNPolarity = TIM_OCNPolarity_High;
  42:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNIdleState = TIM_OCNIdleState_Reset; // 关闭输出时为低
  43:Hardware/pwm.c **** 
  44:Hardware/pwm.c ****     TIM_OC1Init(TIM1, &tim_oc_struct);
 164              		.loc 1 44 5 view .LVU49
 165 009c 2000     		movs	r0, r4
 166 009e 0EA9     		add	r1, sp, #56
  36:Hardware/pwm.c ****     tim_oc_struct.TIM_OutputState = TIM_OutputState_Enable;
 167              		.loc 1 36 30 view .LVU50
 168 00a0 0E93     		str	r3, [sp, #56]
  37:Hardware/pwm.c ****     tim_oc_struct.TIM_OCPolarity = TIM_OCPolarity_High;
 169              		.loc 1 37 5 is_stmt 1 view .LVU51
  38:Hardware/pwm.c ****     tim_oc_struct.TIM_OCIdleState = TIM_OCIdleState_Reset; // 关闭输出时为低
 170              		.loc 1 38 5 view .LVU52
  38:Hardware/pwm.c ****     tim_oc_struct.TIM_OCIdleState = TIM_OCIdleState_Reset; // 关闭输出时为低
ARM GAS  /tmp/ccCoaTlC.s 			page 5


 171              		.loc 1 38 34 is_stmt 0 view .LVU53
 172 00a2 1295     		str	r5, [sp, #72]
  39:Hardware/pwm.c ****     tim_oc_struct.TIM_OutputNState = TIM_OutputNState_Enable;
 173              		.loc 1 39 5 is_stmt 1 view .LVU54
  39:Hardware/pwm.c ****     tim_oc_struct.TIM_OutputNState = TIM_OutputNState_Enable;
 174              		.loc 1 39 35 is_stmt 0 view .LVU55
 175 00a4 1495     		str	r5, [sp, #80]
  40:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNPolarity = TIM_OCNPolarity_High;
 176              		.loc 1 40 5 is_stmt 1 view .LVU56
  40:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNPolarity = TIM_OCNPolarity_High;
 177              		.loc 1 40 36 is_stmt 0 view .LVU57
 178 00a6 1096     		str	r6, [sp, #64]
  41:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNIdleState = TIM_OCNIdleState_Reset; // 关闭输出时为低
 179              		.loc 1 41 5 is_stmt 1 view .LVU58
  41:Hardware/pwm.c ****     tim_oc_struct.TIM_OCNIdleState = TIM_OCNIdleState_Reset; // 关闭输出时为低
 180              		.loc 1 41 35 is_stmt 0 view .LVU59
 181 00a8 1395     		str	r5, [sp, #76]
  42:Hardware/pwm.c **** 
 182              		.loc 1 42 5 is_stmt 1 view .LVU60
  42:Hardware/pwm.c **** 
 183              		.loc 1 42 36 is_stmt 0 view .LVU61
 184 00aa 1595     		str	r5, [sp, #84]
 185              		.loc 1 44 5 is_stmt 1 view .LVU62
 186 00ac FFF7FEFF 		bl	TIM_OC1Init
 187              	.LVL13:
  45:Hardware/pwm.c ****     TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
 188              		.loc 1 45 5 view .LVU63
 189 00b0 2000     		movs	r0, r4
 190 00b2 0821     		movs	r1, #8
 191 00b4 FFF7FEFF 		bl	TIM_OC1PreloadConfig
 192              	.LVL14:
  46:Hardware/pwm.c ****     TIM_OC2Init(TIM1, &tim_oc_struct);
 193              		.loc 1 46 5 view .LVU64
 194 00b8 2000     		movs	r0, r4
 195 00ba 0EA9     		add	r1, sp, #56
 196 00bc FFF7FEFF 		bl	TIM_OC2Init
 197              	.LVL15:
  47:Hardware/pwm.c ****     TIM_OC2PreloadConfig(TIM1, TIM_OCPreload_Enable);
 198              		.loc 1 47 5 view .LVU65
 199 00c0 2000     		movs	r0, r4
 200 00c2 0821     		movs	r1, #8
 201 00c4 FFF7FEFF 		bl	TIM_OC2PreloadConfig
 202              	.LVL16:
  48:Hardware/pwm.c ****     TIM_OC3Init(TIM1, &tim_oc_struct);
 203              		.loc 1 48 5 view .LVU66
 204 00c8 2000     		movs	r0, r4
 205 00ca 0EA9     		add	r1, sp, #56
 206 00cc FFF7FEFF 		bl	TIM_OC3Init
 207              	.LVL17:
  49:Hardware/pwm.c ****     TIM_OC3PreloadConfig(TIM1, TIM_OCPreload_Enable);
 208              		.loc 1 49 5 view .LVU67
 209 00d0 2000     		movs	r0, r4
 210 00d2 0821     		movs	r1, #8
 211 00d4 FFF7FEFF 		bl	TIM_OC3PreloadConfig
 212              	.LVL18:
  50:Hardware/pwm.c ****     tim_oc_struct.TIM_Pulse = PWM_TRIG_VAL;
 213              		.loc 1 50 5 view .LVU68
ARM GAS  /tmp/ccCoaTlC.s 			page 6


 214              		.loc 1 50 29 is_stmt 0 view .LVU69
 215 00d8 224B     		ldr	r3, .L3+16
  51:Hardware/pwm.c ****     TIM_OC4Init(TIM1, &tim_oc_struct);
 216              		.loc 1 51 5 view .LVU70
 217 00da 2000     		movs	r0, r4
 218 00dc 0EA9     		add	r1, sp, #56
  50:Hardware/pwm.c ****     tim_oc_struct.TIM_Pulse = PWM_TRIG_VAL;
 219              		.loc 1 50 29 view .LVU71
 220 00de 1193     		str	r3, [sp, #68]
 221              		.loc 1 51 5 is_stmt 1 view .LVU72
 222 00e0 FFF7FEFF 		bl	TIM_OC4Init
 223              	.LVL19:
  52:Hardware/pwm.c **** 
  53:Hardware/pwm.c ****     TIM_ARRPreloadConfig(TIM1, ENABLE);
 224              		.loc 1 53 5 view .LVU73
 225 00e4 2000     		movs	r0, r4
 226 00e6 0121     		movs	r1, #1
 227 00e8 FFF7FEFF 		bl	TIM_ARRPreloadConfig
 228              	.LVL20:
  54:Hardware/pwm.c **** 
  55:Hardware/pwm.c ****     TIM_BDTRInitTypeDef tim_bdtr_struct;
 229              		.loc 1 55 5 view .LVU74
  56:Hardware/pwm.c ****     tim_bdtr_struct.TIM_LOCKLevel = TIM_LOCKLevel_OFF;
 230              		.loc 1 56 5 view .LVU75
  57:Hardware/pwm.c ****     tim_bdtr_struct.TIM_DeadTime = 47; // 1us
 231              		.loc 1 57 34 is_stmt 0 view .LVU76
 232 00ec 2F23     		movs	r3, #47
 233 00ee 0A93     		str	r3, [sp, #40]
  58:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSIState = TIM_OSSIState_Enable;
 234              		.loc 1 58 35 view .LVU77
 235 00f0 8023     		movs	r3, #128
  59:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSRState = TIM_OSSRState_Disable;
  60:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break = TIM_Break_Disable;
  61:Hardware/pwm.c ****     tim_bdtr_struct.TIM_BreakPolarity = TIM_BreakPolarity_Low;
  62:Hardware/pwm.c ****     tim_bdtr_struct.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
  63:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break2 = TIM_Break_Disable;
  64:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break2Polarity = TIM_BreakPolarity_Low;
  65:Hardware/pwm.c ****     tim_bdtr_struct.TIM_AutomaticOutput2 = TIM_AutomaticOutput_Disable;
  66:Hardware/pwm.c ****     TIM_BDTRConfig(TIM1, &tim_bdtr_struct);
 236              		.loc 1 66 5 view .LVU78
 237 00f2 2000     		movs	r0, r4
  58:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSIState = TIM_OSSIState_Enable;
 238              		.loc 1 58 35 view .LVU79
 239 00f4 DB00     		lsls	r3, r3, #3
 240              		.loc 1 66 5 view .LVU80
 241 00f6 07A9     		add	r1, sp, #28
  58:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSIState = TIM_OSSIState_Enable;
 242              		.loc 1 58 35 view .LVU81
 243 00f8 0893     		str	r3, [sp, #32]
  56:Hardware/pwm.c ****     tim_bdtr_struct.TIM_DeadTime = 47; // 1us
 244              		.loc 1 56 35 view .LVU82
 245 00fa 0995     		str	r5, [sp, #36]
  57:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSIState = TIM_OSSIState_Enable;
 246              		.loc 1 57 5 is_stmt 1 view .LVU83
  58:Hardware/pwm.c ****     tim_bdtr_struct.TIM_OSSRState = TIM_OSSRState_Disable;
 247              		.loc 1 58 5 view .LVU84
  59:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break = TIM_Break_Disable;
ARM GAS  /tmp/ccCoaTlC.s 			page 7


 248              		.loc 1 59 5 view .LVU85
  59:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break = TIM_Break_Disable;
 249              		.loc 1 59 35 is_stmt 0 view .LVU86
 250 00fc 0795     		str	r5, [sp, #28]
  60:Hardware/pwm.c ****     tim_bdtr_struct.TIM_BreakPolarity = TIM_BreakPolarity_Low;
 251              		.loc 1 60 5 is_stmt 1 view .LVU87
  61:Hardware/pwm.c ****     tim_bdtr_struct.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
 252              		.loc 1 61 5 view .LVU88
  62:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break2 = TIM_Break_Disable;
 253              		.loc 1 62 5 view .LVU89
  63:Hardware/pwm.c ****     tim_bdtr_struct.TIM_Break2Polarity = TIM_BreakPolarity_Low;
 254              		.loc 1 63 5 view .LVU90
  64:Hardware/pwm.c ****     tim_bdtr_struct.TIM_AutomaticOutput2 = TIM_AutomaticOutput_Disable;
 255              		.loc 1 64 5 view .LVU91
  65:Hardware/pwm.c ****     TIM_BDTRConfig(TIM1, &tim_bdtr_struct);
 256              		.loc 1 65 5 view .LVU92
  60:Hardware/pwm.c ****     tim_bdtr_struct.TIM_BreakPolarity = TIM_BreakPolarity_Low;
 257              		.loc 1 60 31 is_stmt 0 view .LVU93
 258 00fe 0B95     		str	r5, [sp, #44]
 259 0100 0C95     		str	r5, [sp, #48]
 260 0102 0D95     		str	r5, [sp, #52]
 261              		.loc 1 66 5 is_stmt 1 view .LVU94
 262 0104 FFF7FEFF 		bl	TIM_BDTRConfig
 263              	.LVL21:
  67:Hardware/pwm.c **** 
  68:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM3, TIM1_PWMx_OC1);  // UH
 264              		.loc 1 68 5 view .LVU95
 265 0108 0021     		movs	r1, #0
 266 010a 0220     		movs	r0, #2
 267 010c FFF7FEFF 		bl	TIM1_PWMxSel_Config
 268              	.LVL22:
  69:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM7, TIM1_PWMx_OC1N); // UL
 269              		.loc 1 69 5 view .LVU96
 270 0110 0421     		movs	r1, #4
 271 0112 0620     		movs	r0, #6
 272 0114 FFF7FEFF 		bl	TIM1_PWMxSel_Config
 273              	.LVL23:
  70:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM2, TIM1_PWMx_OC2);  // VH
 274              		.loc 1 70 5 view .LVU97
 275 0118 0121     		movs	r1, #1
 276 011a 0120     		movs	r0, #1
 277 011c FFF7FEFF 		bl	TIM1_PWMxSel_Config
 278              	.LVL24:
  71:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM6, TIM1_PWMx_OC2N); // VL
 279              		.loc 1 71 5 view .LVU98
 280 0120 0521     		movs	r1, #5
 281 0122 0520     		movs	r0, #5
 282 0124 FFF7FEFF 		bl	TIM1_PWMxSel_Config
 283              	.LVL25:
  72:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM4, TIM1_PWMx_OC3);  // WH
 284              		.loc 1 72 5 view .LVU99
 285 0128 0221     		movs	r1, #2
 286 012a 0320     		movs	r0, #3
 287 012c FFF7FEFF 		bl	TIM1_PWMxSel_Config
 288              	.LVL26:
  73:Hardware/pwm.c ****     TIM1_PWMxSel_Config(TIM1_PWM5, TIM1_PWMx_OC3N); // WL
 289              		.loc 1 73 5 view .LVU100
ARM GAS  /tmp/ccCoaTlC.s 			page 8


 290 0130 0621     		movs	r1, #6
 291 0132 0420     		movs	r0, #4
 292 0134 FFF7FEFF 		bl	TIM1_PWMxSel_Config
 293              	.LVL27:
  74:Hardware/pwm.c **** 
  75:Hardware/pwm.c ****     TIM_CtrlPWMOutputs(TIM1, ENABLE);
 294              		.loc 1 75 5 view .LVU101
 295 0138 2000     		movs	r0, r4
 296 013a 0121     		movs	r1, #1
 297 013c FFF7FEFF 		bl	TIM_CtrlPWMOutputs
 298              	.LVL28:
  76:Hardware/pwm.c **** 
  77:Hardware/pwm.c ****     PWMOUT_DISABLE(); // 禁用PWM输出
 299              		.loc 1 77 5 view .LVU102
 300 0140 236A     		ldr	r3, [r4, #32]
 301 0142 094A     		ldr	r2, .L3+20
  78:Hardware/pwm.c **** 
  79:Hardware/pwm.c ****     TIM_Cmd(TIM1, ENABLE);
 302              		.loc 1 79 5 is_stmt 0 view .LVU103
 303 0144 0121     		movs	r1, #1
  77:Hardware/pwm.c **** 
 304              		.loc 1 77 5 view .LVU104
 305 0146 1340     		ands	r3, r2
 306              		.loc 1 79 5 view .LVU105
 307 0148 2000     		movs	r0, r4
  77:Hardware/pwm.c **** 
 308              		.loc 1 77 5 view .LVU106
 309 014a 2362     		str	r3, [r4, #32]
 310              		.loc 1 79 5 is_stmt 1 view .LVU107
 311 014c FFF7FEFF 		bl	TIM_Cmd
 312              	.LVL29:
  80:Hardware/pwm.c **** }...
 313              		.loc 1 80 1 is_stmt 0 view .LVU108
 314 0150 16B0     		add	sp, sp, #88
 315              		@ sp needed
 316 0152 70BD     		pop	{r4, r5, r6, pc}
 317              	.L4:
 318              		.align	2
 319              	.L3:
 320 0154 02000002 		.word	33554434
 321 0158 00020048 		.word	1207960064
 322 015c DB050000 		.word	1499
 323 0160 00000140 		.word	1073807360
 324 0164 32050000 		.word	1330
 325 0168 AAFAFFFF 		.word	-1366
 326              		.cfi_endproc
 327              	.LFE45:
 329              		.text
 330              	.Letext0:
 331              		.file 2 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 332              		.file 3 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 333              		.file 4 "Library/inc/lcm32f06x.h"
 334              		.file 5 "Library/inc/lcm32f06x_tim.h"
 335              		.file 6 "Library/inc/lcm32f06x_gpio.h"
 336              		.file 7 "Library/inc/lcm32f06x_rcc.h"
ARM GAS  /tmp/ccCoaTlC.s 			page 9


DEFINED SYMBOLS
                            *ABS*:00000000 pwm.c
     /tmp/ccCoaTlC.s:17     .text.pwm_init:00000000 $t
     /tmp/ccCoaTlC.s:24     .text.pwm_init:00000000 pwm_init
     /tmp/ccCoaTlC.s:320    .text.pwm_init:00000154 $d

UNDEFINED SYMBOLS
RCC_APB0PeriphClockCmd
RCC_AHBPeriphClockCmd
GPIO_Init
GPIO_PinAFConfig
TIM_TimeBaseStructInit
TIM_TimeBaseInit
TIM_OCStructInit
TIM_OC1Init
TIM_OC1PreloadConfig
TIM_OC2Init
TIM_OC2PreloadConfig
TIM_OC3Init
TIM_OC3PreloadConfig
TIM_OC4Init
TIM_ARRPreloadConfig
TIM_BDTRConfig
TIM1_PWMxSel_Config
TIM_CtrlPWMOutputs
TIM_Cmd
