ARM GAS  /tmp/ccQ8FEb0.s 			page 1


   1              		.cpu cortex-m0
   2              		.arch armv6s-m
   3              		.fpu softvfp
   4              		.eabi_attribute 23, 1
   5              		.eabi_attribute 24, 1
   6              		.eabi_attribute 25, 1
   7              		.eabi_attribute 26, 1
   8              		.eabi_attribute 30, 2
   9              		.eabi_attribute 34, 0
  10              		.eabi_attribute 18, 4
  11              		.file	"lcm32f06x_acmp.c"
  12              		.text
  13              	.Ltext0:
  14              		.cfi_sections	.debug_frame
  15              		.file 1 "Library/src/lcm32f06x_acmp.c"
  16              		.section	.text.ACMP_DeInit,"ax",%progbits
  17              		.align	1
  18              		.p2align 2,,3
  19              		.global	ACMP_DeInit
  20              		.syntax unified
  21              		.code	16
  22              		.thumb_func
  24              	ACMP_DeInit:
  25              	.LFB45:
   1:Library/src/lcm32f06x_acmp.c **** /**
   2:Library/src/lcm32f06x_acmp.c ****   ******************************************************************************
   3:Library/src/lcm32f06x_acmp.c ****   * @file    lcm32f06x_acmp.c
   4:Library/src/lcm32f06x_acmp.c ****   * @author  System R&D Team
   5:Library/src/lcm32f06x_acmp.c ****   * @version V2.0.2
   6:Library/src/lcm32f06x_acmp.c ****   * @date    10-April-2025
   7:Library/src/lcm32f06x_acmp.c ****   * @brief   This file provides all the ACMP firmware functions.
   8:Library/src/lcm32f06x_acmp.c ****   ******************************************************************************
   9:Library/src/lcm32f06x_acmp.c ****   * @attention
  10:Library/src/lcm32f06x_acmp.c ****   *
  11:Library/src/lcm32f06x_acmp.c ****   * Copyright (c) Hangzhou Lingxin Microelectronics Co.
  12:Library/src/lcm32f06x_acmp.c ****   * All rights reserved.
  13:Library/src/lcm32f06x_acmp.c ****   *
  14:Library/src/lcm32f06x_acmp.c ****   * This software is licensed under terms that can be found in the LICENSE file
  15:Library/src/lcm32f06x_acmp.c ****   * in the root directory of this software component.
  16:Library/src/lcm32f06x_acmp.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  17:Library/src/lcm32f06x_acmp.c ****   *
  18:Library/src/lcm32f06x_acmp.c ****   ******************************************************************************
  19:Library/src/lcm32f06x_acmp.c ****   */
  20:Library/src/lcm32f06x_acmp.c **** 
  21:Library/src/lcm32f06x_acmp.c **** /* Includes ------------------------------------------------------------------*/
  22:Library/src/lcm32f06x_acmp.c **** #include "lcm32f06x_acmp.h"
  23:Library/src/lcm32f06x_acmp.c **** 
  24:Library/src/lcm32f06x_acmp.c **** /**
  25:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP_DeInit
  26:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Deinitializes ACMP peripheral registers to their default reset values.
  27:Library/src/lcm32f06x_acmp.c ****   *         CN: 将 ACMP 外设寄存器初始化为其默认重置值。
  28:Library/src/lcm32f06x_acmp.c ****   * @param  None
  29:Library/src/lcm32f06x_acmp.c ****   * @retval None
  30:Library/src/lcm32f06x_acmp.c ****   * @note   EN: DAC ACMP and OPA share the same clock enable which can be used once.
  31:Library/src/lcm32f06x_acmp.c ****   *         CN: DAC ACMP OPA 共用一个时钟使能，使用一次即可。
  32:Library/src/lcm32f06x_acmp.c ****   */
  33:Library/src/lcm32f06x_acmp.c **** void ACMP_DeInit(void)
ARM GAS  /tmp/ccQ8FEb0.s 			page 2


  34:Library/src/lcm32f06x_acmp.c **** {
  26              		.loc 1 34 1 view -0
  27              		.cfi_startproc
  28              		@ args = 0, pretend = 0, frame = 0
  29              		@ frame_needed = 0, uses_anonymous_args = 0
  35:Library/src/lcm32f06x_acmp.c ****   RCC_APB0PeriphResetCmd(RCC_APB0Periph_ANACTRL, ENABLE);
  30              		.loc 1 35 3 view .LVU1
  34:Library/src/lcm32f06x_acmp.c ****   RCC_APB0PeriphResetCmd(RCC_APB0Periph_ANACTRL, ENABLE);
  31              		.loc 1 34 1 is_stmt 0 view .LVU2
  32 0000 10B5     		push	{r4, lr}
  33              	.LCFI0:
  34              		.cfi_def_cfa_offset 8
  35              		.cfi_offset 4, -8
  36              		.cfi_offset 14, -4
  37              		.loc 1 35 3 view .LVU3
  38 0002 0121     		movs	r1, #1
  36:Library/src/lcm32f06x_acmp.c ****   RCC_APB0PeriphResetCmd(RCC_APB0Periph_ANACTRL, DISABLE);
  37:Library/src/lcm32f06x_acmp.c **** }
  39              		.loc 1 37 1 view .LVU4
  40              		@ sp needed
  35:Library/src/lcm32f06x_acmp.c ****   RCC_APB0PeriphResetCmd(RCC_APB0Periph_ANACTRL, DISABLE);
  41              		.loc 1 35 3 view .LVU5
  42 0004 2020     		movs	r0, #32
  43 0006 FFF7FEFF 		bl	RCC_APB0PeriphResetCmd
  44              	.LVL0:
  36:Library/src/lcm32f06x_acmp.c ****   RCC_APB0PeriphResetCmd(RCC_APB0Periph_ANACTRL, DISABLE);
  45              		.loc 1 36 3 is_stmt 1 view .LVU6
  46 000a 0021     		movs	r1, #0
  47 000c 2020     		movs	r0, #32
  48 000e FFF7FEFF 		bl	RCC_APB0PeriphResetCmd
  49              	.LVL1:
  50              		.loc 1 37 1 is_stmt 0 view .LVU7
  51 0012 10BD     		pop	{r4, pc}
  52              		.cfi_endproc
  53              	.LFE45:
  55              		.section	.text.ACMP0_Init,"ax",%progbits
  56              		.align	1
  57              		.p2align 2,,3
  58              		.global	ACMP0_Init
  59              		.syntax unified
  60              		.code	16
  61              		.thumb_func
  63              	ACMP0_Init:
  64              	.LVL2:
  65              	.LFB46:
  38:Library/src/lcm32f06x_acmp.c **** 
  39:Library/src/lcm32f06x_acmp.c **** /**
  40:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_Init
  41:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Initializes the ACMP peripheral according to the specified 
  42:Library/src/lcm32f06x_acmp.c ****   *             parameters in the ACMP_InitStruct.
  43:Library/src/lcm32f06x_acmp.c ****   *         CN: 根据 ACMP_InitStruct 中指定的参数初始化 ACMP。
  44:Library/src/lcm32f06x_acmp.c ****   * @param  ACMP_InitStruct: 
  45:Library/src/lcm32f06x_acmp.c ****   *         EN: pointer to a ACMP_InitTypeDef structure that contains the 
  46:Library/src/lcm32f06x_acmp.c ****   *             configuration information for the specified ACMP peripheral.
  47:Library/src/lcm32f06x_acmp.c ****   *         CN: 指向 ACMP_InitTypeDef 结构的指针，该结构包含指定 ACMP 外设的配置信息。
  48:Library/src/lcm32f06x_acmp.c ****   * @retval None
  49:Library/src/lcm32f06x_acmp.c ****   */
ARM GAS  /tmp/ccQ8FEb0.s 			page 3


  50:Library/src/lcm32f06x_acmp.c **** void ACMP0_Init(ACMP_InitTypeDef *ACMP_InitStruct)
  51:Library/src/lcm32f06x_acmp.c **** {
  66              		.loc 1 51 1 is_stmt 1 view -0
  67              		.cfi_startproc
  68              		@ args = 0, pretend = 0, frame = 0
  69              		@ frame_needed = 0, uses_anonymous_args = 0
  52:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
  70              		.loc 1 52 3 view .LVU9
  53:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg1 = 0;
  71              		.loc 1 53 3 view .LVU10
  54:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg2 = 0;
  72              		.loc 1 54 3 view .LVU11
  55:Library/src/lcm32f06x_acmp.c ****   tmpreg = ACMP->ACMP0_CSR;
  73              		.loc 1 55 3 view .LVU12
  51:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
  74              		.loc 1 51 1 is_stmt 0 view .LVU13
  75 0000 F0B5     		push	{r4, r5, r6, r7, lr}
  76              	.LCFI1:
  77              		.cfi_def_cfa_offset 20
  78              		.cfi_offset 4, -20
  79              		.cfi_offset 5, -16
  80              		.cfi_offset 6, -12
  81              		.cfi_offset 7, -8
  82              		.cfi_offset 14, -4
  83 0002 D646     		mov	lr, r10
  84 0004 4F46     		mov	r7, r9
  85 0006 4646     		mov	r6, r8
  56:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
  57:Library/src/lcm32f06x_acmp.c **** 
  58:Library/src/lcm32f06x_acmp.c ****   tmpreg1 = ACMP->ACMP0_MUXCSR;
  59:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
  60:Library/src/lcm32f06x_acmp.c **** 
  61:Library/src/lcm32f06x_acmp.c ****   tmpreg2 = ACMP->ACMP0_EXTCFG;
  86              		.loc 1 61 11 view .LVU14
  87 0008 C422     		movs	r2, #196
  51:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
  88              		.loc 1 51 1 view .LVU15
  89 000a C0B5     		push	{r6, r7, lr}
  90              	.LCFI2:
  91              		.cfi_def_cfa_offset 32
  92              		.cfi_offset 8, -32
  93              		.cfi_offset 9, -28
  94              		.cfi_offset 10, -24
  58:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
  95              		.loc 1 58 11 view .LVU16
  96 000c C026     		movs	r6, #192
  55:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
  97              		.loc 1 55 10 view .LVU17
  98 000e 2E4C     		ldr	r4, .L4
  99              		.loc 1 61 11 view .LVU18
 100 0010 9246     		mov	r10, r2
  55:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
 101              		.loc 1 55 10 view .LVU19
 102 0012 236A     		ldr	r3, [r4, #32]
 103              	.LVL3:
  56:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
 104              		.loc 1 56 3 is_stmt 1 view .LVU20
ARM GAS  /tmp/ccQ8FEb0.s 			page 4


  58:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 105              		.loc 1 58 3 view .LVU21
  58:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 106              		.loc 1 58 11 is_stmt 0 view .LVU22
 107 0014 A759     		ldr	r7, [r4, r6]
 108              	.LVL4:
  59:Library/src/lcm32f06x_acmp.c **** 
 109              		.loc 1 59 3 is_stmt 1 view .LVU23
 110              		.loc 1 61 3 view .LVU24
 111              		.loc 1 61 11 is_stmt 0 view .LVU25
 112 0016 A158     		ldr	r1, [r4, r2]
 113              	.LVL5:
  62:Library/src/lcm32f06x_acmp.c ****   tmpreg2 &= ~(ANACTRL_ACMPX_EXTCFG_EXTDTG_Msk | ANACTRL_ACMPX_EXTCFG_EXTSE_Msk);
 114              		.loc 1 62 3 is_stmt 1 view .LVU26
 115              		.loc 1 62 11 is_stmt 0 view .LVU27
 116 0018 2C4A     		ldr	r2, .L4+4
 117 001a 056A     		ldr	r5, [r0, #32]
 118 001c 1140     		ands	r1, r2
 119              	.LVL6:
  63:Library/src/lcm32f06x_acmp.c **** 
  64:Library/src/lcm32f06x_acmp.c ****   tmpreg |= (((uint8_t)ACMP_InitStruct->ACMP_FILTER_SEL << 23) | (ACMP_InitStruct->ACMP_LPS << 15) 
 120              		.loc 1 64 3 is_stmt 1 view .LVU28
 121 001e C269     		ldr	r2, [r0, #28]
 122 0020 2A43     		orrs	r2, r5
  56:Library/src/lcm32f06x_acmp.c **** 
 123              		.loc 1 56 10 is_stmt 0 view .LVU29
 124 0022 2B4D     		ldr	r5, .L4+8
 125 0024 2B40     		ands	r3, r5
 126              	.LVL7:
  56:Library/src/lcm32f06x_acmp.c **** 
 127              		.loc 1 56 10 view .LVU30
 128 0026 1A43     		orrs	r2, r3
  65:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
  66:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_Is | (ACMP_InitStruct->ACMP_HYSEN << 2) | (ACMP_InitStruct->ACM
 129              		.loc 1 66 58 view .LVU31
 130 0028 2423     		movs	r3, #36
 131              	.LVL8:
 132              		.loc 1 66 71 view .LVU32
 133 002a C35C     		ldrb	r3, [r0, r3]
  65:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 134              		.loc 1 65 30 view .LVU33
 135 002c 457E     		ldrb	r5, [r0, #25]
 136              		.loc 1 66 71 view .LVU34
 137 002e 9B00     		lsls	r3, r3, #2
 138 0030 1A43     		orrs	r2, r3
 139              		.loc 1 66 95 view .LVU35
 140 0032 2523     		movs	r3, #37
 141              		.loc 1 66 107 view .LVU36
 142 0034 C35C     		ldrb	r3, [r0, r3]
  65:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 143              		.loc 1 65 40 view .LVU37
 144 0036 ED02     		lsls	r5, r5, #11
 145              		.loc 1 66 107 view .LVU38
 146 0038 5B00     		lsls	r3, r3, #1
 147 003a 1A43     		orrs	r2, r3
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 148              		.loc 1 64 82 view .LVU39
ARM GAS  /tmp/ccQ8FEb0.s 			page 5


 149 003c 037E     		ldrb	r3, [r0, #24]
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 150              		.loc 1 64 93 view .LVU40
 151 003e DB03     		lsls	r3, r3, #15
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 152              		.loc 1 64 100 view .LVU41
 153 0040 2B43     		orrs	r3, r5
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 154              		.loc 1 64 57 view .LVU42
 155 0042 4569     		ldr	r5, [r0, #20]
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 156              		.loc 1 64 100 view .LVU43
 157 0044 9946     		mov	r9, r3
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 158              		.loc 1 64 57 view .LVU44
 159 0046 ED05     		lsls	r5, r5, #23
 160 0048 AC46     		mov	ip, r5
 161 004a FF25     		movs	r5, #255
 162 004c ED05     		lsls	r5, r5, #23
 163 004e A846     		mov	r8, r5
 164 0050 6546     		mov	r5, ip
 165 0052 4346     		mov	r3, r8
 166 0054 1D40     		ands	r5, r3
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 167              		.loc 1 64 100 view .LVU45
 168 0056 2B00     		movs	r3, r5
 169 0058 4D46     		mov	r5, r9
 170 005a 1D43     		orrs	r5, r3
 171 005c 2B00     		movs	r3, r5
  67:Library/src/lcm32f06x_acmp.c **** 
  68:Library/src/lcm32f06x_acmp.c ****   tmpreg1 |= (ACMP_InitStruct->ACMP_TrigMode | ACMP_InitStruct->ACMP_WorkMode | \
 172              		.loc 1 68 46 view .LVU46
 173 005e 4568     		ldr	r5, [r0, #4]
  64:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 174              		.loc 1 64 10 view .LVU47
 175 0060 1343     		orrs	r3, r2
 176              	.LVL9:
 177              		.loc 1 68 3 is_stmt 1 view .LVU48
 178              		.loc 1 68 46 is_stmt 0 view .LVU49
 179 0062 0268     		ldr	r2, [r0]
 180 0064 2A43     		orrs	r2, r5
  59:Library/src/lcm32f06x_acmp.c **** 
 181              		.loc 1 59 11 view .LVU50
 182 0066 1B4D     		ldr	r5, .L4+12
 183 0068 2F40     		ands	r7, r5
 184              	.LVL10:
  69:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_P_Select| ACMP_InitStruct->ACMP_N_Select | \
  70:Library/src/lcm32f06x_acmp.c ****               ((uint8_t)ACMP_InitStruct->ACMP_CNT_CFG << 1));
 185              		.loc 1 70 55 view .LVU51
 186 006a FF25     		movs	r5, #255
 187 006c 3A43     		orrs	r2, r7
 188 006e 8768     		ldr	r7, [r0, #8]
 189              	.LVL11:
 190              		.loc 1 70 55 view .LVU52
 191 0070 6D00     		lsls	r5, r5, #1
 192 0072 3A43     		orrs	r2, r7
 193 0074 C768     		ldr	r7, [r0, #12]
ARM GAS  /tmp/ccQ8FEb0.s 			page 6


 194 0076 3A43     		orrs	r2, r7
 195 0078 0769     		ldr	r7, [r0, #16]
 196 007a 7F00     		lsls	r7, r7, #1
 197 007c 2F40     		ands	r7, r5
  68:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_P_Select| ACMP_InitStruct->ACMP_N_Select | \
 198              		.loc 1 68 11 view .LVU53
 199 007e 3A43     		orrs	r2, r7
 200              	.LVL12:
  71:Library/src/lcm32f06x_acmp.c **** 
  72:Library/src/lcm32f06x_acmp.c ****   tmpreg2 |= ((ACMP_InitStruct->EXTSELECT) | ACMP_InitStruct->TRIG_DELAY_TIME);
 201              		.loc 1 72 3 is_stmt 1 view .LVU54
 202              		.loc 1 72 44 is_stmt 0 view .LVU55
 203 0080 C56A     		ldr	r5, [r0, #44]
 204 0082 876A     		ldr	r7, [r0, #40]
 205 0084 2F43     		orrs	r7, r5
 206              		.loc 1 72 11 view .LVU56
 207 0086 0F43     		orrs	r7, r1
 208              	.LVL13:
  73:Library/src/lcm32f06x_acmp.c **** 
  74:Library/src/lcm32f06x_acmp.c ****   sysctrl_access();
 209              		.loc 1 74 3 is_stmt 1 view .LVU57
 210              	.LBB54:
 211              	.LBI54:
 212              		.file 2 "Core/cmsis_gcc.h"
   1:Core/cmsis_gcc.h **** /**************************************************************************//**
   2:Core/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Core/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Core/cmsis_gcc.h ****  * @version  V5.4.1
   5:Core/cmsis_gcc.h ****  * @date     27. May 2021
   6:Core/cmsis_gcc.h ****  ******************************************************************************/
   7:Core/cmsis_gcc.h **** /*
   8:Core/cmsis_gcc.h ****  * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
   9:Core/cmsis_gcc.h ****  *
  10:Core/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Core/cmsis_gcc.h ****  *
  12:Core/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Core/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Core/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Core/cmsis_gcc.h ****  *
  16:Core/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Core/cmsis_gcc.h ****  *
  18:Core/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Core/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Core/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Core/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Core/cmsis_gcc.h ****  * limitations under the License.
  23:Core/cmsis_gcc.h ****  */
  24:Core/cmsis_gcc.h **** 
  25:Core/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Core/cmsis_gcc.h **** #define __CMSIS_GCC_H
  27:Core/cmsis_gcc.h **** 
  28:Core/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Core/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Core/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccQ8FEb0.s 			page 7


  34:Core/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Core/cmsis_gcc.h **** #ifndef __has_builtin
  36:Core/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Core/cmsis_gcc.h **** #endif
  38:Core/cmsis_gcc.h **** 
  39:Core/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Core/cmsis_gcc.h **** #ifndef   __ASM
  41:Core/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Core/cmsis_gcc.h **** #endif
  43:Core/cmsis_gcc.h **** #ifndef   __INLINE
  44:Core/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Core/cmsis_gcc.h **** #endif
  46:Core/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Core/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Core/cmsis_gcc.h **** #endif
  49:Core/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE
  50:Core/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Core/cmsis_gcc.h **** #endif
  52:Core/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Core/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Core/cmsis_gcc.h **** #endif
  55:Core/cmsis_gcc.h **** #ifndef   __USED
  56:Core/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Core/cmsis_gcc.h **** #endif
  58:Core/cmsis_gcc.h **** #ifndef   __WEAK
  59:Core/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Core/cmsis_gcc.h **** #endif
  61:Core/cmsis_gcc.h **** #ifndef   __PACKED
  62:Core/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Core/cmsis_gcc.h **** #endif
  64:Core/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Core/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Core/cmsis_gcc.h **** #endif
  67:Core/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Core/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Core/cmsis_gcc.h **** #endif
  70:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Core/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Core/cmsis_gcc.h **** #endif
  78:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  84:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Core/cmsis_gcc.h **** #endif
  86:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
ARM GAS  /tmp/ccQ8FEb0.s 			page 8


  91:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Core/cmsis_gcc.h **** #endif
  94:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Core/cmsis_gcc.h **** #endif
 102:Core/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Core/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Core/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Core/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Core/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Core/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Core/cmsis_gcc.h **** #endif
 110:Core/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Core/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Core/cmsis_gcc.h **** #endif
 113:Core/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Core/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Core/cmsis_gcc.h **** #endif
 116:Core/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Core/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Core/cmsis_gcc.h **** #endif
 119:Core/cmsis_gcc.h **** 
 120:Core/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Core/cmsis_gcc.h **** 
 122:Core/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Core/cmsis_gcc.h **** 
 124:Core/cmsis_gcc.h **** /**
 125:Core/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Core/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Core/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Core/cmsis_gcc.h ****            in the used linker script.
 129:Core/cmsis_gcc.h **** 
 130:Core/cmsis_gcc.h ****  */
 131:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Core/cmsis_gcc.h **** {
 133:Core/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Core/cmsis_gcc.h **** 
 135:Core/cmsis_gcc.h ****   typedef struct {
 136:Core/cmsis_gcc.h ****     uint32_t const* src;
 137:Core/cmsis_gcc.h ****     uint32_t* dest;
 138:Core/cmsis_gcc.h ****     uint32_t  wlen;
 139:Core/cmsis_gcc.h ****   } __copy_table_t;
 140:Core/cmsis_gcc.h **** 
 141:Core/cmsis_gcc.h ****   typedef struct {
 142:Core/cmsis_gcc.h ****     uint32_t* dest;
 143:Core/cmsis_gcc.h ****     uint32_t  wlen;
 144:Core/cmsis_gcc.h ****   } __zero_table_t;
 145:Core/cmsis_gcc.h **** 
 146:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Core/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
ARM GAS  /tmp/ccQ8FEb0.s 			page 9


 148:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Core/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Core/cmsis_gcc.h **** 
 151:Core/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Core/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Core/cmsis_gcc.h ****     }
 155:Core/cmsis_gcc.h ****   }
 156:Core/cmsis_gcc.h **** 
 157:Core/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Core/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Core/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Core/cmsis_gcc.h ****     }
 161:Core/cmsis_gcc.h ****   }
 162:Core/cmsis_gcc.h **** 
 163:Core/cmsis_gcc.h ****   _start();
 164:Core/cmsis_gcc.h **** }
 165:Core/cmsis_gcc.h **** 
 166:Core/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Core/cmsis_gcc.h **** #endif
 168:Core/cmsis_gcc.h **** 
 169:Core/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Core/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Core/cmsis_gcc.h **** #endif
 172:Core/cmsis_gcc.h **** 
 173:Core/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Core/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Core/cmsis_gcc.h **** #endif
 176:Core/cmsis_gcc.h **** 
 177:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Core/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Core/cmsis_gcc.h **** #endif
 180:Core/cmsis_gcc.h **** 
 181:Core/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Core/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
 183:Core/cmsis_gcc.h **** #endif
 184:Core/cmsis_gcc.h **** 
 185:Core/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 186:Core/cmsis_gcc.h **** #ifndef __STACK_SEAL
 187:Core/cmsis_gcc.h **** #define __STACK_SEAL              __StackSeal
 188:Core/cmsis_gcc.h **** #endif
 189:Core/cmsis_gcc.h **** 
 190:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE
 191:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE      8U
 192:Core/cmsis_gcc.h **** #endif
 193:Core/cmsis_gcc.h **** 
 194:Core/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE
 195:Core/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE     0xFEF5EDA5FEF5EDA5ULL
 196:Core/cmsis_gcc.h **** #endif
 197:Core/cmsis_gcc.h **** 
 198:Core/cmsis_gcc.h **** 
 199:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
 200:Core/cmsis_gcc.h ****   *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
 201:Core/cmsis_gcc.h **** }
 202:Core/cmsis_gcc.h **** #endif
 203:Core/cmsis_gcc.h **** 
 204:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccQ8FEb0.s 			page 10


 205:Core/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 206:Core/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
 207:Core/cmsis_gcc.h ****   Access to dedicated instructions
 208:Core/cmsis_gcc.h ****   @{
 209:Core/cmsis_gcc.h **** */
 210:Core/cmsis_gcc.h **** 
 211:Core/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 212:Core/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 213:Core/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 214:Core/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 215:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 216:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 217:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 218:Core/cmsis_gcc.h **** #else
 219:Core/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 220:Core/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 221:Core/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 222:Core/cmsis_gcc.h **** #endif
 223:Core/cmsis_gcc.h **** 
 224:Core/cmsis_gcc.h **** /**
 225:Core/cmsis_gcc.h ****   \brief   No Operation
 226:Core/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 227:Core/cmsis_gcc.h ****  */
 228:Core/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 229:Core/cmsis_gcc.h **** 
 230:Core/cmsis_gcc.h **** /**
 231:Core/cmsis_gcc.h ****   \brief   Wait For Interrupt
 232:Core/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 233:Core/cmsis_gcc.h ****  */
 234:Core/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi":::"memory")
 235:Core/cmsis_gcc.h **** 
 236:Core/cmsis_gcc.h **** 
 237:Core/cmsis_gcc.h **** /**
 238:Core/cmsis_gcc.h ****   \brief   Wait For Event
 239:Core/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 240:Core/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 241:Core/cmsis_gcc.h ****  */
 242:Core/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe":::"memory")
 243:Core/cmsis_gcc.h **** 
 244:Core/cmsis_gcc.h **** 
 245:Core/cmsis_gcc.h **** /**
 246:Core/cmsis_gcc.h ****   \brief   Send Event
 247:Core/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 248:Core/cmsis_gcc.h ****  */
 249:Core/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 250:Core/cmsis_gcc.h **** 
 251:Core/cmsis_gcc.h **** 
 252:Core/cmsis_gcc.h **** /**
 253:Core/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 254:Core/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 255:Core/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 256:Core/cmsis_gcc.h ****            after the instruction has been completed.
 257:Core/cmsis_gcc.h ****  */
 258:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 213              		.loc 2 258 27 view .LVU58
 214              	.LBB55:
 259:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccQ8FEb0.s 			page 11


 260:Core/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 215              		.loc 2 260 3 view .LVU59
 216              		.syntax divided
 217              	@ 260 "Core/cmsis_gcc.h" 1
 218 0088 BFF36F8F 		isb 0xF
 219              	@ 0 "" 2
 220              		.thumb
 221              		.syntax unified
 222              	.LBE55:
 223              	.LBE54:
 224              		.loc 1 74 3 discriminator 1 view .LVU60
 225              	.LBB56:
 226              	.LBI56:
 261:Core/cmsis_gcc.h **** }
 262:Core/cmsis_gcc.h **** 
 263:Core/cmsis_gcc.h **** 
 264:Core/cmsis_gcc.h **** /**
 265:Core/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 266:Core/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 267:Core/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 268:Core/cmsis_gcc.h ****  */
 269:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 270:Core/cmsis_gcc.h **** {
 271:Core/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 272:Core/cmsis_gcc.h **** }
 273:Core/cmsis_gcc.h **** 
 274:Core/cmsis_gcc.h **** 
 275:Core/cmsis_gcc.h **** /**
 276:Core/cmsis_gcc.h ****   \brief   Data Memory Barrier
 277:Core/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 278:Core/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 279:Core/cmsis_gcc.h ****  */
 280:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 281:Core/cmsis_gcc.h **** {
 282:Core/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 283:Core/cmsis_gcc.h **** }
 284:Core/cmsis_gcc.h **** 
 285:Core/cmsis_gcc.h **** 
 286:Core/cmsis_gcc.h **** /**
 287:Core/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 288:Core/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 289:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 290:Core/cmsis_gcc.h ****   \return               Reversed value
 291:Core/cmsis_gcc.h ****  */
 292:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 293:Core/cmsis_gcc.h **** {
 294:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 295:Core/cmsis_gcc.h ****   return __builtin_bswap32(value);
 296:Core/cmsis_gcc.h **** #else
 297:Core/cmsis_gcc.h ****   uint32_t result;
 298:Core/cmsis_gcc.h **** 
 299:Core/cmsis_gcc.h ****   __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 300:Core/cmsis_gcc.h ****   return result;
 301:Core/cmsis_gcc.h **** #endif
 302:Core/cmsis_gcc.h **** }
 303:Core/cmsis_gcc.h **** 
 304:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccQ8FEb0.s 			page 12


 305:Core/cmsis_gcc.h **** /**
 306:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 307:Core/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 308:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 309:Core/cmsis_gcc.h ****   \return               Reversed value
 310:Core/cmsis_gcc.h ****  */
 311:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 312:Core/cmsis_gcc.h **** {
 313:Core/cmsis_gcc.h ****   uint32_t result;
 314:Core/cmsis_gcc.h **** 
 315:Core/cmsis_gcc.h ****   __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 316:Core/cmsis_gcc.h ****   return result;
 317:Core/cmsis_gcc.h **** }
 318:Core/cmsis_gcc.h **** 
 319:Core/cmsis_gcc.h **** 
 320:Core/cmsis_gcc.h **** /**
 321:Core/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 322:Core/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 323:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 324:Core/cmsis_gcc.h ****   \return               Reversed value
 325:Core/cmsis_gcc.h ****  */
 326:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
 327:Core/cmsis_gcc.h **** {
 328:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 329:Core/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
 330:Core/cmsis_gcc.h **** #else
 331:Core/cmsis_gcc.h ****   int16_t result;
 332:Core/cmsis_gcc.h **** 
 333:Core/cmsis_gcc.h ****   __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 334:Core/cmsis_gcc.h ****   return result;
 335:Core/cmsis_gcc.h **** #endif
 336:Core/cmsis_gcc.h **** }
 337:Core/cmsis_gcc.h **** 
 338:Core/cmsis_gcc.h **** 
 339:Core/cmsis_gcc.h **** /**
 340:Core/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
 341:Core/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
 342:Core/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
 343:Core/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
 344:Core/cmsis_gcc.h ****   \return               Rotated value
 345:Core/cmsis_gcc.h ****  */
 346:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 347:Core/cmsis_gcc.h **** {
 348:Core/cmsis_gcc.h ****   op2 %= 32U;
 349:Core/cmsis_gcc.h ****   if (op2 == 0U)
 350:Core/cmsis_gcc.h ****   {
 351:Core/cmsis_gcc.h ****     return op1;
 352:Core/cmsis_gcc.h ****   }
 353:Core/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 354:Core/cmsis_gcc.h **** }
 355:Core/cmsis_gcc.h **** 
 356:Core/cmsis_gcc.h **** 
 357:Core/cmsis_gcc.h **** /**
 358:Core/cmsis_gcc.h ****   \brief   Breakpoint
 359:Core/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 360:Core/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
 361:Core/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
ARM GAS  /tmp/ccQ8FEb0.s 			page 13


 362:Core/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
 363:Core/cmsis_gcc.h ****  */
 364:Core/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
 365:Core/cmsis_gcc.h **** 
 366:Core/cmsis_gcc.h **** 
 367:Core/cmsis_gcc.h **** /**
 368:Core/cmsis_gcc.h ****   \brief   Reverse bit order of value
 369:Core/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
 370:Core/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 371:Core/cmsis_gcc.h ****   \return               Reversed value
 372:Core/cmsis_gcc.h ****  */
 373:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 374:Core/cmsis_gcc.h **** {
 375:Core/cmsis_gcc.h ****   uint32_t result;
 376:Core/cmsis_gcc.h **** 
 377:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 378:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 379:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 380:Core/cmsis_gcc.h ****    __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
 381:Core/cmsis_gcc.h **** #else
 382:Core/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
 383:Core/cmsis_gcc.h **** 
 384:Core/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
 385:Core/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
 386:Core/cmsis_gcc.h ****   {
 387:Core/cmsis_gcc.h ****     result <<= 1U;
 388:Core/cmsis_gcc.h ****     result |= value & 1U;
 389:Core/cmsis_gcc.h ****     s--;
 390:Core/cmsis_gcc.h ****   }
 391:Core/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
 392:Core/cmsis_gcc.h **** #endif
 393:Core/cmsis_gcc.h ****   return result;
 394:Core/cmsis_gcc.h **** }
 395:Core/cmsis_gcc.h **** 
 396:Core/cmsis_gcc.h **** 
 397:Core/cmsis_gcc.h **** /**
 398:Core/cmsis_gcc.h ****   \brief   Count leading zeros
 399:Core/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
 400:Core/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
 401:Core/cmsis_gcc.h ****   \return             number of leading zeros in value
 402:Core/cmsis_gcc.h ****  */
 403:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 404:Core/cmsis_gcc.h **** {
 405:Core/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
 406:Core/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
 407:Core/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
 408:Core/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
 409:Core/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
 410:Core/cmsis_gcc.h ****      is non-zero".
 411:Core/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
 412:Core/cmsis_gcc.h ****      single CLZ instruction.
 413:Core/cmsis_gcc.h ****    */
 414:Core/cmsis_gcc.h ****   if (value == 0U)
 415:Core/cmsis_gcc.h ****   {
 416:Core/cmsis_gcc.h ****     return 32U;
 417:Core/cmsis_gcc.h ****   }
 418:Core/cmsis_gcc.h ****   return __builtin_clz(value);
ARM GAS  /tmp/ccQ8FEb0.s 			page 14


 419:Core/cmsis_gcc.h **** }
 420:Core/cmsis_gcc.h **** 
 421:Core/cmsis_gcc.h **** 
 422:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 423:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 424:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 425:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 426:Core/cmsis_gcc.h **** /**
 427:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (8 bit)
 428:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 8 bit value.
 429:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 430:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 431:Core/cmsis_gcc.h ****  */
 432:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
 433:Core/cmsis_gcc.h **** {
 434:Core/cmsis_gcc.h ****     uint32_t result;
 435:Core/cmsis_gcc.h **** 
 436:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 437:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
 438:Core/cmsis_gcc.h **** #else
 439:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 440:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 441:Core/cmsis_gcc.h ****     */
 442:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 443:Core/cmsis_gcc.h **** #endif
 444:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 445:Core/cmsis_gcc.h **** }
 446:Core/cmsis_gcc.h **** 
 447:Core/cmsis_gcc.h **** 
 448:Core/cmsis_gcc.h **** /**
 449:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (16 bit)
 450:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 16 bit values.
 451:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 452:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 453:Core/cmsis_gcc.h ****  */
 454:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
 455:Core/cmsis_gcc.h **** {
 456:Core/cmsis_gcc.h ****     uint32_t result;
 457:Core/cmsis_gcc.h **** 
 458:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 459:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
 460:Core/cmsis_gcc.h **** #else
 461:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 462:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 463:Core/cmsis_gcc.h ****     */
 464:Core/cmsis_gcc.h ****    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
 465:Core/cmsis_gcc.h **** #endif
 466:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 467:Core/cmsis_gcc.h **** }
 468:Core/cmsis_gcc.h **** 
 469:Core/cmsis_gcc.h **** 
 470:Core/cmsis_gcc.h **** /**
 471:Core/cmsis_gcc.h ****   \brief   LDR Exclusive (32 bit)
 472:Core/cmsis_gcc.h ****   \details Executes a exclusive LDR instruction for 32 bit values.
 473:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 474:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 475:Core/cmsis_gcc.h ****  */
ARM GAS  /tmp/ccQ8FEb0.s 			page 15


 476:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
 477:Core/cmsis_gcc.h **** {
 478:Core/cmsis_gcc.h ****     uint32_t result;
 479:Core/cmsis_gcc.h **** 
 480:Core/cmsis_gcc.h ****    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 481:Core/cmsis_gcc.h ****    return(result);
 482:Core/cmsis_gcc.h **** }
 483:Core/cmsis_gcc.h **** 
 484:Core/cmsis_gcc.h **** 
 485:Core/cmsis_gcc.h **** /**
 486:Core/cmsis_gcc.h ****   \brief   STR Exclusive (8 bit)
 487:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 8 bit values.
 488:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 489:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 490:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 491:Core/cmsis_gcc.h ****   \return          1  Function failed
 492:Core/cmsis_gcc.h ****  */
 493:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
 494:Core/cmsis_gcc.h **** {
 495:Core/cmsis_gcc.h ****    uint32_t result;
 496:Core/cmsis_gcc.h **** 
 497:Core/cmsis_gcc.h ****    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 498:Core/cmsis_gcc.h ****    return(result);
 499:Core/cmsis_gcc.h **** }
 500:Core/cmsis_gcc.h **** 
 501:Core/cmsis_gcc.h **** 
 502:Core/cmsis_gcc.h **** /**
 503:Core/cmsis_gcc.h ****   \brief   STR Exclusive (16 bit)
 504:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 16 bit values.
 505:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 506:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 507:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 508:Core/cmsis_gcc.h ****   \return          1  Function failed
 509:Core/cmsis_gcc.h ****  */
 510:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
 511:Core/cmsis_gcc.h **** {
 512:Core/cmsis_gcc.h ****    uint32_t result;
 513:Core/cmsis_gcc.h **** 
 514:Core/cmsis_gcc.h ****    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
 515:Core/cmsis_gcc.h ****    return(result);
 516:Core/cmsis_gcc.h **** }
 517:Core/cmsis_gcc.h **** 
 518:Core/cmsis_gcc.h **** 
 519:Core/cmsis_gcc.h **** /**
 520:Core/cmsis_gcc.h ****   \brief   STR Exclusive (32 bit)
 521:Core/cmsis_gcc.h ****   \details Executes a exclusive STR instruction for 32 bit values.
 522:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 523:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 524:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 525:Core/cmsis_gcc.h ****   \return          1  Function failed
 526:Core/cmsis_gcc.h ****  */
 527:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
 528:Core/cmsis_gcc.h **** {
 529:Core/cmsis_gcc.h ****    uint32_t result;
 530:Core/cmsis_gcc.h **** 
 531:Core/cmsis_gcc.h ****    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 532:Core/cmsis_gcc.h ****    return(result);
ARM GAS  /tmp/ccQ8FEb0.s 			page 16


 533:Core/cmsis_gcc.h **** }
 534:Core/cmsis_gcc.h **** 
 535:Core/cmsis_gcc.h **** 
 536:Core/cmsis_gcc.h **** /**
 537:Core/cmsis_gcc.h ****   \brief   Remove the exclusive lock
 538:Core/cmsis_gcc.h ****   \details Removes the exclusive lock which is created by LDREX.
 539:Core/cmsis_gcc.h ****  */
 540:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void)
 541:Core/cmsis_gcc.h **** {
 542:Core/cmsis_gcc.h ****   __ASM volatile ("clrex" ::: "memory");
 543:Core/cmsis_gcc.h **** }
 544:Core/cmsis_gcc.h **** 
 545:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 546:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 547:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 548:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 549:Core/cmsis_gcc.h **** 
 550:Core/cmsis_gcc.h **** 
 551:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 552:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 553:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 554:Core/cmsis_gcc.h **** /**
 555:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 556:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 557:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 558:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (1..32)
 559:Core/cmsis_gcc.h ****   \return             Saturated value
 560:Core/cmsis_gcc.h ****  */
 561:Core/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \
 562:Core/cmsis_gcc.h **** __extension__ \
 563:Core/cmsis_gcc.h **** ({                          \
 564:Core/cmsis_gcc.h ****   int32_t __RES, __ARG1 = (ARG1); \
 565:Core/cmsis_gcc.h ****   __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 566:Core/cmsis_gcc.h ****   __RES; \
 567:Core/cmsis_gcc.h ****  })
 568:Core/cmsis_gcc.h **** 
 569:Core/cmsis_gcc.h **** 
 570:Core/cmsis_gcc.h **** /**
 571:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 572:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 573:Core/cmsis_gcc.h ****   \param [in]  ARG1  Value to be saturated
 574:Core/cmsis_gcc.h ****   \param [in]  ARG2  Bit position to saturate to (0..31)
 575:Core/cmsis_gcc.h ****   \return             Saturated value
 576:Core/cmsis_gcc.h ****  */
 577:Core/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \
 578:Core/cmsis_gcc.h **** __extension__ \
 579:Core/cmsis_gcc.h **** ({                          \
 580:Core/cmsis_gcc.h ****   uint32_t __RES, __ARG1 = (ARG1); \
 581:Core/cmsis_gcc.h ****   __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
 582:Core/cmsis_gcc.h ****   __RES; \
 583:Core/cmsis_gcc.h ****  })
 584:Core/cmsis_gcc.h **** 
 585:Core/cmsis_gcc.h **** 
 586:Core/cmsis_gcc.h **** /**
 587:Core/cmsis_gcc.h ****   \brief   Rotate Right with Extend (32 bit)
 588:Core/cmsis_gcc.h ****   \details Moves each bit of a bitstring right by one bit.
 589:Core/cmsis_gcc.h ****            The carry input is shifted in at the left end of the bitstring.
ARM GAS  /tmp/ccQ8FEb0.s 			page 17


 590:Core/cmsis_gcc.h ****   \param [in]    value  Value to rotate
 591:Core/cmsis_gcc.h ****   \return               Rotated value
 592:Core/cmsis_gcc.h ****  */
 593:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
 594:Core/cmsis_gcc.h **** {
 595:Core/cmsis_gcc.h ****   uint32_t result;
 596:Core/cmsis_gcc.h **** 
 597:Core/cmsis_gcc.h ****   __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 598:Core/cmsis_gcc.h ****   return(result);
 599:Core/cmsis_gcc.h **** }
 600:Core/cmsis_gcc.h **** 
 601:Core/cmsis_gcc.h **** 
 602:Core/cmsis_gcc.h **** /**
 603:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (8 bit)
 604:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 8 bit value.
 605:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 606:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 607:Core/cmsis_gcc.h ****  */
 608:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
 609:Core/cmsis_gcc.h **** {
 610:Core/cmsis_gcc.h ****     uint32_t result;
 611:Core/cmsis_gcc.h **** 
 612:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 613:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
 614:Core/cmsis_gcc.h **** #else
 615:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 616:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 617:Core/cmsis_gcc.h ****     */
 618:Core/cmsis_gcc.h ****    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 619:Core/cmsis_gcc.h **** #endif
 620:Core/cmsis_gcc.h ****    return ((uint8_t) result);    /* Add explicit type cast here */
 621:Core/cmsis_gcc.h **** }
 622:Core/cmsis_gcc.h **** 
 623:Core/cmsis_gcc.h **** 
 624:Core/cmsis_gcc.h **** /**
 625:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (16 bit)
 626:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 16 bit values.
 627:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 628:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 629:Core/cmsis_gcc.h ****  */
 630:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
 631:Core/cmsis_gcc.h **** {
 632:Core/cmsis_gcc.h ****     uint32_t result;
 633:Core/cmsis_gcc.h **** 
 634:Core/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
 635:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
 636:Core/cmsis_gcc.h **** #else
 637:Core/cmsis_gcc.h ****     /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
 638:Core/cmsis_gcc.h ****        accepted by assembler. So has to use following less efficient pattern.
 639:Core/cmsis_gcc.h ****     */
 640:Core/cmsis_gcc.h ****    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
 641:Core/cmsis_gcc.h **** #endif
 642:Core/cmsis_gcc.h ****    return ((uint16_t) result);    /* Add explicit type cast here */
 643:Core/cmsis_gcc.h **** }
 644:Core/cmsis_gcc.h **** 
 645:Core/cmsis_gcc.h **** 
 646:Core/cmsis_gcc.h **** /**
ARM GAS  /tmp/ccQ8FEb0.s 			page 18


 647:Core/cmsis_gcc.h ****   \brief   LDRT Unprivileged (32 bit)
 648:Core/cmsis_gcc.h ****   \details Executes a Unprivileged LDRT instruction for 32 bit values.
 649:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 650:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 651:Core/cmsis_gcc.h ****  */
 652:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
 653:Core/cmsis_gcc.h **** {
 654:Core/cmsis_gcc.h ****     uint32_t result;
 655:Core/cmsis_gcc.h **** 
 656:Core/cmsis_gcc.h ****    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
 657:Core/cmsis_gcc.h ****    return(result);
 658:Core/cmsis_gcc.h **** }
 659:Core/cmsis_gcc.h **** 
 660:Core/cmsis_gcc.h **** 
 661:Core/cmsis_gcc.h **** /**
 662:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (8 bit)
 663:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 8 bit values.
 664:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 665:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 666:Core/cmsis_gcc.h ****  */
 667:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
 668:Core/cmsis_gcc.h **** {
 669:Core/cmsis_gcc.h ****    __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 670:Core/cmsis_gcc.h **** }
 671:Core/cmsis_gcc.h **** 
 672:Core/cmsis_gcc.h **** 
 673:Core/cmsis_gcc.h **** /**
 674:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (16 bit)
 675:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 16 bit values.
 676:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 677:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 678:Core/cmsis_gcc.h ****  */
 679:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
 680:Core/cmsis_gcc.h **** {
 681:Core/cmsis_gcc.h ****    __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
 682:Core/cmsis_gcc.h **** }
 683:Core/cmsis_gcc.h **** 
 684:Core/cmsis_gcc.h **** 
 685:Core/cmsis_gcc.h **** /**
 686:Core/cmsis_gcc.h ****   \brief   STRT Unprivileged (32 bit)
 687:Core/cmsis_gcc.h ****   \details Executes a Unprivileged STRT instruction for 32 bit values.
 688:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 689:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 690:Core/cmsis_gcc.h ****  */
 691:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
 692:Core/cmsis_gcc.h **** {
 693:Core/cmsis_gcc.h ****    __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
 694:Core/cmsis_gcc.h **** }
 695:Core/cmsis_gcc.h **** 
 696:Core/cmsis_gcc.h **** #else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 697:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 698:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 699:Core/cmsis_gcc.h **** 
 700:Core/cmsis_gcc.h **** /**
 701:Core/cmsis_gcc.h ****   \brief   Signed Saturate
 702:Core/cmsis_gcc.h ****   \details Saturates a signed value.
 703:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
ARM GAS  /tmp/ccQ8FEb0.s 			page 19


 704:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (1..32)
 705:Core/cmsis_gcc.h ****   \return             Saturated value
 706:Core/cmsis_gcc.h ****  */
 707:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 708:Core/cmsis_gcc.h **** {
 709:Core/cmsis_gcc.h ****   if ((sat >= 1U) && (sat <= 32U))
 710:Core/cmsis_gcc.h ****   {
 711:Core/cmsis_gcc.h ****     const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
 712:Core/cmsis_gcc.h ****     const int32_t min = -1 - max ;
 713:Core/cmsis_gcc.h ****     if (val > max)
 714:Core/cmsis_gcc.h ****     {
 715:Core/cmsis_gcc.h ****       return max;
 716:Core/cmsis_gcc.h ****     }
 717:Core/cmsis_gcc.h ****     else if (val < min)
 718:Core/cmsis_gcc.h ****     {
 719:Core/cmsis_gcc.h ****       return min;
 720:Core/cmsis_gcc.h ****     }
 721:Core/cmsis_gcc.h ****   }
 722:Core/cmsis_gcc.h ****   return val;
 723:Core/cmsis_gcc.h **** }
 724:Core/cmsis_gcc.h **** 
 725:Core/cmsis_gcc.h **** /**
 726:Core/cmsis_gcc.h ****   \brief   Unsigned Saturate
 727:Core/cmsis_gcc.h ****   \details Saturates an unsigned value.
 728:Core/cmsis_gcc.h ****   \param [in]  value  Value to be saturated
 729:Core/cmsis_gcc.h ****   \param [in]    sat  Bit position to saturate to (0..31)
 730:Core/cmsis_gcc.h ****   \return             Saturated value
 731:Core/cmsis_gcc.h ****  */
 732:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 733:Core/cmsis_gcc.h **** {
 734:Core/cmsis_gcc.h ****   if (sat <= 31U)
 735:Core/cmsis_gcc.h ****   {
 736:Core/cmsis_gcc.h ****     const uint32_t max = ((1U << sat) - 1U);
 737:Core/cmsis_gcc.h ****     if (val > (int32_t)max)
 738:Core/cmsis_gcc.h ****     {
 739:Core/cmsis_gcc.h ****       return max;
 740:Core/cmsis_gcc.h ****     }
 741:Core/cmsis_gcc.h ****     else if (val < 0)
 742:Core/cmsis_gcc.h ****     {
 743:Core/cmsis_gcc.h ****       return 0U;
 744:Core/cmsis_gcc.h ****     }
 745:Core/cmsis_gcc.h ****   }
 746:Core/cmsis_gcc.h ****   return (uint32_t)val;
 747:Core/cmsis_gcc.h **** }
 748:Core/cmsis_gcc.h **** 
 749:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 750:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 751:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 752:Core/cmsis_gcc.h **** 
 753:Core/cmsis_gcc.h **** 
 754:Core/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 755:Core/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 756:Core/cmsis_gcc.h **** /**
 757:Core/cmsis_gcc.h ****   \brief   Load-Acquire (8 bit)
 758:Core/cmsis_gcc.h ****   \details Executes a LDAB instruction for 8 bit value.
 759:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 760:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
ARM GAS  /tmp/ccQ8FEb0.s 			page 20


 761:Core/cmsis_gcc.h ****  */
 762:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
 763:Core/cmsis_gcc.h **** {
 764:Core/cmsis_gcc.h ****     uint32_t result;
 765:Core/cmsis_gcc.h **** 
 766:Core/cmsis_gcc.h ****    __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 767:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 768:Core/cmsis_gcc.h **** }
 769:Core/cmsis_gcc.h **** 
 770:Core/cmsis_gcc.h **** 
 771:Core/cmsis_gcc.h **** /**
 772:Core/cmsis_gcc.h ****   \brief   Load-Acquire (16 bit)
 773:Core/cmsis_gcc.h ****   \details Executes a LDAH instruction for 16 bit values.
 774:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 775:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 776:Core/cmsis_gcc.h ****  */
 777:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
 778:Core/cmsis_gcc.h **** {
 779:Core/cmsis_gcc.h ****     uint32_t result;
 780:Core/cmsis_gcc.h **** 
 781:Core/cmsis_gcc.h ****    __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 782:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 783:Core/cmsis_gcc.h **** }
 784:Core/cmsis_gcc.h **** 
 785:Core/cmsis_gcc.h **** 
 786:Core/cmsis_gcc.h **** /**
 787:Core/cmsis_gcc.h ****   \brief   Load-Acquire (32 bit)
 788:Core/cmsis_gcc.h ****   \details Executes a LDA instruction for 32 bit values.
 789:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 790:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 791:Core/cmsis_gcc.h ****  */
 792:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
 793:Core/cmsis_gcc.h **** {
 794:Core/cmsis_gcc.h ****     uint32_t result;
 795:Core/cmsis_gcc.h **** 
 796:Core/cmsis_gcc.h ****    __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 797:Core/cmsis_gcc.h ****    return(result);
 798:Core/cmsis_gcc.h **** }
 799:Core/cmsis_gcc.h **** 
 800:Core/cmsis_gcc.h **** 
 801:Core/cmsis_gcc.h **** /**
 802:Core/cmsis_gcc.h ****   \brief   Store-Release (8 bit)
 803:Core/cmsis_gcc.h ****   \details Executes a STLB instruction for 8 bit values.
 804:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 805:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 806:Core/cmsis_gcc.h ****  */
 807:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
 808:Core/cmsis_gcc.h **** {
 809:Core/cmsis_gcc.h ****    __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 810:Core/cmsis_gcc.h **** }
 811:Core/cmsis_gcc.h **** 
 812:Core/cmsis_gcc.h **** 
 813:Core/cmsis_gcc.h **** /**
 814:Core/cmsis_gcc.h ****   \brief   Store-Release (16 bit)
 815:Core/cmsis_gcc.h ****   \details Executes a STLH instruction for 16 bit values.
 816:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 817:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
ARM GAS  /tmp/ccQ8FEb0.s 			page 21


 818:Core/cmsis_gcc.h ****  */
 819:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
 820:Core/cmsis_gcc.h **** {
 821:Core/cmsis_gcc.h ****    __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 822:Core/cmsis_gcc.h **** }
 823:Core/cmsis_gcc.h **** 
 824:Core/cmsis_gcc.h **** 
 825:Core/cmsis_gcc.h **** /**
 826:Core/cmsis_gcc.h ****   \brief   Store-Release (32 bit)
 827:Core/cmsis_gcc.h ****   \details Executes a STL instruction for 32 bit values.
 828:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 829:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 830:Core/cmsis_gcc.h ****  */
 831:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
 832:Core/cmsis_gcc.h **** {
 833:Core/cmsis_gcc.h ****    __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
 834:Core/cmsis_gcc.h **** }
 835:Core/cmsis_gcc.h **** 
 836:Core/cmsis_gcc.h **** 
 837:Core/cmsis_gcc.h **** /**
 838:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (8 bit)
 839:Core/cmsis_gcc.h ****   \details Executes a LDAB exclusive instruction for 8 bit value.
 840:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 841:Core/cmsis_gcc.h ****   \return             value of type uint8_t at (*ptr)
 842:Core/cmsis_gcc.h ****  */
 843:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
 844:Core/cmsis_gcc.h **** {
 845:Core/cmsis_gcc.h ****     uint32_t result;
 846:Core/cmsis_gcc.h **** 
 847:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 848:Core/cmsis_gcc.h ****    return ((uint8_t) result);
 849:Core/cmsis_gcc.h **** }
 850:Core/cmsis_gcc.h **** 
 851:Core/cmsis_gcc.h **** 
 852:Core/cmsis_gcc.h **** /**
 853:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (16 bit)
 854:Core/cmsis_gcc.h ****   \details Executes a LDAH exclusive instruction for 16 bit values.
 855:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 856:Core/cmsis_gcc.h ****   \return        value of type uint16_t at (*ptr)
 857:Core/cmsis_gcc.h ****  */
 858:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
 859:Core/cmsis_gcc.h **** {
 860:Core/cmsis_gcc.h ****     uint32_t result;
 861:Core/cmsis_gcc.h **** 
 862:Core/cmsis_gcc.h ****    __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 863:Core/cmsis_gcc.h ****    return ((uint16_t) result);
 864:Core/cmsis_gcc.h **** }
 865:Core/cmsis_gcc.h **** 
 866:Core/cmsis_gcc.h **** 
 867:Core/cmsis_gcc.h **** /**
 868:Core/cmsis_gcc.h ****   \brief   Load-Acquire Exclusive (32 bit)
 869:Core/cmsis_gcc.h ****   \details Executes a LDA exclusive instruction for 32 bit values.
 870:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to data
 871:Core/cmsis_gcc.h ****   \return        value of type uint32_t at (*ptr)
 872:Core/cmsis_gcc.h ****  */
 873:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
 874:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccQ8FEb0.s 			page 22


 875:Core/cmsis_gcc.h ****     uint32_t result;
 876:Core/cmsis_gcc.h **** 
 877:Core/cmsis_gcc.h ****    __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
 878:Core/cmsis_gcc.h ****    return(result);
 879:Core/cmsis_gcc.h **** }
 880:Core/cmsis_gcc.h **** 
 881:Core/cmsis_gcc.h **** 
 882:Core/cmsis_gcc.h **** /**
 883:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (8 bit)
 884:Core/cmsis_gcc.h ****   \details Executes a STLB exclusive instruction for 8 bit values.
 885:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 886:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 887:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 888:Core/cmsis_gcc.h ****   \return          1  Function failed
 889:Core/cmsis_gcc.h ****  */
 890:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
 891:Core/cmsis_gcc.h **** {
 892:Core/cmsis_gcc.h ****    uint32_t result;
 893:Core/cmsis_gcc.h **** 
 894:Core/cmsis_gcc.h ****    __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 895:Core/cmsis_gcc.h ****    return(result);
 896:Core/cmsis_gcc.h **** }
 897:Core/cmsis_gcc.h **** 
 898:Core/cmsis_gcc.h **** 
 899:Core/cmsis_gcc.h **** /**
 900:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (16 bit)
 901:Core/cmsis_gcc.h ****   \details Executes a STLH exclusive instruction for 16 bit values.
 902:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 903:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 904:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 905:Core/cmsis_gcc.h ****   \return          1  Function failed
 906:Core/cmsis_gcc.h ****  */
 907:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
 908:Core/cmsis_gcc.h **** {
 909:Core/cmsis_gcc.h ****    uint32_t result;
 910:Core/cmsis_gcc.h **** 
 911:Core/cmsis_gcc.h ****    __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem
 912:Core/cmsis_gcc.h ****    return(result);
 913:Core/cmsis_gcc.h **** }
 914:Core/cmsis_gcc.h **** 
 915:Core/cmsis_gcc.h **** 
 916:Core/cmsis_gcc.h **** /**
 917:Core/cmsis_gcc.h ****   \brief   Store-Release Exclusive (32 bit)
 918:Core/cmsis_gcc.h ****   \details Executes a STL exclusive instruction for 32 bit values.
 919:Core/cmsis_gcc.h ****   \param [in]  value  Value to store
 920:Core/cmsis_gcc.h ****   \param [in]    ptr  Pointer to location
 921:Core/cmsis_gcc.h ****   \return          0  Function succeeded
 922:Core/cmsis_gcc.h ****   \return          1  Function failed
 923:Core/cmsis_gcc.h ****  */
 924:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
 925:Core/cmsis_gcc.h **** {
 926:Core/cmsis_gcc.h ****    uint32_t result;
 927:Core/cmsis_gcc.h **** 
 928:Core/cmsis_gcc.h ****    __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo
 929:Core/cmsis_gcc.h ****    return(result);
 930:Core/cmsis_gcc.h **** }
 931:Core/cmsis_gcc.h **** 
ARM GAS  /tmp/ccQ8FEb0.s 			page 23


 932:Core/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 933:Core/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 934:Core/cmsis_gcc.h **** 
 935:Core/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
 936:Core/cmsis_gcc.h **** 
 937:Core/cmsis_gcc.h **** 
 938:Core/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 939:Core/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 940:Core/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 941:Core/cmsis_gcc.h ****   @{
 942:Core/cmsis_gcc.h ****  */
 943:Core/cmsis_gcc.h **** 
 944:Core/cmsis_gcc.h **** /**
 945:Core/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 946:Core/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
 947:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 948:Core/cmsis_gcc.h ****  */
 949:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 950:Core/cmsis_gcc.h **** {
 951:Core/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 952:Core/cmsis_gcc.h **** }
 953:Core/cmsis_gcc.h **** 
 954:Core/cmsis_gcc.h **** 
 955:Core/cmsis_gcc.h **** /**
 956:Core/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 957:Core/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
 958:Core/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 959:Core/cmsis_gcc.h ****  */
 960:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 961:Core/cmsis_gcc.h **** {
 962:Core/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 963:Core/cmsis_gcc.h **** }
 964:Core/cmsis_gcc.h **** 
 965:Core/cmsis_gcc.h **** 
 966:Core/cmsis_gcc.h **** /**
 967:Core/cmsis_gcc.h ****   \brief   Get Control Register
 968:Core/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 969:Core/cmsis_gcc.h ****   \return               Control Register value
 970:Core/cmsis_gcc.h ****  */
 971:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 972:Core/cmsis_gcc.h **** {
 973:Core/cmsis_gcc.h ****   uint32_t result;
 974:Core/cmsis_gcc.h **** 
 975:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 976:Core/cmsis_gcc.h ****   return(result);
 977:Core/cmsis_gcc.h **** }
 978:Core/cmsis_gcc.h **** 
 979:Core/cmsis_gcc.h **** 
 980:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 981:Core/cmsis_gcc.h **** /**
 982:Core/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 983:Core/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 984:Core/cmsis_gcc.h ****   \return               non-secure Control Register value
 985:Core/cmsis_gcc.h ****  */
 986:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 987:Core/cmsis_gcc.h **** {
 988:Core/cmsis_gcc.h ****   uint32_t result;
ARM GAS  /tmp/ccQ8FEb0.s 			page 24


 989:Core/cmsis_gcc.h **** 
 990:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 991:Core/cmsis_gcc.h ****   return(result);
 992:Core/cmsis_gcc.h **** }
 993:Core/cmsis_gcc.h **** #endif
 994:Core/cmsis_gcc.h **** 
 995:Core/cmsis_gcc.h **** 
 996:Core/cmsis_gcc.h **** /**
 997:Core/cmsis_gcc.h ****   \brief   Set Control Register
 998:Core/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 999:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1000:Core/cmsis_gcc.h ****  */
1001:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
1002:Core/cmsis_gcc.h **** {
1003:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
1004:Core/cmsis_gcc.h ****   __ISB();
1005:Core/cmsis_gcc.h **** }
1006:Core/cmsis_gcc.h **** 
1007:Core/cmsis_gcc.h **** 
1008:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1009:Core/cmsis_gcc.h **** /**
1010:Core/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
1011:Core/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
1012:Core/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
1013:Core/cmsis_gcc.h ****  */
1014:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
1015:Core/cmsis_gcc.h **** {
1016:Core/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
1017:Core/cmsis_gcc.h ****   __ISB();
1018:Core/cmsis_gcc.h **** }
1019:Core/cmsis_gcc.h **** #endif
1020:Core/cmsis_gcc.h **** 
1021:Core/cmsis_gcc.h **** 
1022:Core/cmsis_gcc.h **** /**
1023:Core/cmsis_gcc.h ****   \brief   Get IPSR Register
1024:Core/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
1025:Core/cmsis_gcc.h ****   \return               IPSR Register value
1026:Core/cmsis_gcc.h ****  */
1027:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
1028:Core/cmsis_gcc.h **** {
1029:Core/cmsis_gcc.h ****   uint32_t result;
1030:Core/cmsis_gcc.h **** 
1031:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
1032:Core/cmsis_gcc.h ****   return(result);
1033:Core/cmsis_gcc.h **** }
1034:Core/cmsis_gcc.h **** 
1035:Core/cmsis_gcc.h **** 
1036:Core/cmsis_gcc.h **** /**
1037:Core/cmsis_gcc.h ****   \brief   Get APSR Register
1038:Core/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
1039:Core/cmsis_gcc.h ****   \return               APSR Register value
1040:Core/cmsis_gcc.h ****  */
1041:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
1042:Core/cmsis_gcc.h **** {
1043:Core/cmsis_gcc.h ****   uint32_t result;
1044:Core/cmsis_gcc.h **** 
1045:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
ARM GAS  /tmp/ccQ8FEb0.s 			page 25


1046:Core/cmsis_gcc.h ****   return(result);
1047:Core/cmsis_gcc.h **** }
1048:Core/cmsis_gcc.h **** 
1049:Core/cmsis_gcc.h **** 
1050:Core/cmsis_gcc.h **** /**
1051:Core/cmsis_gcc.h ****   \brief   Get xPSR Register
1052:Core/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
1053:Core/cmsis_gcc.h ****   \return               xPSR Register value
1054:Core/cmsis_gcc.h ****  */
1055:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
1056:Core/cmsis_gcc.h **** {
1057:Core/cmsis_gcc.h ****   uint32_t result;
1058:Core/cmsis_gcc.h **** 
1059:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
1060:Core/cmsis_gcc.h ****   return(result);
1061:Core/cmsis_gcc.h **** }
1062:Core/cmsis_gcc.h **** 
1063:Core/cmsis_gcc.h **** 
1064:Core/cmsis_gcc.h **** /**
1065:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
1066:Core/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
1067:Core/cmsis_gcc.h ****   \return               PSP Register value
1068:Core/cmsis_gcc.h ****  */
1069:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
1070:Core/cmsis_gcc.h **** {
1071:Core/cmsis_gcc.h ****   uint32_t result;
1072:Core/cmsis_gcc.h **** 
1073:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
1074:Core/cmsis_gcc.h ****   return(result);
1075:Core/cmsis_gcc.h **** }
1076:Core/cmsis_gcc.h **** 
1077:Core/cmsis_gcc.h **** 
1078:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1079:Core/cmsis_gcc.h **** /**
1080:Core/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
1081:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
1082:Core/cmsis_gcc.h ****   \return               PSP Register value
1083:Core/cmsis_gcc.h ****  */
1084:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
1085:Core/cmsis_gcc.h **** {
1086:Core/cmsis_gcc.h ****   uint32_t result;
1087:Core/cmsis_gcc.h **** 
1088:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
1089:Core/cmsis_gcc.h ****   return(result);
1090:Core/cmsis_gcc.h **** }
1091:Core/cmsis_gcc.h **** #endif
1092:Core/cmsis_gcc.h **** 
1093:Core/cmsis_gcc.h **** 
1094:Core/cmsis_gcc.h **** /**
1095:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
1096:Core/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
1097:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1098:Core/cmsis_gcc.h ****  */
1099:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
1100:Core/cmsis_gcc.h **** {
1101:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
1102:Core/cmsis_gcc.h **** }
ARM GAS  /tmp/ccQ8FEb0.s 			page 26


1103:Core/cmsis_gcc.h **** 
1104:Core/cmsis_gcc.h **** 
1105:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1106:Core/cmsis_gcc.h **** /**
1107:Core/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
1108:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
1109:Core/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
1110:Core/cmsis_gcc.h ****  */
1111:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
1112:Core/cmsis_gcc.h **** {
1113:Core/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
1114:Core/cmsis_gcc.h **** }
1115:Core/cmsis_gcc.h **** #endif
1116:Core/cmsis_gcc.h **** 
1117:Core/cmsis_gcc.h **** 
1118:Core/cmsis_gcc.h **** /**
1119:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
1120:Core/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
1121:Core/cmsis_gcc.h ****   \return               MSP Register value
1122:Core/cmsis_gcc.h ****  */
1123:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
1124:Core/cmsis_gcc.h **** {
1125:Core/cmsis_gcc.h ****   uint32_t result;
1126:Core/cmsis_gcc.h **** 
1127:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
1128:Core/cmsis_gcc.h ****   return(result);
1129:Core/cmsis_gcc.h **** }
1130:Core/cmsis_gcc.h **** 
1131:Core/cmsis_gcc.h **** 
1132:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1133:Core/cmsis_gcc.h **** /**
1134:Core/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
1135:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
1136:Core/cmsis_gcc.h ****   \return               MSP Register value
1137:Core/cmsis_gcc.h ****  */
1138:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
1139:Core/cmsis_gcc.h **** {
1140:Core/cmsis_gcc.h ****   uint32_t result;
1141:Core/cmsis_gcc.h **** 
1142:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
1143:Core/cmsis_gcc.h ****   return(result);
1144:Core/cmsis_gcc.h **** }
1145:Core/cmsis_gcc.h **** #endif
1146:Core/cmsis_gcc.h **** 
1147:Core/cmsis_gcc.h **** 
1148:Core/cmsis_gcc.h **** /**
1149:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
1150:Core/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
1151:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1152:Core/cmsis_gcc.h ****  */
1153:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
1154:Core/cmsis_gcc.h **** {
1155:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
1156:Core/cmsis_gcc.h **** }
1157:Core/cmsis_gcc.h **** 
1158:Core/cmsis_gcc.h **** 
1159:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ARM GAS  /tmp/ccQ8FEb0.s 			page 27


1160:Core/cmsis_gcc.h **** /**
1161:Core/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
1162:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
1163:Core/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
1164:Core/cmsis_gcc.h ****  */
1165:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
1166:Core/cmsis_gcc.h **** {
1167:Core/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
1168:Core/cmsis_gcc.h **** }
1169:Core/cmsis_gcc.h **** #endif
1170:Core/cmsis_gcc.h **** 
1171:Core/cmsis_gcc.h **** 
1172:Core/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
1173:Core/cmsis_gcc.h **** /**
1174:Core/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
1175:Core/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
1176:Core/cmsis_gcc.h ****   \return               SP Register value
1177:Core/cmsis_gcc.h ****  */
1178:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
1179:Core/cmsis_gcc.h **** {
1180:Core/cmsis_gcc.h ****   uint32_t result;
1181:Core/cmsis_gcc.h **** 
1182:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
1183:Core/cmsis_gcc.h ****   return(result);
1184:Core/cmsis_gcc.h **** }
1185:Core/cmsis_gcc.h **** 
1186:Core/cmsis_gcc.h **** 
1187:Core/cmsis_gcc.h **** /**
1188:Core/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
1189:Core/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
1190:Core/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
1191:Core/cmsis_gcc.h ****  */
1192:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
1193:Core/cmsis_gcc.h **** {
1194:Core/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
1195:Core/cmsis_gcc.h **** }
1196:Core/cmsis_gcc.h **** #endif
1197:Core/cmsis_gcc.h **** 
1198:Core/cmsis_gcc.h **** 
1199:Core/cmsis_gcc.h **** /**
1200:Core/cmsis_gcc.h ****   \brief   Get Priority Mask
1201:Core/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
1202:Core/cmsis_gcc.h ****   \return               Priority Mask value
1203:Core/cmsis_gcc.h ****  */
1204:Core/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 227              		.loc 2 1204 31 view .LVU61
 228              	.LBB57:
1205:Core/cmsis_gcc.h **** {
1206:Core/cmsis_gcc.h ****   uint32_t result;
 229              		.loc 2 1206 3 view .LVU62
1207:Core/cmsis_gcc.h **** 
1208:Core/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) );
 230              		.loc 2 1208 3 view .LVU63
 231              		.syntax divided
 232              	@ 1208 "Core/cmsis_gcc.h" 1
 233 008c EFF31081 		MRS r1, primask
 234              	@ 0 "" 2
ARM GAS  /tmp/ccQ8FEb0.s 			page 28


 235              	.LVL14:
1209:Core/cmsis_gcc.h ****   return(result);
 236              		.loc 2 1209 3 view .LVU64
 237              		.loc 2 1209 3 is_stmt 0 view .LVU65
 238              		.thumb
 239              		.syntax unified
 240              	.LBE57:
 241              	.LBE56:
 242              		.loc 1 74 3 is_stmt 1 discriminator 2 view .LVU66
 243              	.LBB58:
 244              	.LBI58:
 960:Core/cmsis_gcc.h **** {
 245              		.loc 2 960 27 view .LVU67
 246              	.LBB59:
 962:Core/cmsis_gcc.h **** }
 247              		.loc 2 962 3 view .LVU68
 248              		.syntax divided
 249              	@ 962 "Core/cmsis_gcc.h" 1
 250 0090 72B6     		cpsid i
 251              	@ 0 "" 2
 252              		.thumb
 253              		.syntax unified
 254              	.LBE59:
 255              	.LBE58:
 256              		.loc 1 74 3 discriminator 3 view .LVU69
 257 0092 1149     		ldr	r1, .L4+16
 258 0094 114D     		ldr	r5, .L4+20
 259 0096 0D60     		str	r5, [r1]
 260              		.loc 1 74 19 discriminator 3 view .LVU70
  75:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL) | (ACMP_InitStruct->TRIG_SOURC
 261              		.loc 1 75 3 view .LVU71
 262              		.loc 1 75 10 is_stmt 0 view .LVU72
 263 0098 1149     		ldr	r1, .L4+24
 264              		.loc 1 75 70 view .LVU73
 265 009a 456B     		ldr	r5, [r0, #52]
 266              		.loc 1 75 10 view .LVU74
 267 009c 8C46     		mov	ip, r1
 268 009e 096E     		ldr	r1, [r1, #96]
 269 00a0 8846     		mov	r8, r1
 270              		.loc 1 75 70 view .LVU75
 271 00a2 016B     		ldr	r1, [r0, #48]
  76:Library/src/lcm32f06x_acmp.c ****                                    (ACMP_InitStruct->CP_EXTSP << 12);
 272              		.loc 1 76 63 view .LVU76
 273 00a4 806B     		ldr	r0, [r0, #56]
 274              	.LVL15:
  75:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL) | (ACMP_InitStruct->TRIG_SOURC
 275              		.loc 1 75 70 view .LVU77
 276 00a6 2943     		orrs	r1, r5
  75:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL) | (ACMP_InitStruct->TRIG_SOURC
 277              		.loc 1 75 22 view .LVU78
 278 00a8 4546     		mov	r5, r8
 279              		.loc 1 76 63 view .LVU79
 280 00aa 0003     		lsls	r0, r0, #12
  75:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL) | (ACMP_InitStruct->TRIG_SOURC
 281              		.loc 1 75 22 view .LVU80
 282 00ac 2943     		orrs	r1, r5
 283 00ae 0143     		orrs	r1, r0
ARM GAS  /tmp/ccQ8FEb0.s 			page 29


 284 00b0 6046     		mov	r0, ip
 285 00b2 0166     		str	r1, [r0, #96]
  77:Library/src/lcm32f06x_acmp.c ****   __dekey();
 286              		.loc 1 77 3 is_stmt 1 view .LVU81
 287              	.LBB60:
 288              	.LBI60:
 949:Core/cmsis_gcc.h **** {
 289              		.loc 2 949 27 view .LVU82
 290              	.LBB61:
 951:Core/cmsis_gcc.h **** }
 291              		.loc 2 951 3 view .LVU83
 292              		.syntax divided
 293              	@ 951 "Core/cmsis_gcc.h" 1
 294 00b4 62B6     		cpsie i
 295              	@ 0 "" 2
 296              		.thumb
 297              		.syntax unified
 298              	.LBE61:
 299              	.LBE60:
 300              		.loc 1 77 12 discriminator 1 view .LVU84
  78:Library/src/lcm32f06x_acmp.c **** 
  79:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CSR = tmpreg;
 301              		.loc 1 79 3 view .LVU85
 302              		.loc 1 79 19 is_stmt 0 view .LVU86
 303 00b6 2362     		str	r3, [r4, #32]
  80:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR = tmpreg1;
 304              		.loc 1 80 3 is_stmt 1 view .LVU87
  81:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_EXTCFG = tmpreg2;
 305              		.loc 1 81 22 is_stmt 0 view .LVU88
 306 00b8 5346     		mov	r3, r10
 307              	.LVL16:
  82:Library/src/lcm32f06x_acmp.c **** }
 308              		.loc 1 82 1 view .LVU89
 309              		@ sp needed
  80:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR = tmpreg1;
 310              		.loc 1 80 22 view .LVU90
 311 00ba A251     		str	r2, [r4, r6]
 312              	.LVL17:
  81:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_EXTCFG = tmpreg2;
 313              		.loc 1 81 3 is_stmt 1 view .LVU91
  81:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_EXTCFG = tmpreg2;
 314              		.loc 1 81 22 is_stmt 0 view .LVU92
 315 00bc E750     		str	r7, [r4, r3]
 316              	.LVL18:
 317              		.loc 1 82 1 view .LVU93
 318 00be E0BC     		pop	{r5, r6, r7}
 319 00c0 BA46     		mov	r10, r7
 320 00c2 B146     		mov	r9, r6
 321 00c4 A846     		mov	r8, r5
 322 00c6 F0BD     		pop	{r4, r5, r6, r7, pc}
 323              	.L5:
 324              		.align	2
 325              	.L4:
 326 00c8 007C0140 		.word	1073839104
 327 00cc 0FF0FFE7 		.word	-402657265
 328 00d0 0780FFFF 		.word	-32761
 329 00d4 FE00FF9F 		.word	-1610678018
ARM GAS  /tmp/ccQ8FEb0.s 			page 30


 330 00d8 7C700048 		.word	1207988348
 331 00dc 9A65FA05 		.word	100296090
 332 00e0 00700048 		.word	1207988224
 333              		.cfi_endproc
 334              	.LFE46:
 336              		.section	.text.ACMP1_Init,"ax",%progbits
 337              		.align	1
 338              		.p2align 2,,3
 339              		.global	ACMP1_Init
 340              		.syntax unified
 341              		.code	16
 342              		.thumb_func
 344              	ACMP1_Init:
 345              	.LVL19:
 346              	.LFB47:
  83:Library/src/lcm32f06x_acmp.c **** 
  84:Library/src/lcm32f06x_acmp.c **** /**
  85:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_Init
  86:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Initializes the ACMP0 peripheral according to the specified 
  87:Library/src/lcm32f06x_acmp.c ****   *             parameters in the ACMP_InitStruct.
  88:Library/src/lcm32f06x_acmp.c ****   *         CN: 根据 ACMP_InitStruct 中指定的参数初始化 ACMP0。
  89:Library/src/lcm32f06x_acmp.c ****   * @param  ACMP_InitStruct: 
  90:Library/src/lcm32f06x_acmp.c ****   *         EN: pointer to a ACMP_InitTypeDef structure that contains the 
  91:Library/src/lcm32f06x_acmp.c ****   *             configuration information for the specified ACMP peripheral.
  92:Library/src/lcm32f06x_acmp.c ****   *         CN: 指向 ACMP_InitTypeDef 结构的指针，该结构包含指定 ACMP 外设的配置信息。
  93:Library/src/lcm32f06x_acmp.c ****   * @retval None
  94:Library/src/lcm32f06x_acmp.c ****   */
  95:Library/src/lcm32f06x_acmp.c **** void ACMP1_Init(ACMP_InitTypeDef *ACMP_InitStruct)
  96:Library/src/lcm32f06x_acmp.c **** {
 347              		.loc 1 96 1 is_stmt 1 view -0
 348              		.cfi_startproc
 349              		@ args = 0, pretend = 0, frame = 0
 350              		@ frame_needed = 0, uses_anonymous_args = 0
  97:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
 351              		.loc 1 97 3 view .LVU95
  98:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg1 = 0;
 352              		.loc 1 98 3 view .LVU96
  99:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg2 = 0;
 353              		.loc 1 99 3 view .LVU97
 100:Library/src/lcm32f06x_acmp.c ****   tmpreg = ACMP->ACMP1_CSR;
 354              		.loc 1 100 3 view .LVU98
  96:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
 355              		.loc 1 96 1 is_stmt 0 view .LVU99
 356 0000 F0B5     		push	{r4, r5, r6, r7, lr}
 357              	.LCFI3:
 358              		.cfi_def_cfa_offset 20
 359              		.cfi_offset 4, -20
 360              		.cfi_offset 5, -16
 361              		.cfi_offset 6, -12
 362              		.cfi_offset 7, -8
 363              		.cfi_offset 14, -4
 101:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
 102:Library/src/lcm32f06x_acmp.c **** 
 103:Library/src/lcm32f06x_acmp.c ****   tmpreg1 = ACMP->ACMP1_MUXCSR;
 104:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 105:Library/src/lcm32f06x_acmp.c **** 
 106:Library/src/lcm32f06x_acmp.c ****   tmpreg2 = ACMP->ACMP1_EXTCFG;
ARM GAS  /tmp/ccQ8FEb0.s 			page 31


 364              		.loc 1 106 11 view .LVU100
 365 0002 CC22     		movs	r2, #204
  96:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
 366              		.loc 1 96 1 view .LVU101
 367 0004 D646     		mov	lr, r10
 368 0006 4F46     		mov	r7, r9
 369 0008 4646     		mov	r6, r8
 103:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 370              		.loc 1 103 11 view .LVU102
 371 000a C825     		movs	r5, #200
 100:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
 372              		.loc 1 100 10 view .LVU103
 373 000c 2F49     		ldr	r1, .L7
  96:Library/src/lcm32f06x_acmp.c ****   uint32_t tmpreg = 0;
 374              		.loc 1 96 1 view .LVU104
 375 000e C0B5     		push	{r6, r7, lr}
 376              	.LCFI4:
 377              		.cfi_def_cfa_offset 32
 378              		.cfi_offset 8, -32
 379              		.cfi_offset 9, -28
 380              		.cfi_offset 10, -24
 100:Library/src/lcm32f06x_acmp.c ****   tmpreg &= ~(0x00007FF8);
 381              		.loc 1 100 10 view .LVU105
 382 0010 4B6A     		ldr	r3, [r1, #36]
 383              	.LVL20:
 101:Library/src/lcm32f06x_acmp.c **** 
 384              		.loc 1 101 3 is_stmt 1 view .LVU106
 103:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 385              		.loc 1 103 3 view .LVU107
 386              		.loc 1 106 11 is_stmt 0 view .LVU108
 387 0012 9246     		mov	r10, r2
 103:Library/src/lcm32f06x_acmp.c ****   tmpreg1 &= ~(0x6000FF01);
 388              		.loc 1 103 11 view .LVU109
 389 0014 4E59     		ldr	r6, [r1, r5]
 390              	.LVL21:
 104:Library/src/lcm32f06x_acmp.c **** 
 391              		.loc 1 104 3 is_stmt 1 view .LVU110
 392              		.loc 1 106 3 view .LVU111
 393              		.loc 1 106 11 is_stmt 0 view .LVU112
 394 0016 8F58     		ldr	r7, [r1, r2]
 395              	.LVL22:
 107:Library/src/lcm32f06x_acmp.c ****   tmpreg2 &= ~(ANACTRL_ACMPX_EXTCFG_EXTDTG_Msk | ANACTRL_ACMPX_EXTCFG_EXTSE_Msk);
 396              		.loc 1 107 3 is_stmt 1 view .LVU113
 397              		.loc 1 107 11 is_stmt 0 view .LVU114
 398 0018 2D4A     		ldr	r2, .L7+4
 399 001a 046A     		ldr	r4, [r0, #32]
 400 001c 1740     		ands	r7, r2
 401              	.LVL23:
 108:Library/src/lcm32f06x_acmp.c **** 
 109:Library/src/lcm32f06x_acmp.c ****   tmpreg |= (((uint8_t)ACMP_InitStruct->ACMP_FILTER_SEL << 23) | (ACMP_InitStruct->ACMP_LPS << 15) 
 402              		.loc 1 109 3 is_stmt 1 view .LVU115
 403 001e C269     		ldr	r2, [r0, #28]
 404 0020 2243     		orrs	r2, r4
 101:Library/src/lcm32f06x_acmp.c **** 
 405              		.loc 1 101 10 is_stmt 0 view .LVU116
 406 0022 2C4C     		ldr	r4, .L7+8
 407 0024 2340     		ands	r3, r4
ARM GAS  /tmp/ccQ8FEb0.s 			page 32


 408              	.LVL24:
 101:Library/src/lcm32f06x_acmp.c **** 
 409              		.loc 1 101 10 view .LVU117
 410 0026 1A43     		orrs	r2, r3
 110:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 111:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_Is | (ACMP_InitStruct->ACMP_HYSEN << 2) | (ACMP_InitStruct->ACM
 411              		.loc 1 111 58 view .LVU118
 412 0028 2423     		movs	r3, #36
 413              	.LVL25:
 414              		.loc 1 111 71 view .LVU119
 415 002a C35C     		ldrb	r3, [r0, r3]
 110:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 416              		.loc 1 110 30 view .LVU120
 417 002c 447E     		ldrb	r4, [r0, #25]
 418              		.loc 1 111 71 view .LVU121
 419 002e 9B00     		lsls	r3, r3, #2
 420 0030 1A43     		orrs	r2, r3
 421              		.loc 1 111 95 view .LVU122
 422 0032 2523     		movs	r3, #37
 423              		.loc 1 111 107 view .LVU123
 424 0034 C35C     		ldrb	r3, [r0, r3]
 110:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 425              		.loc 1 110 40 view .LVU124
 426 0036 E402     		lsls	r4, r4, #11
 427              		.loc 1 111 107 view .LVU125
 428 0038 5B00     		lsls	r3, r3, #1
 429 003a 1A43     		orrs	r2, r3
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 430              		.loc 1 109 82 view .LVU126
 431 003c 037E     		ldrb	r3, [r0, #24]
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 432              		.loc 1 109 93 view .LVU127
 433 003e DB03     		lsls	r3, r3, #15
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 434              		.loc 1 109 100 view .LVU128
 435 0040 2343     		orrs	r3, r4
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 436              		.loc 1 109 57 view .LVU129
 437 0042 4469     		ldr	r4, [r0, #20]
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 438              		.loc 1 109 100 view .LVU130
 439 0044 9946     		mov	r9, r3
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 440              		.loc 1 109 57 view .LVU131
 441 0046 E405     		lsls	r4, r4, #23
 442 0048 A446     		mov	ip, r4
 443 004a FF24     		movs	r4, #255
 444 004c E405     		lsls	r4, r4, #23
 445 004e A046     		mov	r8, r4
 446 0050 6446     		mov	r4, ip
 447 0052 4346     		mov	r3, r8
 448 0054 1C40     		ands	r4, r3
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 449              		.loc 1 109 100 view .LVU132
 450 0056 2300     		movs	r3, r4
 451 0058 4C46     		mov	r4, r9
 452 005a 1C43     		orrs	r4, r3
ARM GAS  /tmp/ccQ8FEb0.s 			page 33


 453 005c 2300     		movs	r3, r4
 112:Library/src/lcm32f06x_acmp.c **** 
 113:Library/src/lcm32f06x_acmp.c ****   tmpreg1 |= (ACMP_InitStruct->ACMP_TrigMode | ACMP_InitStruct->ACMP_WorkMode | \
 454              		.loc 1 113 46 view .LVU133
 455 005e 4468     		ldr	r4, [r0, #4]
 109:Library/src/lcm32f06x_acmp.c ****              (ACMP_InitStruct->ACMP_FS << 11) | ACMP_InitStruct->ACMP_Delay_time | \
 456              		.loc 1 109 10 view .LVU134
 457 0060 1343     		orrs	r3, r2
 458              	.LVL26:
 459              		.loc 1 113 3 is_stmt 1 view .LVU135
 460              		.loc 1 113 46 is_stmt 0 view .LVU136
 461 0062 0268     		ldr	r2, [r0]
 462 0064 2243     		orrs	r2, r4
 104:Library/src/lcm32f06x_acmp.c **** 
 463              		.loc 1 104 11 view .LVU137
 464 0066 1C4C     		ldr	r4, .L7+12
 465 0068 2640     		ands	r6, r4
 466              	.LVL27:
 114:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_P_Select| ACMP_InitStruct->ACMP_N_Select | \
 115:Library/src/lcm32f06x_acmp.c ****               ((uint8_t)ACMP_InitStruct->ACMP_CNT_CFG << 1));
 467              		.loc 1 115 55 view .LVU138
 468 006a FF24     		movs	r4, #255
 469 006c 3243     		orrs	r2, r6
 470 006e 8668     		ldr	r6, [r0, #8]
 471              	.LVL28:
 472              		.loc 1 115 55 view .LVU139
 473 0070 6400     		lsls	r4, r4, #1
 474 0072 3243     		orrs	r2, r6
 475 0074 C668     		ldr	r6, [r0, #12]
 476 0076 3243     		orrs	r2, r6
 477 0078 0669     		ldr	r6, [r0, #16]
 478 007a 7600     		lsls	r6, r6, #1
 479 007c 2640     		ands	r6, r4
 113:Library/src/lcm32f06x_acmp.c ****               ACMP_InitStruct->ACMP_P_Select| ACMP_InitStruct->ACMP_N_Select | \
 480              		.loc 1 113 11 view .LVU140
 481 007e 1643     		orrs	r6, r2
 482              	.LVL29:
 116:Library/src/lcm32f06x_acmp.c **** 
 117:Library/src/lcm32f06x_acmp.c ****   tmpreg2 |= ((ACMP_InitStruct->EXTSELECT) | ACMP_InitStruct->TRIG_DELAY_TIME);
 483              		.loc 1 117 3 is_stmt 1 view .LVU141
 484              		.loc 1 117 44 is_stmt 0 view .LVU142
 485 0080 C46A     		ldr	r4, [r0, #44]
 486 0082 826A     		ldr	r2, [r0, #40]
 487 0084 2243     		orrs	r2, r4
 488              		.loc 1 117 11 view .LVU143
 489 0086 1743     		orrs	r7, r2
 490              	.LVL30:
 118:Library/src/lcm32f06x_acmp.c **** 
 119:Library/src/lcm32f06x_acmp.c ****   sysctrl_access();
 491              		.loc 1 119 3 is_stmt 1 view .LVU144
 492              	.LBB62:
 493              	.LBI62:
 258:Core/cmsis_gcc.h **** {
 494              		.loc 2 258 27 view .LVU145
 495              	.LBB63:
 260:Core/cmsis_gcc.h **** }
 496              		.loc 2 260 3 view .LVU146
ARM GAS  /tmp/ccQ8FEb0.s 			page 34


 497              		.syntax divided
 498              	@ 260 "Core/cmsis_gcc.h" 1
 499 0088 BFF36F8F 		isb 0xF
 500              	@ 0 "" 2
 501              		.thumb
 502              		.syntax unified
 503              	.LBE63:
 504              	.LBE62:
 505              		.loc 1 119 3 discriminator 1 view .LVU147
 506              	.LBB64:
 507              	.LBI64:
1204:Core/cmsis_gcc.h **** {
 508              		.loc 2 1204 31 view .LVU148
 509              	.LBB65:
1206:Core/cmsis_gcc.h **** 
 510              		.loc 2 1206 3 view .LVU149
1208:Core/cmsis_gcc.h ****   return(result);
 511              		.loc 2 1208 3 view .LVU150
 512              		.syntax divided
 513              	@ 1208 "Core/cmsis_gcc.h" 1
 514 008c EFF31082 		MRS r2, primask
 515              	@ 0 "" 2
 516              	.LVL31:
 517              		.loc 2 1209 3 view .LVU151
 518              		.loc 2 1209 3 is_stmt 0 view .LVU152
 519              		.thumb
 520              		.syntax unified
 521              	.LBE65:
 522              	.LBE64:
 523              		.loc 1 119 3 is_stmt 1 discriminator 2 view .LVU153
 524              	.LBB66:
 525              	.LBI66:
 960:Core/cmsis_gcc.h **** {
 526              		.loc 2 960 27 view .LVU154
 527              	.LBB67:
 962:Core/cmsis_gcc.h **** }
 528              		.loc 2 962 3 view .LVU155
 529              		.syntax divided
 530              	@ 962 "Core/cmsis_gcc.h" 1
 531 0090 72B6     		cpsid i
 532              	@ 0 "" 2
 533              		.thumb
 534              		.syntax unified
 535              	.LBE67:
 536              	.LBE66:
 537              		.loc 1 119 3 discriminator 3 view .LVU156
 538 0092 124A     		ldr	r2, .L7+16
 539 0094 124C     		ldr	r4, .L7+20
 540 0096 1460     		str	r4, [r2]
 541              		.loc 1 119 19 discriminator 3 view .LVU157
 120:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL << 2) | (ACMP_InitStruct->TRIG_
 542              		.loc 1 120 3 view .LVU158
 543              		.loc 1 120 10 is_stmt 0 view .LVU159
 544 0098 124A     		ldr	r2, .L7+24
 545              		.loc 1 120 107 view .LVU160
 546 009a 446B     		ldr	r4, [r0, #52]
 547              		.loc 1 120 10 view .LVU161
ARM GAS  /tmp/ccQ8FEb0.s 			page 35


 548 009c 9446     		mov	ip, r2
 549 009e 126E     		ldr	r2, [r2, #96]
 550              		.loc 1 120 107 view .LVU162
 551 00a0 2401     		lsls	r4, r4, #4
 552              		.loc 1 120 10 view .LVU163
 553 00a2 9146     		mov	r9, r2
 554              		.loc 1 120 25 view .LVU164
 555 00a4 026B     		ldr	r2, [r0, #48]
 121:Library/src/lcm32f06x_acmp.c ****                                    (ACMP_InitStruct->CP_EXTSP << 14);
 556              		.loc 1 121 63 view .LVU165
 557 00a6 806B     		ldr	r0, [r0, #56]
 558              	.LVL32:
 120:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL << 2) | (ACMP_InitStruct->TRIG_
 559              		.loc 1 120 25 view .LVU166
 560 00a8 9200     		lsls	r2, r2, #2
 120:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL << 2) | (ACMP_InitStruct->TRIG_
 561              		.loc 1 120 75 view .LVU167
 562 00aa 2243     		orrs	r2, r4
 120:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL << 2) | (ACMP_InitStruct->TRIG_
 563              		.loc 1 120 22 view .LVU168
 564 00ac 4C46     		mov	r4, r9
 565              		.loc 1 121 63 view .LVU169
 566 00ae 8003     		lsls	r0, r0, #14
 120:Library/src/lcm32f06x_acmp.c ****   SYSCTRL->EDU_CFG16 |= (uint32_t) (ACMP_InitStruct->EXTEN_MODE_SEL << 2) | (ACMP_InitStruct->TRIG_
 567              		.loc 1 120 22 view .LVU170
 568 00b0 2243     		orrs	r2, r4
 569 00b2 0243     		orrs	r2, r0
 570 00b4 6046     		mov	r0, ip
 571 00b6 0266     		str	r2, [r0, #96]
 122:Library/src/lcm32f06x_acmp.c ****   __dekey();
 572              		.loc 1 122 3 is_stmt 1 view .LVU171
 573              	.LBB68:
 574              	.LBI68:
 949:Core/cmsis_gcc.h **** {
 575              		.loc 2 949 27 view .LVU172
 576              	.LBB69:
 951:Core/cmsis_gcc.h **** }
 577              		.loc 2 951 3 view .LVU173
 578              		.syntax divided
 579              	@ 951 "Core/cmsis_gcc.h" 1
 580 00b8 62B6     		cpsie i
 581              	@ 0 "" 2
 582              		.thumb
 583              		.syntax unified
 584              	.LBE69:
 585              	.LBE68:
 586              		.loc 1 122 12 discriminator 1 view .LVU174
 123:Library/src/lcm32f06x_acmp.c **** 
 124:Library/src/lcm32f06x_acmp.c **** 
 125:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CSR = tmpreg;
 587              		.loc 1 125 3 view .LVU175
 588              		.loc 1 125 19 is_stmt 0 view .LVU176
 589 00ba 4B62     		str	r3, [r1, #36]
 126:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR = tmpreg1;
 590              		.loc 1 126 3 is_stmt 1 view .LVU177
 127:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_EXTCFG = tmpreg2;
 591              		.loc 1 127 22 is_stmt 0 view .LVU178
ARM GAS  /tmp/ccQ8FEb0.s 			page 36


 592 00bc 5346     		mov	r3, r10
 593              	.LVL33:
 128:Library/src/lcm32f06x_acmp.c **** }
 594              		.loc 1 128 1 view .LVU179
 595              		@ sp needed
 126:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR = tmpreg1;
 596              		.loc 1 126 22 view .LVU180
 597 00be 4E51     		str	r6, [r1, r5]
 598              	.LVL34:
 127:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_EXTCFG = tmpreg2;
 599              		.loc 1 127 3 is_stmt 1 view .LVU181
 127:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_EXTCFG = tmpreg2;
 600              		.loc 1 127 22 is_stmt 0 view .LVU182
 601 00c0 CF50     		str	r7, [r1, r3]
 602              	.LVL35:
 603              	.LVL36:
 604              		.loc 1 128 1 view .LVU183
 605 00c2 E0BC     		pop	{r5, r6, r7}
 606 00c4 BA46     		mov	r10, r7
 607 00c6 B146     		mov	r9, r6
 608 00c8 A846     		mov	r8, r5
 609 00ca F0BD     		pop	{r4, r5, r6, r7, pc}
 610              	.L8:
 611              		.align	2
 612              	.L7:
 613 00cc 007C0140 		.word	1073839104
 614 00d0 0FF0FFE7 		.word	-402657265
 615 00d4 0780FFFF 		.word	-32761
 616 00d8 FE00FF9F 		.word	-1610678018
 617 00dc 7C700048 		.word	1207988348
 618 00e0 9A65FA05 		.word	100296090
 619 00e4 00700048 		.word	1207988224
 620              		.cfi_endproc
 621              	.LFE47:
 623              		.section	.text.ACMP_StructInit,"ax",%progbits
 624              		.align	1
 625              		.p2align 2,,3
 626              		.global	ACMP_StructInit
 627              		.syntax unified
 628              		.code	16
 629              		.thumb_func
 631              	ACMP_StructInit:
 632              	.LVL37:
 633              	.LFB48:
 129:Library/src/lcm32f06x_acmp.c **** 
 130:Library/src/lcm32f06x_acmp.c **** /**
 131:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP_StructInit
 132:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Fills each ACMP_InitTypeDef member with its default value.
 133:Library/src/lcm32f06x_acmp.c ****   *         CN: 用默认值填充每个 ACMP_InitTypeDef 成员。
 134:Library/src/lcm32f06x_acmp.c ****   * @param  ACMP_InitStruct: 
 135:Library/src/lcm32f06x_acmp.c ****   *         EN: pointer to a ACMP_InitTypeDef structure that contains the 
 136:Library/src/lcm32f06x_acmp.c ****   *             configuration information for the specified ACMP peripheral.
 137:Library/src/lcm32f06x_acmp.c ****   *         CN: 指向 ACMP_InitTypeDef 结构的指针，该结构包含指定 ACMP 外设的配置信息。
 138:Library/src/lcm32f06x_acmp.c ****   * @retval None
 139:Library/src/lcm32f06x_acmp.c ****   */
 140:Library/src/lcm32f06x_acmp.c **** void ACMP_StructInit(ACMP_InitTypeDef *ACMP_InitStruct)
 141:Library/src/lcm32f06x_acmp.c **** {
ARM GAS  /tmp/ccQ8FEb0.s 			page 37


 634              		.loc 1 141 1 is_stmt 1 view -0
 635              		.cfi_startproc
 636              		@ args = 0, pretend = 0, frame = 0
 637              		@ frame_needed = 0, uses_anonymous_args = 0
 638              		@ link register save eliminated.
 142:Library/src/lcm32f06x_acmp.c ****   /*--------------- Reset ACMP init structure parameters values -----------------*/
 143:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_TrigMode = ACMP_TrigMode_Software;          //比较器触发模式选择
 639              		.loc 1 143 3 view .LVU185
 640              		.loc 1 143 34 is_stmt 0 view .LVU186
 641 0000 0023     		movs	r3, #0
 144:Library/src/lcm32f06x_acmp.c **** 
 145:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_WorkMode = ACMP_WorkMode_SingleCompar;      //比较器工作模式选择
 146:Library/src/lcm32f06x_acmp.c **** 
 147:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_P_Select = CP_PS_P0;                        //比较器正端输入选择
 148:Library/src/lcm32f06x_acmp.c **** 
 149:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_N_Select = CP_NS_N0;                        //比较器负端输入选择
 150:Library/src/lcm32f06x_acmp.c **** 
 151:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_CNT_CFG = 0;                                //通道间切换时钟周期数选择
 152:Library/src/lcm32f06x_acmp.c **** 
 153:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_FILTER_SEL = 0;                             //比较器数字滤波挡位选择
 154:Library/src/lcm32f06x_acmp.c **** 
 155:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_LPS = DISABLE;                              //低功耗模式使能
 156:Library/src/lcm32f06x_acmp.c **** 
 157:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_FS = DISABLE;                               //输出滤波使能配
 158:Library/src/lcm32f06x_acmp.c **** 
 159:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_Delay_time = 0;                             //输出延迟配置
 160:Library/src/lcm32f06x_acmp.c **** 
 161:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_Is = DISABLE;                               //比较器输出极性
 162:Library/src/lcm32f06x_acmp.c **** 
 163:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_HYSEN = DISABLE;                            //迟滞使能配置
 164:Library/src/lcm32f06x_acmp.c **** 
 165:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->ACMP_FREN = DISABLE;                             //快速响应使能
 166:Library/src/lcm32f06x_acmp.c **** 
 167:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->EXTSELECT = ACMP_EXTSELG_DIS;                    //两组触发源使能
 168:Library/src/lcm32f06x_acmp.c **** 
 169:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->TRIG_DELAY_TIME = TRIG_DELAY_TIME_0CLK;          //外部触发延迟时钟
 170:Library/src/lcm32f06x_acmp.c **** 
 171:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->EXTEN_MODE_SEL = ACMP_EXTEN_RISE;                //外部触发模式选择
 172:Library/src/lcm32f06x_acmp.c **** 
 173:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->TRIG_SOURCE = EXTSELG0_TIM1_TRIG_OC1;            //外部触发源选择
 174:Library/src/lcm32f06x_acmp.c **** 
 175:Library/src/lcm32f06x_acmp.c ****   ACMP_InitStruct->CP_EXTSP = CP_EXTSP_POS;                         //触发源极性选择
 176:Library/src/lcm32f06x_acmp.c **** };
 642              		.loc 1 176 1 view .LVU187
 643              		@ sp needed
 143:Library/src/lcm32f06x_acmp.c **** 
 644              		.loc 1 143 34 view .LVU188
 645 0002 0360     		str	r3, [r0]
 145:Library/src/lcm32f06x_acmp.c **** 
 646              		.loc 1 145 3 is_stmt 1 view .LVU189
 145:Library/src/lcm32f06x_acmp.c **** 
 647              		.loc 1 145 34 is_stmt 0 view .LVU190
 648 0004 4360     		str	r3, [r0, #4]
 147:Library/src/lcm32f06x_acmp.c **** 
 649              		.loc 1 147 3 is_stmt 1 view .LVU191
 147:Library/src/lcm32f06x_acmp.c **** 
 650              		.loc 1 147 34 is_stmt 0 view .LVU192
ARM GAS  /tmp/ccQ8FEb0.s 			page 38


 651 0006 8360     		str	r3, [r0, #8]
 149:Library/src/lcm32f06x_acmp.c **** 
 652              		.loc 1 149 3 is_stmt 1 view .LVU193
 149:Library/src/lcm32f06x_acmp.c **** 
 653              		.loc 1 149 34 is_stmt 0 view .LVU194
 654 0008 C360     		str	r3, [r0, #12]
 151:Library/src/lcm32f06x_acmp.c **** 
 655              		.loc 1 151 3 is_stmt 1 view .LVU195
 151:Library/src/lcm32f06x_acmp.c **** 
 656              		.loc 1 151 33 is_stmt 0 view .LVU196
 657 000a 0361     		str	r3, [r0, #16]
 153:Library/src/lcm32f06x_acmp.c **** 
 658              		.loc 1 153 3 is_stmt 1 view .LVU197
 153:Library/src/lcm32f06x_acmp.c **** 
 659              		.loc 1 153 36 is_stmt 0 view .LVU198
 660 000c 4361     		str	r3, [r0, #20]
 155:Library/src/lcm32f06x_acmp.c **** 
 661              		.loc 1 155 3 is_stmt 1 view .LVU199
 157:Library/src/lcm32f06x_acmp.c **** 
 662              		.loc 1 157 3 view .LVU200
 155:Library/src/lcm32f06x_acmp.c **** 
 663              		.loc 1 155 29 is_stmt 0 view .LVU201
 664 000e 0383     		strh	r3, [r0, #24]
 159:Library/src/lcm32f06x_acmp.c **** 
 665              		.loc 1 159 3 is_stmt 1 view .LVU202
 159:Library/src/lcm32f06x_acmp.c **** 
 666              		.loc 1 159 36 is_stmt 0 view .LVU203
 667 0010 C361     		str	r3, [r0, #28]
 161:Library/src/lcm32f06x_acmp.c **** 
 668              		.loc 1 161 3 is_stmt 1 view .LVU204
 161:Library/src/lcm32f06x_acmp.c **** 
 669              		.loc 1 161 28 is_stmt 0 view .LVU205
 670 0012 0362     		str	r3, [r0, #32]
 163:Library/src/lcm32f06x_acmp.c **** 
 671              		.loc 1 163 3 is_stmt 1 view .LVU206
 165:Library/src/lcm32f06x_acmp.c **** 
 672              		.loc 1 165 3 view .LVU207
 163:Library/src/lcm32f06x_acmp.c **** 
 673              		.loc 1 163 31 is_stmt 0 view .LVU208
 674 0014 8384     		strh	r3, [r0, #36]
 167:Library/src/lcm32f06x_acmp.c **** 
 675              		.loc 1 167 3 is_stmt 1 view .LVU209
 167:Library/src/lcm32f06x_acmp.c **** 
 676              		.loc 1 167 30 is_stmt 0 view .LVU210
 677 0016 8362     		str	r3, [r0, #40]
 169:Library/src/lcm32f06x_acmp.c **** 
 678              		.loc 1 169 3 is_stmt 1 view .LVU211
 169:Library/src/lcm32f06x_acmp.c **** 
 679              		.loc 1 169 36 is_stmt 0 view .LVU212
 680 0018 C362     		str	r3, [r0, #44]
 171:Library/src/lcm32f06x_acmp.c **** 
 681              		.loc 1 171 3 is_stmt 1 view .LVU213
 171:Library/src/lcm32f06x_acmp.c **** 
 682              		.loc 1 171 35 is_stmt 0 view .LVU214
 683 001a 0363     		str	r3, [r0, #48]
 173:Library/src/lcm32f06x_acmp.c **** 
 684              		.loc 1 173 3 is_stmt 1 view .LVU215
ARM GAS  /tmp/ccQ8FEb0.s 			page 39


 173:Library/src/lcm32f06x_acmp.c **** 
 685              		.loc 1 173 32 is_stmt 0 view .LVU216
 686 001c 4363     		str	r3, [r0, #52]
 175:Library/src/lcm32f06x_acmp.c **** };
 687              		.loc 1 175 3 is_stmt 1 view .LVU217
 175:Library/src/lcm32f06x_acmp.c **** };
 688              		.loc 1 175 29 is_stmt 0 view .LVU218
 689 001e 8363     		str	r3, [r0, #56]
 690              		.loc 1 176 1 view .LVU219
 691 0020 7047     		bx	lr
 692              		.cfi_endproc
 693              	.LFE48:
 695 0022 C046     		.section	.text.ACMP0_SoftWareTrigger,"ax",%progbits
 696              		.align	1
 697              		.p2align 2,,3
 698              		.global	ACMP0_SoftWareTrigger
 699              		.syntax unified
 700              		.code	16
 701              		.thumb_func
 703              	ACMP0_SoftWareTrigger:
 704              	.LFB49:
 177:Library/src/lcm32f06x_acmp.c **** 
 178:Library/src/lcm32f06x_acmp.c **** /**
 179:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_SoftWareTrigger
 180:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 software triggers conversion.
 181:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 软件触发转换。
 182:Library/src/lcm32f06x_acmp.c ****   * @retval None
 183:Library/src/lcm32f06x_acmp.c ****   */
 184:Library/src/lcm32f06x_acmp.c **** void ACMP0_SoftWareTrigger(void)
 185:Library/src/lcm32f06x_acmp.c **** {
 705              		.loc 1 185 1 is_stmt 1 view -0
 706              		.cfi_startproc
 707              		@ args = 0, pretend = 0, frame = 0
 708              		@ frame_needed = 0, uses_anonymous_args = 0
 709              		@ link register save eliminated.
 186:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 710              		.loc 1 186 3 view .LVU221
 711              		.loc 1 186 7 is_stmt 0 view .LVU222
 712 0000 C022     		movs	r2, #192
 187:Library/src/lcm32f06x_acmp.c **** }
 713              		.loc 1 187 1 view .LVU223
 714              		@ sp needed
 186:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 715              		.loc 1 186 22 view .LVU224
 716 0002 0120     		movs	r0, #1
 186:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 717              		.loc 1 186 7 view .LVU225
 718 0004 0249     		ldr	r1, .L11
 719 0006 8B58     		ldr	r3, [r1, r2]
 186:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 720              		.loc 1 186 22 view .LVU226
 721 0008 0343     		orrs	r3, r0
 722 000a 8B50     		str	r3, [r1, r2]
 723              		.loc 1 187 1 view .LVU227
 724 000c 7047     		bx	lr
 725              	.L12:
 726 000e C046     		.align	2
ARM GAS  /tmp/ccQ8FEb0.s 			page 40


 727              	.L11:
 728 0010 007C0140 		.word	1073839104
 729              		.cfi_endproc
 730              	.LFE49:
 732              		.section	.text.ACMP1_SoftWareTrigger,"ax",%progbits
 733              		.align	1
 734              		.p2align 2,,3
 735              		.global	ACMP1_SoftWareTrigger
 736              		.syntax unified
 737              		.code	16
 738              		.thumb_func
 740              	ACMP1_SoftWareTrigger:
 741              	.LFB50:
 188:Library/src/lcm32f06x_acmp.c **** 
 189:Library/src/lcm32f06x_acmp.c **** /**
 190:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_SoftWareTrigger
 191:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 software triggers conversion.
 192:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 软件触发转换。
 193:Library/src/lcm32f06x_acmp.c ****   * @retval None
 194:Library/src/lcm32f06x_acmp.c ****   */
 195:Library/src/lcm32f06x_acmp.c **** void ACMP1_SoftWareTrigger(void)
 196:Library/src/lcm32f06x_acmp.c **** {
 742              		.loc 1 196 1 is_stmt 1 view -0
 743              		.cfi_startproc
 744              		@ args = 0, pretend = 0, frame = 0
 745              		@ frame_needed = 0, uses_anonymous_args = 0
 746              		@ link register save eliminated.
 197:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 747              		.loc 1 197 3 view .LVU229
 748              		.loc 1 197 7 is_stmt 0 view .LVU230
 749 0000 C822     		movs	r2, #200
 198:Library/src/lcm32f06x_acmp.c **** }
 750              		.loc 1 198 1 view .LVU231
 751              		@ sp needed
 197:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 752              		.loc 1 197 22 view .LVU232
 753 0002 0120     		movs	r0, #1
 197:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 754              		.loc 1 197 7 view .LVU233
 755 0004 0249     		ldr	r1, .L14
 756 0006 8B58     		ldr	r3, [r1, r2]
 197:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_MUXCSR |= ANACTRL_ACMPX_MUXCSR_CMP_SEQ_START_Msk;
 757              		.loc 1 197 22 view .LVU234
 758 0008 0343     		orrs	r3, r0
 759 000a 8B50     		str	r3, [r1, r2]
 760              		.loc 1 198 1 view .LVU235
 761 000c 7047     		bx	lr
 762              	.L15:
 763 000e C046     		.align	2
 764              	.L14:
 765 0010 007C0140 		.word	1073839104
 766              		.cfi_endproc
 767              	.LFE50:
 769              		.section	.text.GET_ACMP0_SEQ_RESLUT,"ax",%progbits
 770              		.align	1
 771              		.p2align 2,,3
 772              		.global	GET_ACMP0_SEQ_RESLUT
ARM GAS  /tmp/ccQ8FEb0.s 			page 41


 773              		.syntax unified
 774              		.code	16
 775              		.thumb_func
 777              	GET_ACMP0_SEQ_RESLUT:
 778              	.LFB51:
 199:Library/src/lcm32f06x_acmp.c **** 
 200:Library/src/lcm32f06x_acmp.c **** /**
 201:Library/src/lcm32f06x_acmp.c ****   * @name   GET_ACMP0_SEQ_RESLUT
 202:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: get the results of continuous compare.
 203:Library/src/lcm32f06x_acmp.c ****   *         CN: 获取连续比较的结果 ACMP0。
 204:Library/src/lcm32f06x_acmp.c ****   * @retval uint32_t
 205:Library/src/lcm32f06x_acmp.c ****   */
 206:Library/src/lcm32f06x_acmp.c **** uint32_t GET_ACMP0_SEQ_RESLUT(void)
 207:Library/src/lcm32f06x_acmp.c **** {
 779              		.loc 1 207 1 is_stmt 1 view -0
 780              		.cfi_startproc
 781              		@ args = 0, pretend = 0, frame = 0
 782              		@ frame_needed = 0, uses_anonymous_args = 0
 783              		@ link register save eliminated.
 208:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 784              		.loc 1 208 3 view .LVU237
 785              		.loc 1 208 16 is_stmt 0 view .LVU238
 786 0000 C023     		movs	r3, #192
 209:Library/src/lcm32f06x_acmp.c **** }
 787              		.loc 1 209 1 view .LVU239
 788              		@ sp needed
 208:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 789              		.loc 1 208 16 view .LVU240
 790 0002 024A     		ldr	r2, .L17
 791 0004 D058     		ldr	r0, [r2, r3]
 208:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 792              		.loc 1 208 69 view .LVU241
 793 0006 0004     		lsls	r0, r0, #16
 794 0008 000E     		lsrs	r0, r0, #24
 795              		.loc 1 209 1 view .LVU242
 796 000a 7047     		bx	lr
 797              	.L18:
 798              		.align	2
 799              	.L17:
 800 000c 007C0140 		.word	1073839104
 801              		.cfi_endproc
 802              	.LFE51:
 804              		.section	.text.GET_ACMP1_SEQ_RESLUT,"ax",%progbits
 805              		.align	1
 806              		.p2align 2,,3
 807              		.global	GET_ACMP1_SEQ_RESLUT
 808              		.syntax unified
 809              		.code	16
 810              		.thumb_func
 812              	GET_ACMP1_SEQ_RESLUT:
 813              	.LFB52:
 210:Library/src/lcm32f06x_acmp.c **** /**
 211:Library/src/lcm32f06x_acmp.c ****   * @name   GET_ACMP1_SEQ_RESLUT
 212:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: get the results of continuous compare.
 213:Library/src/lcm32f06x_acmp.c ****   *         CN: 获取连续比较的结果 ACMP1。
 214:Library/src/lcm32f06x_acmp.c ****   * @retval uint32_t
 215:Library/src/lcm32f06x_acmp.c ****   */
ARM GAS  /tmp/ccQ8FEb0.s 			page 42


 216:Library/src/lcm32f06x_acmp.c **** uint32_t GET_ACMP1_SEQ_RESLUT(void)
 217:Library/src/lcm32f06x_acmp.c **** {
 814              		.loc 1 217 1 is_stmt 1 view -0
 815              		.cfi_startproc
 816              		@ args = 0, pretend = 0, frame = 0
 817              		@ frame_needed = 0, uses_anonymous_args = 0
 818              		@ link register save eliminated.
 218:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 819              		.loc 1 218 3 view .LVU244
 820              		.loc 1 218 16 is_stmt 0 view .LVU245
 821 0000 C823     		movs	r3, #200
 219:Library/src/lcm32f06x_acmp.c **** }
 822              		.loc 1 219 1 view .LVU246
 823              		@ sp needed
 218:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 824              		.loc 1 218 16 view .LVU247
 825 0002 024A     		ldr	r2, .L20
 826 0004 D058     		ldr	r0, [r2, r3]
 218:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_MUXCSR & ANACTRL_ACMPX_MUXCSR_CPOUT_SEQ_Msk) >> ANACTRL_ACMPX_MUXCSR_CPOUT_S
 827              		.loc 1 218 69 view .LVU248
 828 0006 0004     		lsls	r0, r0, #16
 829 0008 000E     		lsrs	r0, r0, #24
 830              		.loc 1 219 1 view .LVU249
 831 000a 7047     		bx	lr
 832              	.L21:
 833              		.align	2
 834              	.L20:
 835 000c 007C0140 		.word	1073839104
 836              		.cfi_endproc
 837              	.LFE52:
 839              		.section	.text.ACMP0_Cmd,"ax",%progbits
 840              		.align	1
 841              		.p2align 2,,3
 842              		.global	ACMP0_Cmd
 843              		.syntax unified
 844              		.code	16
 845              		.thumb_func
 847              	ACMP0_Cmd:
 848              	.LVL38:
 849              	.LFB53:
 220:Library/src/lcm32f06x_acmp.c **** 
 221:Library/src/lcm32f06x_acmp.c **** /**
 222:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_Cmd
 223:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Enables or disables the specified ACMP0 peripheral.
 224:Library/src/lcm32f06x_acmp.c ****   *         CN: 启用或禁用指定的 ACMP0 外设。
 225:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 226:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the ACMP0 peripheral.
 227:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 外设的新状态。
 228:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 229:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 230:Library/src/lcm32f06x_acmp.c ****   * @retval None
 231:Library/src/lcm32f06x_acmp.c ****   */
 232:Library/src/lcm32f06x_acmp.c **** void ACMP0_Cmd(FunctionalState NewState)
 233:Library/src/lcm32f06x_acmp.c **** {
 850              		.loc 1 233 1 is_stmt 1 view -0
 851              		.cfi_startproc
 852              		@ args = 0, pretend = 0, frame = 0
ARM GAS  /tmp/ccQ8FEb0.s 			page 43


 853              		@ frame_needed = 0, uses_anonymous_args = 0
 854              		@ link register save eliminated.
 234:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 855              		.loc 1 234 3 view .LVU251
 235:Library/src/lcm32f06x_acmp.c ****   {
 236:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP0_CSR |= (ANACTRL_ACMPX_CSR_CP_EN_Msk);
 856              		.loc 1 236 9 is_stmt 0 view .LVU252
 857 0000 054A     		ldr	r2, .L25
 858              		.loc 1 236 21 view .LVU253
 859 0002 0121     		movs	r1, #1
 860              		.loc 1 236 9 view .LVU254
 861 0004 136A     		ldr	r3, [r2, #32]
 234:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 862              		.loc 1 234 6 view .LVU255
 863 0006 0028     		cmp	r0, #0
 864 0008 02D0     		beq	.L23
 865              		.loc 1 236 5 is_stmt 1 view .LVU256
 866              		.loc 1 236 21 is_stmt 0 view .LVU257
 867 000a 0B43     		orrs	r3, r1
 868 000c 1362     		str	r3, [r2, #32]
 869              	.L22:
 237:Library/src/lcm32f06x_acmp.c ****   }
 238:Library/src/lcm32f06x_acmp.c ****   else
 239:Library/src/lcm32f06x_acmp.c ****   {
 240:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP0_CSR &= (~(ANACTRL_ACMPX_CSR_CP_EN_Msk));
 241:Library/src/lcm32f06x_acmp.c ****   }
 242:Library/src/lcm32f06x_acmp.c **** }
 870              		.loc 1 242 1 view .LVU258
 871              		@ sp needed
 872 000e 7047     		bx	lr
 873              	.L23:
 240:Library/src/lcm32f06x_acmp.c ****   }
 874              		.loc 1 240 5 is_stmt 1 view .LVU259
 240:Library/src/lcm32f06x_acmp.c ****   }
 875              		.loc 1 240 21 is_stmt 0 view .LVU260
 876 0010 8B43     		bics	r3, r1
 877 0012 1362     		str	r3, [r2, #32]
 878              		.loc 1 242 1 view .LVU261
 879 0014 FBE7     		b	.L22
 880              	.L26:
 881 0016 C046     		.align	2
 882              	.L25:
 883 0018 007C0140 		.word	1073839104
 884              		.cfi_endproc
 885              	.LFE53:
 887              		.section	.text.ACMP1_Cmd,"ax",%progbits
 888              		.align	1
 889              		.p2align 2,,3
 890              		.global	ACMP1_Cmd
 891              		.syntax unified
 892              		.code	16
 893              		.thumb_func
 895              	ACMP1_Cmd:
 896              	.LVL39:
 897              	.LFB54:
 243:Library/src/lcm32f06x_acmp.c **** 
 244:Library/src/lcm32f06x_acmp.c **** /**
ARM GAS  /tmp/ccQ8FEb0.s 			page 44


 245:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_Cmd
 246:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Enables or disables the specified ACMP1 peripheral.
 247:Library/src/lcm32f06x_acmp.c ****   *         CN: 启用或禁用指定的 ACMP1 外设。
 248:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 249:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the ACMP1 peripheral.
 250:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 外设的新状态。
 251:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 252:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 253:Library/src/lcm32f06x_acmp.c ****   * @retval None
 254:Library/src/lcm32f06x_acmp.c ****   */
 255:Library/src/lcm32f06x_acmp.c **** void ACMP1_Cmd(FunctionalState NewState)
 256:Library/src/lcm32f06x_acmp.c **** {
 898              		.loc 1 256 1 is_stmt 1 view -0
 899              		.cfi_startproc
 900              		@ args = 0, pretend = 0, frame = 0
 901              		@ frame_needed = 0, uses_anonymous_args = 0
 902              		@ link register save eliminated.
 257:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 903              		.loc 1 257 3 view .LVU263
 258:Library/src/lcm32f06x_acmp.c ****   {
 259:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP1_CSR |= (ANACTRL_ACMPX_CSR_CP_EN_Msk);
 904              		.loc 1 259 9 is_stmt 0 view .LVU264
 905 0000 054A     		ldr	r2, .L30
 906              		.loc 1 259 21 view .LVU265
 907 0002 0121     		movs	r1, #1
 908              		.loc 1 259 9 view .LVU266
 909 0004 536A     		ldr	r3, [r2, #36]
 257:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 910              		.loc 1 257 6 view .LVU267
 911 0006 0028     		cmp	r0, #0
 912 0008 02D0     		beq	.L28
 913              		.loc 1 259 5 is_stmt 1 view .LVU268
 914              		.loc 1 259 21 is_stmt 0 view .LVU269
 915 000a 0B43     		orrs	r3, r1
 916 000c 5362     		str	r3, [r2, #36]
 917              	.L27:
 260:Library/src/lcm32f06x_acmp.c ****   }
 261:Library/src/lcm32f06x_acmp.c ****   else
 262:Library/src/lcm32f06x_acmp.c ****   {
 263:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP1_CSR &= (~(ANACTRL_ACMPX_CSR_CP_EN_Msk));
 264:Library/src/lcm32f06x_acmp.c ****   }
 265:Library/src/lcm32f06x_acmp.c **** }
 918              		.loc 1 265 1 view .LVU270
 919              		@ sp needed
 920 000e 7047     		bx	lr
 921              	.L28:
 263:Library/src/lcm32f06x_acmp.c ****   }
 922              		.loc 1 263 5 is_stmt 1 view .LVU271
 263:Library/src/lcm32f06x_acmp.c ****   }
 923              		.loc 1 263 21 is_stmt 0 view .LVU272
 924 0010 8B43     		bics	r3, r1
 925 0012 5362     		str	r3, [r2, #36]
 926              		.loc 1 265 1 view .LVU273
 927 0014 FBE7     		b	.L27
 928              	.L31:
 929 0016 C046     		.align	2
 930              	.L30:
ARM GAS  /tmp/ccQ8FEb0.s 			page 45


 931 0018 007C0140 		.word	1073839104
 932              		.cfi_endproc
 933              	.LFE54:
 935              		.section	.text.ACMP0_FREN_Cmd,"ax",%progbits
 936              		.align	1
 937              		.p2align 2,,3
 938              		.global	ACMP0_FREN_Cmd
 939              		.syntax unified
 940              		.code	16
 941              		.thumb_func
 943              	ACMP0_FREN_Cmd:
 944              	.LVL40:
 945              	.LFB55:
 266:Library/src/lcm32f06x_acmp.c **** 
 267:Library/src/lcm32f06x_acmp.c **** /**
 268:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_FREN_Cmd
 269:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 Quick Response Enable.
 270:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 快速响应使能。
 271:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 272:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the ACMP0 Quick Response.
 273:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 快速响应的新状态
 274:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 275:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 276:Library/src/lcm32f06x_acmp.c ****   * @retval None
 277:Library/src/lcm32f06x_acmp.c ****   */
 278:Library/src/lcm32f06x_acmp.c **** void ACMP0_FREN_Cmd(FunctionalState NewState)
 279:Library/src/lcm32f06x_acmp.c **** {
 946              		.loc 1 279 1 is_stmt 1 view -0
 947              		.cfi_startproc
 948              		@ args = 0, pretend = 0, frame = 0
 949              		@ frame_needed = 0, uses_anonymous_args = 0
 950              		@ link register save eliminated.
 280:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 951              		.loc 1 280 3 view .LVU275
 281:Library/src/lcm32f06x_acmp.c ****   {
 282:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP0_CSR |= (ANACTRL_ACMPX_CSR_CP_FREN_Msk);
 952              		.loc 1 282 9 is_stmt 0 view .LVU276
 953 0000 054A     		ldr	r2, .L35
 954              		.loc 1 282 21 view .LVU277
 955 0002 0221     		movs	r1, #2
 956              		.loc 1 282 9 view .LVU278
 957 0004 136A     		ldr	r3, [r2, #32]
 280:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 958              		.loc 1 280 6 view .LVU279
 959 0006 0028     		cmp	r0, #0
 960 0008 02D0     		beq	.L33
 961              		.loc 1 282 5 is_stmt 1 view .LVU280
 962              		.loc 1 282 21 is_stmt 0 view .LVU281
 963 000a 0B43     		orrs	r3, r1
 964 000c 1362     		str	r3, [r2, #32]
 965              	.L32:
 283:Library/src/lcm32f06x_acmp.c ****   }
 284:Library/src/lcm32f06x_acmp.c ****   else
 285:Library/src/lcm32f06x_acmp.c ****   {
 286:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP0_CSR &= (~(ANACTRL_ACMPX_CSR_CP_FREN_Msk));
 287:Library/src/lcm32f06x_acmp.c ****   }
 288:Library/src/lcm32f06x_acmp.c **** }
ARM GAS  /tmp/ccQ8FEb0.s 			page 46


 966              		.loc 1 288 1 view .LVU282
 967              		@ sp needed
 968 000e 7047     		bx	lr
 969              	.L33:
 286:Library/src/lcm32f06x_acmp.c ****   }
 970              		.loc 1 286 5 is_stmt 1 view .LVU283
 286:Library/src/lcm32f06x_acmp.c ****   }
 971              		.loc 1 286 21 is_stmt 0 view .LVU284
 972 0010 8B43     		bics	r3, r1
 973 0012 1362     		str	r3, [r2, #32]
 974              		.loc 1 288 1 view .LVU285
 975 0014 FBE7     		b	.L32
 976              	.L36:
 977 0016 C046     		.align	2
 978              	.L35:
 979 0018 007C0140 		.word	1073839104
 980              		.cfi_endproc
 981              	.LFE55:
 983              		.section	.text.ACMP1_FREN_Cmd,"ax",%progbits
 984              		.align	1
 985              		.p2align 2,,3
 986              		.global	ACMP1_FREN_Cmd
 987              		.syntax unified
 988              		.code	16
 989              		.thumb_func
 991              	ACMP1_FREN_Cmd:
 992              	.LVL41:
 993              	.LFB56:
 289:Library/src/lcm32f06x_acmp.c **** 
 290:Library/src/lcm32f06x_acmp.c **** /**
 291:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_FREN_Cmd
 292:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 Quick Response Enable.
 293:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 快速响应使能。
 294:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 295:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the ACMP1 Quick Response.
 296:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 快速响应的新状态。
 297:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 298:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 299:Library/src/lcm32f06x_acmp.c ****   * @retval None
 300:Library/src/lcm32f06x_acmp.c ****   */
 301:Library/src/lcm32f06x_acmp.c **** void ACMP1_FREN_Cmd(FunctionalState NewState)
 302:Library/src/lcm32f06x_acmp.c **** {
 994              		.loc 1 302 1 is_stmt 1 view -0
 995              		.cfi_startproc
 996              		@ args = 0, pretend = 0, frame = 0
 997              		@ frame_needed = 0, uses_anonymous_args = 0
 998              		@ link register save eliminated.
 303:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 999              		.loc 1 303 3 view .LVU287
 304:Library/src/lcm32f06x_acmp.c ****   {
 305:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP1_CSR |= (ANACTRL_ACMPX_CSR_CP_FREN_Msk);
 1000              		.loc 1 305 9 is_stmt 0 view .LVU288
 1001 0000 054A     		ldr	r2, .L40
 1002              		.loc 1 305 21 view .LVU289
 1003 0002 0221     		movs	r1, #2
 1004              		.loc 1 305 9 view .LVU290
 1005 0004 536A     		ldr	r3, [r2, #36]
ARM GAS  /tmp/ccQ8FEb0.s 			page 47


 303:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 1006              		.loc 1 303 6 view .LVU291
 1007 0006 0028     		cmp	r0, #0
 1008 0008 02D0     		beq	.L38
 1009              		.loc 1 305 5 is_stmt 1 view .LVU292
 1010              		.loc 1 305 21 is_stmt 0 view .LVU293
 1011 000a 0B43     		orrs	r3, r1
 1012 000c 5362     		str	r3, [r2, #36]
 1013              	.L37:
 306:Library/src/lcm32f06x_acmp.c ****   }
 307:Library/src/lcm32f06x_acmp.c ****   else
 308:Library/src/lcm32f06x_acmp.c ****   {
 309:Library/src/lcm32f06x_acmp.c ****     ACMP->ACMP1_CSR &= (~(ANACTRL_ACMPX_CSR_CP_FREN_Msk));
 310:Library/src/lcm32f06x_acmp.c ****   }
 311:Library/src/lcm32f06x_acmp.c **** }
 1014              		.loc 1 311 1 view .LVU294
 1015              		@ sp needed
 1016 000e 7047     		bx	lr
 1017              	.L38:
 309:Library/src/lcm32f06x_acmp.c ****   }
 1018              		.loc 1 309 5 is_stmt 1 view .LVU295
 309:Library/src/lcm32f06x_acmp.c ****   }
 1019              		.loc 1 309 21 is_stmt 0 view .LVU296
 1020 0010 8B43     		bics	r3, r1
 1021 0012 5362     		str	r3, [r2, #36]
 1022              		.loc 1 311 1 view .LVU297
 1023 0014 FBE7     		b	.L37
 1024              	.L41:
 1025 0016 C046     		.align	2
 1026              	.L40:
 1027 0018 007C0140 		.word	1073839104
 1028              		.cfi_endproc
 1029              	.LFE56:
 1031              		.section	.text.Acmp0_trim,"ax",%progbits
 1032              		.align	1
 1033              		.p2align 2,,3
 1034              		.global	Acmp0_trim
 1035              		.syntax unified
 1036              		.code	16
 1037              		.thumb_func
 1039              	Acmp0_trim:
 1040              	.LVL42:
 1041              	.LFB57:
 312:Library/src/lcm32f06x_acmp.c **** 
 313:Library/src/lcm32f06x_acmp.c **** /**
 314:Library/src/lcm32f06x_acmp.c ****   * @name   Acmp0_trim
 315:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: acmp0 tuning value writing function.
 316:Library/src/lcm32f06x_acmp.c ****   *         CN: acmp0 修调值写入函数。
 317:Library/src/lcm32f06x_acmp.c ****   * @param  trim: 
 318:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP0 adjustment value.
 319:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 修调值。
 320:Library/src/lcm32f06x_acmp.c ****   * @retval None
 321:Library/src/lcm32f06x_acmp.c ****   */
 322:Library/src/lcm32f06x_acmp.c **** void Acmp0_trim(uint8_t trim)
 323:Library/src/lcm32f06x_acmp.c **** {
 1042              		.loc 1 323 1 is_stmt 1 view -0
 1043              		.cfi_startproc
ARM GAS  /tmp/ccQ8FEb0.s 			page 48


 1044              		@ args = 0, pretend = 0, frame = 0
 1045              		@ frame_needed = 0, uses_anonymous_args = 0
 1046              		@ link register save eliminated.
 324:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CSR = ((ACMP->ACMP0_CSR & (~ANACTRL_ACMPX_CSR_CP_PF_Msk)) | (trim << ANACTRL_ACMPX_CS
 1047              		.loc 1 324 3 view .LVU299
 1048              		.loc 1 324 27 is_stmt 0 view .LVU300
 1049 0000 034A     		ldr	r2, .L43
 1050              		.loc 1 324 39 view .LVU301
 1051 0002 0449     		ldr	r1, .L43+4
 1052              		.loc 1 324 27 view .LVU302
 1053 0004 136A     		ldr	r3, [r2, #32]
 1054              		.loc 1 324 81 view .LVU303
 1055 0006 0004     		lsls	r0, r0, #16
 1056              	.LVL43:
 1057              		.loc 1 324 39 view .LVU304
 1058 0008 0B40     		ands	r3, r1
 1059              		.loc 1 324 73 view .LVU305
 1060 000a 0343     		orrs	r3, r0
 1061              		.loc 1 324 19 view .LVU306
 1062 000c 1362     		str	r3, [r2, #32]
 325:Library/src/lcm32f06x_acmp.c **** }
 1063              		.loc 1 325 1 view .LVU307
 1064              		@ sp needed
 1065 000e 7047     		bx	lr
 1066              	.L44:
 1067              		.align	2
 1068              	.L43:
 1069 0010 007C0140 		.word	1073839104
 1070 0014 FFFFE0FF 		.word	-2031617
 1071              		.cfi_endproc
 1072              	.LFE57:
 1074              		.section	.text.Acmp1_trim,"ax",%progbits
 1075              		.align	1
 1076              		.p2align 2,,3
 1077              		.global	Acmp1_trim
 1078              		.syntax unified
 1079              		.code	16
 1080              		.thumb_func
 1082              	Acmp1_trim:
 1083              	.LVL44:
 1084              	.LFB58:
 326:Library/src/lcm32f06x_acmp.c **** 
 327:Library/src/lcm32f06x_acmp.c **** /**
 328:Library/src/lcm32f06x_acmp.c ****   * @name   Acmp1_trim
 329:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: acmp1 tuning value writing function.
 330:Library/src/lcm32f06x_acmp.c ****   *         CN: acmp1 修调值写入函数。
 331:Library/src/lcm32f06x_acmp.c ****   * @param  trim: 
 332:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP1 adjustment value.
 333:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 修调值。
 334:Library/src/lcm32f06x_acmp.c ****   * @retval None
 335:Library/src/lcm32f06x_acmp.c ****   */
 336:Library/src/lcm32f06x_acmp.c **** void Acmp1_trim(uint8_t trim)
 337:Library/src/lcm32f06x_acmp.c **** {
 1085              		.loc 1 337 1 is_stmt 1 view -0
 1086              		.cfi_startproc
 1087              		@ args = 0, pretend = 0, frame = 0
 1088              		@ frame_needed = 0, uses_anonymous_args = 0
ARM GAS  /tmp/ccQ8FEb0.s 			page 49


 1089              		@ link register save eliminated.
 338:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CSR = ((ACMP->ACMP1_CSR & (~ANACTRL_ACMPX_CSR_CP_PF_Msk)) | (trim << ANACTRL_ACMPX_CS
 1090              		.loc 1 338 3 view .LVU309
 1091              		.loc 1 338 27 is_stmt 0 view .LVU310
 1092 0000 034A     		ldr	r2, .L46
 1093              		.loc 1 338 39 view .LVU311
 1094 0002 0449     		ldr	r1, .L46+4
 1095              		.loc 1 338 27 view .LVU312
 1096 0004 536A     		ldr	r3, [r2, #36]
 1097              		.loc 1 338 81 view .LVU313
 1098 0006 0004     		lsls	r0, r0, #16
 1099              	.LVL45:
 1100              		.loc 1 338 39 view .LVU314
 1101 0008 0B40     		ands	r3, r1
 1102              		.loc 1 338 73 view .LVU315
 1103 000a 0343     		orrs	r3, r0
 1104              		.loc 1 338 19 view .LVU316
 1105 000c 5362     		str	r3, [r2, #36]
 339:Library/src/lcm32f06x_acmp.c **** }
 1106              		.loc 1 339 1 view .LVU317
 1107              		@ sp needed
 1108 000e 7047     		bx	lr
 1109              	.L47:
 1110              		.align	2
 1111              	.L46:
 1112 0010 007C0140 		.word	1073839104
 1113 0014 FFFFE0FF 		.word	-2031617
 1114              		.cfi_endproc
 1115              	.LFE58:
 1117              		.section	.text.get_acmp0_trim,"ax",%progbits
 1118              		.align	1
 1119              		.p2align 2,,3
 1120              		.global	get_acmp0_trim
 1121              		.syntax unified
 1122              		.code	16
 1123              		.thumb_func
 1125              	get_acmp0_trim:
 1126              	.LFB59:
 340:Library/src/lcm32f06x_acmp.c **** /**
 341:Library/src/lcm32f06x_acmp.c ****   * @name   get_acmp0_trim
 342:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Reading ACMP0 tuning values and writing functions.
 343:Library/src/lcm32f06x_acmp.c ****   *         CN: 读取 ACMP0 修调值函数。
 344:Library/src/lcm32f06x_acmp.c ****   * @retval uint8_t：
 345:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP0 adjustment value.
 346:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 修调值。
 347:Library/src/lcm32f06x_acmp.c ****   */
 348:Library/src/lcm32f06x_acmp.c **** uint8_t get_acmp0_trim(void)
 349:Library/src/lcm32f06x_acmp.c **** {
 1127              		.loc 1 349 1 is_stmt 1 view -0
 1128              		.cfi_startproc
 1129              		@ args = 0, pretend = 0, frame = 0
 1130              		@ frame_needed = 0, uses_anonymous_args = 0
 1131              		@ link register save eliminated.
 350:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1132              		.loc 1 350 3 view .LVU319
 1133              		.loc 1 350 16 is_stmt 0 view .LVU320
 1134 0000 024B     		ldr	r3, .L49
ARM GAS  /tmp/ccQ8FEb0.s 			page 50


 351:Library/src/lcm32f06x_acmp.c **** }
 1135              		.loc 1 351 1 view .LVU321
 1136              		@ sp needed
 350:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1137              		.loc 1 350 16 view .LVU322
 1138 0002 186A     		ldr	r0, [r3, #32]
 350:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1139              		.loc 1 350 59 view .LVU323
 1140 0004 C002     		lsls	r0, r0, #11
 350:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP0_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1141              		.loc 1 350 59 discriminator 1 view .LVU324
 1142 0006 C00E     		lsrs	r0, r0, #27
 1143              		.loc 1 351 1 view .LVU325
 1144 0008 7047     		bx	lr
 1145              	.L50:
 1146 000a C046     		.align	2
 1147              	.L49:
 1148 000c 007C0140 		.word	1073839104
 1149              		.cfi_endproc
 1150              	.LFE59:
 1152              		.section	.text.get_acmp1_trim,"ax",%progbits
 1153              		.align	1
 1154              		.p2align 2,,3
 1155              		.global	get_acmp1_trim
 1156              		.syntax unified
 1157              		.code	16
 1158              		.thumb_func
 1160              	get_acmp1_trim:
 1161              	.LFB60:
 352:Library/src/lcm32f06x_acmp.c **** 
 353:Library/src/lcm32f06x_acmp.c **** /**
 354:Library/src/lcm32f06x_acmp.c ****   * @name   get_acmp1_trim
 355:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Reading ACMP1 tuning values and writing functions.
 356:Library/src/lcm32f06x_acmp.c ****   *         CN: 读取 ACMP1 修调值函数。
 357:Library/src/lcm32f06x_acmp.c ****   * @retval uint8_t：
 358:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP1 adjustment value.
 359:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 修调值。
 360:Library/src/lcm32f06x_acmp.c ****   */
 361:Library/src/lcm32f06x_acmp.c **** uint8_t get_acmp1_trim(void)
 362:Library/src/lcm32f06x_acmp.c **** {
 1162              		.loc 1 362 1 is_stmt 1 view -0
 1163              		.cfi_startproc
 1164              		@ args = 0, pretend = 0, frame = 0
 1165              		@ frame_needed = 0, uses_anonymous_args = 0
 1166              		@ link register save eliminated.
 363:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1167              		.loc 1 363 3 view .LVU327
 1168              		.loc 1 363 16 is_stmt 0 view .LVU328
 1169 0000 024B     		ldr	r3, .L52
 364:Library/src/lcm32f06x_acmp.c **** }
 1170              		.loc 1 364 1 view .LVU329
 1171              		@ sp needed
 363:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1172              		.loc 1 363 16 view .LVU330
 1173 0002 586A     		ldr	r0, [r3, #36]
 363:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1174              		.loc 1 363 59 view .LVU331
ARM GAS  /tmp/ccQ8FEb0.s 			page 51


 1175 0004 C002     		lsls	r0, r0, #11
 363:Library/src/lcm32f06x_acmp.c ****   return ((ACMP->ACMP1_CSR & ANACTRL_ACMPX_CSR_CP_PF_Msk) >> ANACTRL_ACMPX_CSR_CP_PF_Pos);
 1176              		.loc 1 363 59 discriminator 1 view .LVU332
 1177 0006 C00E     		lsrs	r0, r0, #27
 1178              		.loc 1 364 1 view .LVU333
 1179 0008 7047     		bx	lr
 1180              	.L53:
 1181 000a C046     		.align	2
 1182              	.L52:
 1183 000c 007C0140 		.word	1073839104
 1184              		.cfi_endproc
 1185              	.LFE60:
 1187              		.section	.text.ACMP0_TrimInit,"ax",%progbits
 1188              		.align	1
 1189              		.p2align 2,,3
 1190              		.global	ACMP0_TrimInit
 1191              		.syntax unified
 1192              		.code	16
 1193              		.thumb_func
 1195              	ACMP0_TrimInit:
 1196              	.LFB61:
 365:Library/src/lcm32f06x_acmp.c **** 
 366:Library/src/lcm32f06x_acmp.c **** 
 367:Library/src/lcm32f06x_acmp.c **** /**
 368:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_TrimInit
 369:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 calibration function.
 370:Library/src/lcm32f06x_acmp.c ****   *         CN: 比较器0校准函数。
 371:Library/src/lcm32f06x_acmp.c ****   * @retval None
 372:Library/src/lcm32f06x_acmp.c ****   */
 373:Library/src/lcm32f06x_acmp.c **** void ACMP0_TrimInit(void)
 374:Library/src/lcm32f06x_acmp.c **** {
 1197              		.loc 1 374 1 is_stmt 1 view -0
 1198              		.cfi_startproc
 1199              		@ args = 0, pretend = 0, frame = 0
 1200              		@ frame_needed = 0, uses_anonymous_args = 0
 375:Library/src/lcm32f06x_acmp.c ****   uint8_t cptrim = 0x00;
 1201              		.loc 1 375 3 view .LVU335
 1202              	.LVL46:
 376:Library/src/lcm32f06x_acmp.c ****   unsigned char tmpregs = 0;
 1203              		.loc 1 376 3 view .LVU336
 377:Library/src/lcm32f06x_acmp.c ****   unsigned char flag = 0;
 1204              		.loc 1 377 3 view .LVU337
 378:Library/src/lcm32f06x_acmp.c **** 
 379:Library/src/lcm32f06x_acmp.c ****   tmpregs = ((ACMP->ACMP0_CSR) >> 28) & 0x01;
 1205              		.loc 1 379 3 view .LVU338
 1206              		.loc 1 379 19 is_stmt 0 view .LVU339
 1207 0000 1149     		ldr	r1, .L61
 1208              		.loc 1 379 11 view .LVU340
 1209 0002 0122     		movs	r2, #1
 1210              		.loc 1 379 19 view .LVU341
 1211 0004 0B6A     		ldr	r3, [r1, #32]
 1212              	.LVL47:
 380:Library/src/lcm32f06x_acmp.c **** 
 381:Library/src/lcm32f06x_acmp.c ****   if (tmpregs == 0)
 1213              		.loc 1 381 3 is_stmt 1 view .LVU342
 374:Library/src/lcm32f06x_acmp.c ****   uint8_t cptrim = 0x00;
 1214              		.loc 1 374 1 is_stmt 0 view .LVU343
ARM GAS  /tmp/ccQ8FEb0.s 			page 52


 1215 0006 30B5     		push	{r4, r5, lr}
 1216              	.LCFI5:
 1217              		.cfi_def_cfa_offset 12
 1218              		.cfi_offset 4, -12
 1219              		.cfi_offset 5, -8
 1220              		.cfi_offset 14, -4
 1221              		.loc 1 381 6 view .LVU344
 1222 0008 DB00     		lsls	r3, r3, #3
 1223 000a 1BD4     		bmi	.L54
 1224              	.LVL48:
 382:Library/src/lcm32f06x_acmp.c ****   {
 383:Library/src/lcm32f06x_acmp.c ****     while (flag != 1)
 1225              		.loc 1 383 17 is_stmt 1 view .LVU345
 384:Library/src/lcm32f06x_acmp.c ****     {
 385:Library/src/lcm32f06x_acmp.c ****       Acmp0_trim(cptrim);
 1226              		.loc 1 385 7 view .LVU346
 1227              	.LBB70:
 1228              	.LBI70:
 322:Library/src/lcm32f06x_acmp.c **** {
 1229              		.loc 1 322 6 view .LVU347
 1230              	.LBB71:
 324:Library/src/lcm32f06x_acmp.c **** }
 1231              		.loc 1 324 3 view .LVU348
 324:Library/src/lcm32f06x_acmp.c **** }
 1232              		.loc 1 324 27 is_stmt 0 view .LVU349
 1233 000c 0B6A     		ldr	r3, [r1, #32]
 324:Library/src/lcm32f06x_acmp.c **** }
 1234              		.loc 1 324 39 view .LVU350
 1235 000e 0F48     		ldr	r0, .L61+4
 1236 0010 0340     		ands	r3, r0
 324:Library/src/lcm32f06x_acmp.c **** }
 1237              		.loc 1 324 19 view .LVU351
 1238 0012 0B62     		str	r3, [r1, #32]
 1239              	.LVL49:
 324:Library/src/lcm32f06x_acmp.c **** }
 1240              		.loc 1 324 19 view .LVU352
 1241              	.LBE71:
 1242              	.LBE70:
 386:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP0_CSR) >> 28) & 0x01;
 1243              		.loc 1 386 7 is_stmt 1 view .LVU353
 1244              		.loc 1 386 23 is_stmt 0 view .LVU354
 1245 0014 0B6A     		ldr	r3, [r1, #32]
 1246              	.LVL50:
 387:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1247              		.loc 1 387 7 is_stmt 1 view .LVU355
 386:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP0_CSR) >> 28) & 0x01;
 1248              		.loc 1 386 36 is_stmt 0 view .LVU356
 1249 0016 1B0F     		lsrs	r3, r3, #28
 1250              	.LVL51:
 1251              		.loc 1 387 10 view .LVU357
 1252 0018 1A42     		tst	r2, r3
 1253 001a 13D1     		bne	.L54
 1254 001c 8022     		movs	r2, #128
 1255 001e 8024     		movs	r4, #128
 388:Library/src/lcm32f06x_acmp.c ****       {
 389:Library/src/lcm32f06x_acmp.c ****         flag = 1;
 390:Library/src/lcm32f06x_acmp.c ****       }
ARM GAS  /tmp/ccQ8FEb0.s 			page 53


 391:Library/src/lcm32f06x_acmp.c ****       else if (cptrim == 0x1f)
 1256              		.loc 1 391 15 view .LVU358
 1257 0020 8025     		movs	r5, #128
 387:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1258              		.loc 1 387 10 view .LVU359
 1259 0022 5202     		lsls	r2, r2, #9
 1260 0024 6405     		lsls	r4, r4, #21
 1261              		.loc 1 391 15 view .LVU360
 1262 0026 AD03     		lsls	r5, r5, #14
 1263 0028 05E0     		b	.L57
 1264              	.LVL52:
 1265              	.L59:
 1266              		.loc 1 391 12 is_stmt 1 view .LVU361
 1267              		.loc 1 391 15 is_stmt 0 view .LVU362
 1268 002a 8023     		movs	r3, #128
 1269              	.LVL53:
 1270              		.loc 1 391 15 view .LVU363
 1271 002c 5B02     		lsls	r3, r3, #9
 1272 002e 9C46     		mov	ip, r3
 1273 0030 6244     		add	r2, r2, ip
 1274              	.LVL54:
 1275              		.loc 1 391 15 view .LVU364
 1276 0032 AA42     		cmp	r2, r5
 1277 0034 06D0     		beq	.L54
 1278              	.LVL55:
 1279              	.L57:
 392:Library/src/lcm32f06x_acmp.c ****       {
 393:Library/src/lcm32f06x_acmp.c ****         flag = 1;
 394:Library/src/lcm32f06x_acmp.c ****       }
 395:Library/src/lcm32f06x_acmp.c ****       else
 396:Library/src/lcm32f06x_acmp.c ****       {
 397:Library/src/lcm32f06x_acmp.c ****         cptrim++;
 1280              		.loc 1 397 9 is_stmt 1 view .LVU365
 383:Library/src/lcm32f06x_acmp.c ****     {
 1281              		.loc 1 383 17 view .LVU366
 385:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP0_CSR) >> 28) & 0x01;
 1282              		.loc 1 385 7 view .LVU367
 1283              	.LBB73:
 322:Library/src/lcm32f06x_acmp.c **** {
 1284              		.loc 1 322 6 view .LVU368
 1285              	.LBB72:
 324:Library/src/lcm32f06x_acmp.c **** }
 1286              		.loc 1 324 3 view .LVU369
 324:Library/src/lcm32f06x_acmp.c **** }
 1287              		.loc 1 324 27 is_stmt 0 view .LVU370
 1288 0036 0B6A     		ldr	r3, [r1, #32]
 324:Library/src/lcm32f06x_acmp.c **** }
 1289              		.loc 1 324 39 view .LVU371
 1290 0038 0340     		ands	r3, r0
 324:Library/src/lcm32f06x_acmp.c **** }
 1291              		.loc 1 324 73 view .LVU372
 1292 003a 1343     		orrs	r3, r2
 324:Library/src/lcm32f06x_acmp.c **** }
 1293              		.loc 1 324 19 view .LVU373
 1294 003c 0B62     		str	r3, [r1, #32]
 1295              	.LVL56:
 324:Library/src/lcm32f06x_acmp.c **** }
ARM GAS  /tmp/ccQ8FEb0.s 			page 54


 1296              		.loc 1 324 19 view .LVU374
 1297              	.LBE72:
 1298              	.LBE73:
 386:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1299              		.loc 1 386 7 is_stmt 1 view .LVU375
 386:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1300              		.loc 1 386 23 is_stmt 0 view .LVU376
 1301 003e 0B6A     		ldr	r3, [r1, #32]
 1302              	.LVL57:
 387:Library/src/lcm32f06x_acmp.c ****       {
 1303              		.loc 1 387 7 is_stmt 1 view .LVU377
 387:Library/src/lcm32f06x_acmp.c ****       {
 1304              		.loc 1 387 10 is_stmt 0 view .LVU378
 1305 0040 2342     		tst	r3, r4
 1306 0042 F2D0     		beq	.L59
 1307              	.LVL58:
 1308              	.L54:
 398:Library/src/lcm32f06x_acmp.c ****       }
 399:Library/src/lcm32f06x_acmp.c ****     }
 400:Library/src/lcm32f06x_acmp.c ****   }
 401:Library/src/lcm32f06x_acmp.c **** }
 1309              		.loc 1 401 1 view .LVU379
 1310              		@ sp needed
 1311 0044 30BD     		pop	{r4, r5, pc}
 1312              	.L62:
 1313 0046 C046     		.align	2
 1314              	.L61:
 1315 0048 007C0140 		.word	1073839104
 1316 004c FFFFE0FF 		.word	-2031617
 1317              		.cfi_endproc
 1318              	.LFE61:
 1320              		.section	.text.ACMP1_TrimInit,"ax",%progbits
 1321              		.align	1
 1322              		.p2align 2,,3
 1323              		.global	ACMP1_TrimInit
 1324              		.syntax unified
 1325              		.code	16
 1326              		.thumb_func
 1328              	ACMP1_TrimInit:
 1329              	.LFB62:
 402:Library/src/lcm32f06x_acmp.c **** 
 403:Library/src/lcm32f06x_acmp.c **** /**
 404:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_TrimInit
 405:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 calibration function.
 406:Library/src/lcm32f06x_acmp.c ****   *         CN: 比较器1校准函数。
 407:Library/src/lcm32f06x_acmp.c ****   * @retval None
 408:Library/src/lcm32f06x_acmp.c ****   */
 409:Library/src/lcm32f06x_acmp.c **** void ACMP1_TrimInit(void)
 410:Library/src/lcm32f06x_acmp.c **** {
 1330              		.loc 1 410 1 is_stmt 1 view -0
 1331              		.cfi_startproc
 1332              		@ args = 0, pretend = 0, frame = 0
 1333              		@ frame_needed = 0, uses_anonymous_args = 0
 411:Library/src/lcm32f06x_acmp.c ****   uint8_t cptrim = 0x00;
 1334              		.loc 1 411 3 view .LVU381
 1335              	.LVL59:
 412:Library/src/lcm32f06x_acmp.c ****   unsigned char tmpregs = 0;
ARM GAS  /tmp/ccQ8FEb0.s 			page 55


 1336              		.loc 1 412 3 view .LVU382
 413:Library/src/lcm32f06x_acmp.c ****   unsigned char flag = 0;
 1337              		.loc 1 413 3 view .LVU383
 414:Library/src/lcm32f06x_acmp.c **** 
 415:Library/src/lcm32f06x_acmp.c ****   tmpregs = ((ACMP->ACMP1_CSR) >> 28) & 0x01;
 1338              		.loc 1 415 3 view .LVU384
 1339              		.loc 1 415 19 is_stmt 0 view .LVU385
 1340 0000 1149     		ldr	r1, .L70
 1341              		.loc 1 415 11 view .LVU386
 1342 0002 0122     		movs	r2, #1
 1343              		.loc 1 415 19 view .LVU387
 1344 0004 4B6A     		ldr	r3, [r1, #36]
 1345              	.LVL60:
 416:Library/src/lcm32f06x_acmp.c **** 
 417:Library/src/lcm32f06x_acmp.c ****   if (tmpregs == 0)
 1346              		.loc 1 417 3 is_stmt 1 view .LVU388
 410:Library/src/lcm32f06x_acmp.c ****   uint8_t cptrim = 0x00;
 1347              		.loc 1 410 1 is_stmt 0 view .LVU389
 1348 0006 30B5     		push	{r4, r5, lr}
 1349              	.LCFI6:
 1350              		.cfi_def_cfa_offset 12
 1351              		.cfi_offset 4, -12
 1352              		.cfi_offset 5, -8
 1353              		.cfi_offset 14, -4
 1354              		.loc 1 417 6 view .LVU390
 1355 0008 DB00     		lsls	r3, r3, #3
 1356 000a 1BD4     		bmi	.L63
 1357              	.LVL61:
 418:Library/src/lcm32f06x_acmp.c ****   {
 419:Library/src/lcm32f06x_acmp.c ****     while (flag != 1)
 1358              		.loc 1 419 17 is_stmt 1 view .LVU391
 420:Library/src/lcm32f06x_acmp.c ****     {
 421:Library/src/lcm32f06x_acmp.c ****       Acmp1_trim(cptrim);
 1359              		.loc 1 421 7 view .LVU392
 1360              	.LBB74:
 1361              	.LBI74:
 336:Library/src/lcm32f06x_acmp.c **** {
 1362              		.loc 1 336 6 view .LVU393
 1363              	.LBB75:
 338:Library/src/lcm32f06x_acmp.c **** }
 1364              		.loc 1 338 3 view .LVU394
 338:Library/src/lcm32f06x_acmp.c **** }
 1365              		.loc 1 338 27 is_stmt 0 view .LVU395
 1366 000c 4B6A     		ldr	r3, [r1, #36]
 338:Library/src/lcm32f06x_acmp.c **** }
 1367              		.loc 1 338 39 view .LVU396
 1368 000e 0F48     		ldr	r0, .L70+4
 1369 0010 0340     		ands	r3, r0
 338:Library/src/lcm32f06x_acmp.c **** }
 1370              		.loc 1 338 19 view .LVU397
 1371 0012 4B62     		str	r3, [r1, #36]
 1372              	.LVL62:
 338:Library/src/lcm32f06x_acmp.c **** }
 1373              		.loc 1 338 19 view .LVU398
 1374              	.LBE75:
 1375              	.LBE74:
 422:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP1_CSR) >> 28) & 0x01;
ARM GAS  /tmp/ccQ8FEb0.s 			page 56


 1376              		.loc 1 422 7 is_stmt 1 view .LVU399
 1377              		.loc 1 422 23 is_stmt 0 view .LVU400
 1378 0014 4B6A     		ldr	r3, [r1, #36]
 1379              	.LVL63:
 423:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1380              		.loc 1 423 7 is_stmt 1 view .LVU401
 422:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP1_CSR) >> 28) & 0x01;
 1381              		.loc 1 422 36 is_stmt 0 view .LVU402
 1382 0016 1B0F     		lsrs	r3, r3, #28
 1383              	.LVL64:
 1384              		.loc 1 423 10 view .LVU403
 1385 0018 1A42     		tst	r2, r3
 1386 001a 13D1     		bne	.L63
 1387 001c 8022     		movs	r2, #128
 1388 001e 8024     		movs	r4, #128
 424:Library/src/lcm32f06x_acmp.c ****       {
 425:Library/src/lcm32f06x_acmp.c ****         flag = 1;
 426:Library/src/lcm32f06x_acmp.c ****       }
 427:Library/src/lcm32f06x_acmp.c ****       else if (cptrim == 0x1f)
 1389              		.loc 1 427 15 view .LVU404
 1390 0020 8025     		movs	r5, #128
 423:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1391              		.loc 1 423 10 view .LVU405
 1392 0022 5202     		lsls	r2, r2, #9
 1393 0024 6405     		lsls	r4, r4, #21
 1394              		.loc 1 427 15 view .LVU406
 1395 0026 AD03     		lsls	r5, r5, #14
 1396 0028 05E0     		b	.L66
 1397              	.LVL65:
 1398              	.L68:
 1399              		.loc 1 427 12 is_stmt 1 view .LVU407
 1400              		.loc 1 427 15 is_stmt 0 view .LVU408
 1401 002a 8023     		movs	r3, #128
 1402              	.LVL66:
 1403              		.loc 1 427 15 view .LVU409
 1404 002c 5B02     		lsls	r3, r3, #9
 1405 002e 9C46     		mov	ip, r3
 1406 0030 6244     		add	r2, r2, ip
 1407              	.LVL67:
 1408              		.loc 1 427 15 view .LVU410
 1409 0032 AA42     		cmp	r2, r5
 1410 0034 06D0     		beq	.L63
 1411              	.LVL68:
 1412              	.L66:
 428:Library/src/lcm32f06x_acmp.c ****       {
 429:Library/src/lcm32f06x_acmp.c ****         flag = 1;
 430:Library/src/lcm32f06x_acmp.c ****       }
 431:Library/src/lcm32f06x_acmp.c ****       else
 432:Library/src/lcm32f06x_acmp.c ****       {
 433:Library/src/lcm32f06x_acmp.c ****         cptrim++;
 1413              		.loc 1 433 9 is_stmt 1 view .LVU411
 419:Library/src/lcm32f06x_acmp.c ****     {
 1414              		.loc 1 419 17 view .LVU412
 421:Library/src/lcm32f06x_acmp.c ****       tmpregs = ((ACMP->ACMP1_CSR) >> 28) & 0x01;
 1415              		.loc 1 421 7 view .LVU413
 1416              	.LBB77:
 336:Library/src/lcm32f06x_acmp.c **** {
ARM GAS  /tmp/ccQ8FEb0.s 			page 57


 1417              		.loc 1 336 6 view .LVU414
 1418              	.LBB76:
 338:Library/src/lcm32f06x_acmp.c **** }
 1419              		.loc 1 338 3 view .LVU415
 338:Library/src/lcm32f06x_acmp.c **** }
 1420              		.loc 1 338 27 is_stmt 0 view .LVU416
 1421 0036 4B6A     		ldr	r3, [r1, #36]
 338:Library/src/lcm32f06x_acmp.c **** }
 1422              		.loc 1 338 39 view .LVU417
 1423 0038 0340     		ands	r3, r0
 338:Library/src/lcm32f06x_acmp.c **** }
 1424              		.loc 1 338 73 view .LVU418
 1425 003a 1343     		orrs	r3, r2
 338:Library/src/lcm32f06x_acmp.c **** }
 1426              		.loc 1 338 19 view .LVU419
 1427 003c 4B62     		str	r3, [r1, #36]
 1428              	.LVL69:
 338:Library/src/lcm32f06x_acmp.c **** }
 1429              		.loc 1 338 19 view .LVU420
 1430              	.LBE76:
 1431              	.LBE77:
 422:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1432              		.loc 1 422 7 is_stmt 1 view .LVU421
 422:Library/src/lcm32f06x_acmp.c ****       if (tmpregs == 1)
 1433              		.loc 1 422 23 is_stmt 0 view .LVU422
 1434 003e 4B6A     		ldr	r3, [r1, #36]
 1435              	.LVL70:
 423:Library/src/lcm32f06x_acmp.c ****       {
 1436              		.loc 1 423 7 is_stmt 1 view .LVU423
 423:Library/src/lcm32f06x_acmp.c ****       {
 1437              		.loc 1 423 10 is_stmt 0 view .LVU424
 1438 0040 2342     		tst	r3, r4
 1439 0042 F2D0     		beq	.L68
 1440              	.LVL71:
 1441              	.L63:
 434:Library/src/lcm32f06x_acmp.c ****       }
 435:Library/src/lcm32f06x_acmp.c ****     }
 436:Library/src/lcm32f06x_acmp.c ****   }
 437:Library/src/lcm32f06x_acmp.c **** }
 1442              		.loc 1 437 1 view .LVU425
 1443              		@ sp needed
 1444 0044 30BD     		pop	{r4, r5, pc}
 1445              	.L71:
 1446 0046 C046     		.align	2
 1447              	.L70:
 1448 0048 007C0140 		.word	1073839104
 1449 004c FFFFE0FF 		.word	-2031617
 1450              		.cfi_endproc
 1451              	.LFE62:
 1453              		.section	.text.Hallmid_IP1_Config,"ax",%progbits
 1454              		.align	1
 1455              		.p2align 2,,3
 1456              		.global	Hallmid_IP1_Config
 1457              		.syntax unified
 1458              		.code	16
 1459              		.thumb_func
 1461              	Hallmid_IP1_Config:
ARM GAS  /tmp/ccQ8FEb0.s 			page 58


 1462              	.LVL72:
 1463              	.LFB63:
 438:Library/src/lcm32f06x_acmp.c **** 
 439:Library/src/lcm32f06x_acmp.c **** /**
 440:Library/src/lcm32f06x_acmp.c ****   * @name   Hallmid_IP1_Config
 441:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Hallmid IP1 config.
 442:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP1 配置。
 443:Library/src/lcm32f06x_acmp.c ****   * @param  HALL_IP1: 
 444:Library/src/lcm32f06x_acmp.c ****   *         EN: Hallmid IP1 Channel selection.
 445:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP1 通道选择。
 446:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP1_ACMP0_P4
 447:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP1_ACMP0_P0
 448:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 449:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the Hallmid IP1.
 450:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP1 的新状态。
 451:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 452:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 453:Library/src/lcm32f06x_acmp.c ****   * @retval None
 454:Library/src/lcm32f06x_acmp.c ****   */
 455:Library/src/lcm32f06x_acmp.c **** void Hallmid_IP1_Config(uint32_t HALL_IP1, FunctionalState NewState)
 456:Library/src/lcm32f06x_acmp.c **** {
 1464              		.loc 1 456 1 is_stmt 1 view -0
 1465              		.cfi_startproc
 1466              		@ args = 0, pretend = 0, frame = 0
 1467              		@ frame_needed = 0, uses_anonymous_args = 0
 457:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP1(HALL_IP1));
 1468              		.loc 1 457 3 view .LVU427
 458:Library/src/lcm32f06x_acmp.c **** 
 459:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1469              		.loc 1 459 3 view .LVU428
 456:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP1(HALL_IP1));
 1470              		.loc 1 456 1 is_stmt 0 view .LVU429
 1471 0000 10B5     		push	{r4, lr}
 1472              	.LCFI7:
 1473              		.cfi_def_cfa_offset 8
 1474              		.cfi_offset 4, -8
 1475              		.cfi_offset 14, -4
 1476              		.loc 1 459 6 view .LVU430
 1477 0002 0129     		cmp	r1, #1
 1478 0004 06D0     		beq	.L75
 460:Library/src/lcm32f06x_acmp.c ****   {
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_IP1_SEL = HALL_IP1;
 462:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 463:Library/src/lcm32f06x_acmp.c ****   }
 464:Library/src/lcm32f06x_acmp.c ****   else
 465:Library/src/lcm32f06x_acmp.c ****   {
 466:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 0;
 1479              		.loc 1 466 5 is_stmt 1 view .LVU431
 1480              		.loc 1 466 33 is_stmt 0 view .LVU432
 1481 0006 F422     		movs	r2, #244
 1482 0008 1020     		movs	r0, #16
 1483              	.LVL73:
 1484              		.loc 1 466 33 view .LVU433
 1485 000a 0949     		ldr	r1, .L76
 1486              	.LVL74:
 1487              		.loc 1 466 33 view .LVU434
 1488 000c 8B5C     		ldrb	r3, [r1, r2]
ARM GAS  /tmp/ccQ8FEb0.s 			page 59


 1489 000e 8343     		bics	r3, r0
 1490 0010 8B54     		strb	r3, [r1, r2]
 1491              	.L72:
 467:Library/src/lcm32f06x_acmp.c ****   }
 468:Library/src/lcm32f06x_acmp.c **** } 
 1492              		.loc 1 468 1 view .LVU435
 1493              		@ sp needed
 1494 0012 10BD     		pop	{r4, pc}
 1495              	.LVL75:
 1496              	.L75:
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 1497              		.loc 1 461 5 is_stmt 1 view .LVU436
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 1498              		.loc 1 461 37 is_stmt 0 view .LVU437
 1499 0014 F424     		movs	r4, #244
 1500 0016 0140     		ands	r1, r0
 1501              	.LVL76:
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 1502              		.loc 1 461 37 view .LVU438
 1503 0018 0220     		movs	r0, #2
 1504              	.LVL77:
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 1505              		.loc 1 461 37 view .LVU439
 1506 001a 054A     		ldr	r2, .L76
 1507 001c 4900     		lsls	r1, r1, #1
 1508 001e 135D     		ldrb	r3, [r2, r4]
 1509 0020 8343     		bics	r3, r0
 1510 0022 0B43     		orrs	r3, r1
 462:Library/src/lcm32f06x_acmp.c ****   }
 1511              		.loc 1 462 33 view .LVU440
 1512 0024 1021     		movs	r1, #16
 461:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW1 = 1;
 1513              		.loc 1 461 37 view .LVU441
 1514 0026 1355     		strb	r3, [r2, r4]
 462:Library/src/lcm32f06x_acmp.c ****   }
 1515              		.loc 1 462 5 is_stmt 1 view .LVU442
 462:Library/src/lcm32f06x_acmp.c ****   }
 1516              		.loc 1 462 33 is_stmt 0 view .LVU443
 1517 0028 135D     		ldrb	r3, [r2, r4]
 1518 002a 0B43     		orrs	r3, r1
 1519 002c 1355     		strb	r3, [r2, r4]
 1520 002e F0E7     		b	.L72
 1521              	.L77:
 1522              		.align	2
 1523              	.L76:
 1524 0030 007C0140 		.word	1073839104
 1525              		.cfi_endproc
 1526              	.LFE63:
 1528              		.section	.text.Hallmid_IP2_Config,"ax",%progbits
 1529              		.align	1
 1530              		.p2align 2,,3
 1531              		.global	Hallmid_IP2_Config
 1532              		.syntax unified
 1533              		.code	16
 1534              		.thumb_func
 1536              	Hallmid_IP2_Config:
 1537              	.LVL78:
ARM GAS  /tmp/ccQ8FEb0.s 			page 60


 1538              	.LFB64:
 469:Library/src/lcm32f06x_acmp.c **** 
 470:Library/src/lcm32f06x_acmp.c **** /**
 471:Library/src/lcm32f06x_acmp.c ****   * @name   Hallmid_IP2_Config
 472:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Hallmid IP2 config.
 473:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP2 配置。
 474:Library/src/lcm32f06x_acmp.c ****   * @param  HALL_IP1: 
 475:Library/src/lcm32f06x_acmp.c ****   *         EN: Hallmid IP2 Channel selection.
 476:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP2 通道选择。
 477:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP2_ACMP0_P5
 478:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP2_ACMP0_P1
 479:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 480:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the Hallmid IP2.
 481:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP2 的新状态。
 482:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 483:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 484:Library/src/lcm32f06x_acmp.c ****   * @retval None
 485:Library/src/lcm32f06x_acmp.c ****   */
 486:Library/src/lcm32f06x_acmp.c **** 
 487:Library/src/lcm32f06x_acmp.c **** void Hallmid_IP2_Config(uint32_t HALL_IP2, FunctionalState NewState)
 488:Library/src/lcm32f06x_acmp.c **** {
 1539              		.loc 1 488 1 is_stmt 1 view -0
 1540              		.cfi_startproc
 1541              		@ args = 0, pretend = 0, frame = 0
 1542              		@ frame_needed = 0, uses_anonymous_args = 0
 489:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP2(HALL_IP2));
 1543              		.loc 1 489 3 view .LVU445
 490:Library/src/lcm32f06x_acmp.c ****   
 491:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1544              		.loc 1 491 3 view .LVU446
 488:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP2(HALL_IP2));
 1545              		.loc 1 488 1 is_stmt 0 view .LVU447
 1546 0000 10B5     		push	{r4, lr}
 1547              	.LCFI8:
 1548              		.cfi_def_cfa_offset 8
 1549              		.cfi_offset 4, -8
 1550              		.cfi_offset 14, -4
 1551              		.loc 1 491 6 view .LVU448
 1552 0002 0129     		cmp	r1, #1
 1553 0004 06D0     		beq	.L81
 492:Library/src/lcm32f06x_acmp.c ****   {
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_IP2_SEL = HALL_IP2;
 494:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 495:Library/src/lcm32f06x_acmp.c ****   }
 496:Library/src/lcm32f06x_acmp.c ****   else
 497:Library/src/lcm32f06x_acmp.c ****   {
 498:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 0;
 1554              		.loc 1 498 5 is_stmt 1 view .LVU449
 1555              		.loc 1 498 33 is_stmt 0 view .LVU450
 1556 0006 F422     		movs	r2, #244
 1557 0008 2020     		movs	r0, #32
 1558              	.LVL79:
 1559              		.loc 1 498 33 view .LVU451
 1560 000a 0949     		ldr	r1, .L82
 1561              	.LVL80:
 1562              		.loc 1 498 33 view .LVU452
 1563 000c 8B5C     		ldrb	r3, [r1, r2]
ARM GAS  /tmp/ccQ8FEb0.s 			page 61


 1564 000e 8343     		bics	r3, r0
 1565 0010 8B54     		strb	r3, [r1, r2]
 1566              	.L78:
 499:Library/src/lcm32f06x_acmp.c ****   }
 500:Library/src/lcm32f06x_acmp.c **** }
 1567              		.loc 1 500 1 view .LVU453
 1568              		@ sp needed
 1569 0012 10BD     		pop	{r4, pc}
 1570              	.LVL81:
 1571              	.L81:
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 1572              		.loc 1 493 5 is_stmt 1 view .LVU454
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 1573              		.loc 1 493 37 is_stmt 0 view .LVU455
 1574 0014 F424     		movs	r4, #244
 1575 0016 0140     		ands	r1, r0
 1576              	.LVL82:
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 1577              		.loc 1 493 37 view .LVU456
 1578 0018 0420     		movs	r0, #4
 1579              	.LVL83:
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 1580              		.loc 1 493 37 view .LVU457
 1581 001a 054A     		ldr	r2, .L82
 1582 001c 8900     		lsls	r1, r1, #2
 1583 001e 135D     		ldrb	r3, [r2, r4]
 1584 0020 8343     		bics	r3, r0
 1585 0022 0B43     		orrs	r3, r1
 494:Library/src/lcm32f06x_acmp.c ****   }
 1586              		.loc 1 494 33 view .LVU458
 1587 0024 2021     		movs	r1, #32
 493:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW2 = 1;
 1588              		.loc 1 493 37 view .LVU459
 1589 0026 1355     		strb	r3, [r2, r4]
 494:Library/src/lcm32f06x_acmp.c ****   }
 1590              		.loc 1 494 5 is_stmt 1 view .LVU460
 494:Library/src/lcm32f06x_acmp.c ****   }
 1591              		.loc 1 494 33 is_stmt 0 view .LVU461
 1592 0028 135D     		ldrb	r3, [r2, r4]
 1593 002a 0B43     		orrs	r3, r1
 1594 002c 1355     		strb	r3, [r2, r4]
 1595 002e F0E7     		b	.L78
 1596              	.L83:
 1597              		.align	2
 1598              	.L82:
 1599 0030 007C0140 		.word	1073839104
 1600              		.cfi_endproc
 1601              	.LFE64:
 1603              		.section	.text.Hallmid_IP3_Config,"ax",%progbits
 1604              		.align	1
 1605              		.p2align 2,,3
 1606              		.global	Hallmid_IP3_Config
 1607              		.syntax unified
 1608              		.code	16
 1609              		.thumb_func
 1611              	Hallmid_IP3_Config:
 1612              	.LVL84:
ARM GAS  /tmp/ccQ8FEb0.s 			page 62


 1613              	.LFB65:
 501:Library/src/lcm32f06x_acmp.c **** 
 502:Library/src/lcm32f06x_acmp.c **** /**
 503:Library/src/lcm32f06x_acmp.c ****   * @name   Hallmid_IP3_Config
 504:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Hallmid IP3 config.
 505:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP3 配置。
 506:Library/src/lcm32f06x_acmp.c ****   * @param  HALL_IP1: 
 507:Library/src/lcm32f06x_acmp.c ****   *         EN: Hallmid IP3 Channel selection.
 508:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP3 通道选择。
 509:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP3_ACMP0_P6
 510:Library/src/lcm32f06x_acmp.c ****   *             @arg HALL_IP3_ACMP0_P2
 511:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 512:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the Hallmid IP3.
 513:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid IP3 的新状态。
 514:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 515:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 516:Library/src/lcm32f06x_acmp.c ****   * @retval None
 517:Library/src/lcm32f06x_acmp.c ****   */
 518:Library/src/lcm32f06x_acmp.c **** void Hallmid_IP3_Config(uint32_t HALL_IP3, FunctionalState NewState)
 519:Library/src/lcm32f06x_acmp.c **** {
 1614              		.loc 1 519 1 is_stmt 1 view -0
 1615              		.cfi_startproc
 1616              		@ args = 0, pretend = 0, frame = 0
 1617              		@ frame_needed = 0, uses_anonymous_args = 0
 520:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP3(HALL_IP3));
 1618              		.loc 1 520 3 view .LVU463
 521:Library/src/lcm32f06x_acmp.c **** 
 522:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1619              		.loc 1 522 3 view .LVU464
 519:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_HALL_IP3(HALL_IP3));
 1620              		.loc 1 519 1 is_stmt 0 view .LVU465
 1621 0000 10B5     		push	{r4, lr}
 1622              	.LCFI9:
 1623              		.cfi_def_cfa_offset 8
 1624              		.cfi_offset 4, -8
 1625              		.cfi_offset 14, -4
 1626              		.loc 1 522 6 view .LVU466
 1627 0002 0129     		cmp	r1, #1
 1628 0004 06D0     		beq	.L87
 523:Library/src/lcm32f06x_acmp.c ****   {
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_IP3_SEL = HALL_IP3;
 525:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 526:Library/src/lcm32f06x_acmp.c ****   }
 527:Library/src/lcm32f06x_acmp.c ****   else
 528:Library/src/lcm32f06x_acmp.c ****   {
 529:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 0;
 1629              		.loc 1 529 5 is_stmt 1 view .LVU467
 1630              		.loc 1 529 33 is_stmt 0 view .LVU468
 1631 0006 F422     		movs	r2, #244
 1632 0008 4020     		movs	r0, #64
 1633              	.LVL85:
 1634              		.loc 1 529 33 view .LVU469
 1635 000a 0949     		ldr	r1, .L88
 1636              	.LVL86:
 1637              		.loc 1 529 33 view .LVU470
 1638 000c 8B5C     		ldrb	r3, [r1, r2]
 1639 000e 8343     		bics	r3, r0
ARM GAS  /tmp/ccQ8FEb0.s 			page 63


 1640 0010 8B54     		strb	r3, [r1, r2]
 1641              	.L84:
 530:Library/src/lcm32f06x_acmp.c ****   }
 531:Library/src/lcm32f06x_acmp.c **** }
 1642              		.loc 1 531 1 view .LVU471
 1643              		@ sp needed
 1644 0012 10BD     		pop	{r4, pc}
 1645              	.LVL87:
 1646              	.L87:
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 1647              		.loc 1 524 5 is_stmt 1 view .LVU472
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 1648              		.loc 1 524 37 is_stmt 0 view .LVU473
 1649 0014 F424     		movs	r4, #244
 1650 0016 0140     		ands	r1, r0
 1651              	.LVL88:
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 1652              		.loc 1 524 37 view .LVU474
 1653 0018 0820     		movs	r0, #8
 1654              	.LVL89:
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 1655              		.loc 1 524 37 view .LVU475
 1656 001a 054A     		ldr	r2, .L88
 1657 001c C900     		lsls	r1, r1, #3
 1658 001e 135D     		ldrb	r3, [r2, r4]
 1659 0020 8343     		bics	r3, r0
 1660 0022 0B43     		orrs	r3, r1
 525:Library/src/lcm32f06x_acmp.c ****   }
 1661              		.loc 1 525 33 view .LVU476
 1662 0024 4021     		movs	r1, #64
 524:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_SW3 = 1;
 1663              		.loc 1 524 37 view .LVU477
 1664 0026 1355     		strb	r3, [r2, r4]
 525:Library/src/lcm32f06x_acmp.c ****   }
 1665              		.loc 1 525 5 is_stmt 1 view .LVU478
 525:Library/src/lcm32f06x_acmp.c ****   }
 1666              		.loc 1 525 33 is_stmt 0 view .LVU479
 1667 0028 135D     		ldrb	r3, [r2, r4]
 1668 002a 0B43     		orrs	r3, r1
 1669 002c 1355     		strb	r3, [r2, r4]
 1670 002e F0E7     		b	.L84
 1671              	.L89:
 1672              		.align	2
 1673              	.L88:
 1674 0030 007C0140 		.word	1073839104
 1675              		.cfi_endproc
 1676              	.LFE65:
 1678              		.section	.text.Hallmid_Cmd,"ax",%progbits
 1679              		.align	1
 1680              		.p2align 2,,3
 1681              		.global	Hallmid_Cmd
 1682              		.syntax unified
 1683              		.code	16
 1684              		.thumb_func
 1686              	Hallmid_Cmd:
 1687              	.LVL90:
 1688              	.LFB66:
ARM GAS  /tmp/ccQ8FEb0.s 			page 64


 532:Library/src/lcm32f06x_acmp.c **** 
 533:Library/src/lcm32f06x_acmp.c **** 
 534:Library/src/lcm32f06x_acmp.c **** /**
 535:Library/src/lcm32f06x_acmp.c ****   * @name   Hallmid_Cmd
 536:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: Hallmid enable. 
 537:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid 使能。
 538:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 539:Library/src/lcm32f06x_acmp.c ****   *         EN: New state of the Hallmid.
 540:Library/src/lcm32f06x_acmp.c ****   *         CN: Hallmid 的新状态。
 541:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 542:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 543:Library/src/lcm32f06x_acmp.c ****   * @retval None
 544:Library/src/lcm32f06x_acmp.c ****   */
 545:Library/src/lcm32f06x_acmp.c **** void Hallmid_Cmd(FunctionalState NewState)
 546:Library/src/lcm32f06x_acmp.c **** {
 1689              		.loc 1 546 1 is_stmt 1 view -0
 1690              		.cfi_startproc
 1691              		@ args = 0, pretend = 0, frame = 0
 1692              		@ frame_needed = 0, uses_anonymous_args = 0
 1693              		@ link register save eliminated.
 547:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1694              		.loc 1 547 3 view .LVU481
 548:Library/src/lcm32f06x_acmp.c ****   {
 549:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_MID_EN = 1;
 1695              		.loc 1 549 36 is_stmt 0 view .LVU482
 1696 0000 F422     		movs	r2, #244
 1697 0002 0549     		ldr	r1, .L94
 1698 0004 8B5C     		ldrb	r3, [r1, r2]
 547:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1699              		.loc 1 547 6 view .LVU483
 1700 0006 0128     		cmp	r0, #1
 1701 0008 03D0     		beq	.L93
 550:Library/src/lcm32f06x_acmp.c ****   }
 551:Library/src/lcm32f06x_acmp.c ****   else
 552:Library/src/lcm32f06x_acmp.c ****   {
 553:Library/src/lcm32f06x_acmp.c ****     ANACTRL->HALL_CR_b.HALL_MID_EN = 0;
 1702              		.loc 1 553 5 is_stmt 1 view .LVU484
 1703              		.loc 1 553 36 is_stmt 0 view .LVU485
 1704 000a 0120     		movs	r0, #1
 1705              	.LVL91:
 1706              		.loc 1 553 36 view .LVU486
 1707 000c 8343     		bics	r3, r0
 1708 000e 8B54     		strb	r3, [r1, r2]
 1709              	.L90:
 554:Library/src/lcm32f06x_acmp.c ****   }
 555:Library/src/lcm32f06x_acmp.c **** }
 1710              		.loc 1 555 1 view .LVU487
 1711              		@ sp needed
 1712 0010 7047     		bx	lr
 1713              	.LVL92:
 1714              	.L93:
 549:Library/src/lcm32f06x_acmp.c ****   }
 1715              		.loc 1 549 5 is_stmt 1 view .LVU488
 549:Library/src/lcm32f06x_acmp.c ****   }
 1716              		.loc 1 549 36 is_stmt 0 view .LVU489
 1717 0012 0343     		orrs	r3, r0
 1718 0014 8B54     		strb	r3, [r1, r2]
ARM GAS  /tmp/ccQ8FEb0.s 			page 65


 1719 0016 FBE7     		b	.L90
 1720              	.L95:
 1721              		.align	2
 1722              	.L94:
 1723 0018 007C0140 		.word	1073839104
 1724              		.cfi_endproc
 1725              	.LFE66:
 1727              		.section	.text.ACMP_ANA_CVREFCfg,"ax",%progbits
 1728              		.align	1
 1729              		.p2align 2,,3
 1730              		.global	ACMP_ANA_CVREFCfg
 1731              		.syntax unified
 1732              		.code	16
 1733              		.thumb_func
 1735              	ACMP_ANA_CVREFCfg:
 1736              	.LVL93:
 1737              	.LFB67:
 556:Library/src/lcm32f06x_acmp.c **** 
 557:Library/src/lcm32f06x_acmp.c **** /**
 558:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP_ANA_CVREFCfg
 559:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP internal reference voltage configuration.
 560:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP内部参考电压配置。
 561:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 562:Library/src/lcm32f06x_acmp.c ****   *         EN: Enable/disable comparator internal voltage CVREF.
 563:Library/src/lcm32f06x_acmp.c ****   *         CN: 启用/禁用 比较器内部电压 CVREF。
 564:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 565:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 566:Library/src/lcm32f06x_acmp.c ****   * @param  VRH_SEL: 
 567:Library/src/lcm32f06x_acmp.c ****   *         EN: Selection of voltage divider resistance range.
 568:Library/src/lcm32f06x_acmp.c ****   *         CN: 分压电阻范围选择。
 569:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_VDDA_0
 570:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_VDDA_1
 571:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_VDDA_2
 572:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_VDDA_3
 573:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_ADC_VREF_0
 574:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_ADC_VREF_1
 575:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_ADC_VREF_2
 576:Library/src/lcm32f06x_acmp.c ****   *             @arg VRH_SEL_ADC_VREF_3
 577:Library/src/lcm32f06x_acmp.c ****   * @param  RDS_SEL: 
 578:Library/src/lcm32f06x_acmp.c ****   *         EN: Selection of voltage divider.
 579:Library/src/lcm32f06x_acmp.c ****   *         CN: 分压选择。
 580:Library/src/lcm32f06x_acmp.c ****   *             @range 0x0 - 0xF
 581:Library/src/lcm32f06x_acmp.c ****   * @retval None
 582:Library/src/lcm32f06x_acmp.c ****   */
 583:Library/src/lcm32f06x_acmp.c **** void ACMP_ANA_CVREFCfg(FunctionalState NewState, uint32_t VRH_SEL,uint8_t RDS_SEL)
 584:Library/src/lcm32f06x_acmp.c **** {
 1738              		.loc 1 584 1 is_stmt 1 view -0
 1739              		.cfi_startproc
 1740              		@ args = 0, pretend = 0, frame = 0
 1741              		@ frame_needed = 0, uses_anonymous_args = 0
 585:Library/src/lcm32f06x_acmp.c ****   uint32_t temprg = 0;
 1742              		.loc 1 585 3 view .LVU491
 586:Library/src/lcm32f06x_acmp.c ****   assert_param(IS_VRH_SEL(VRH_SEL));
 1743              		.loc 1 586 3 view .LVU492
 587:Library/src/lcm32f06x_acmp.c **** 
 588:Library/src/lcm32f06x_acmp.c ****   if (NewState == ENABLE)
 1744              		.loc 1 588 3 view .LVU493
ARM GAS  /tmp/ccQ8FEb0.s 			page 66


 584:Library/src/lcm32f06x_acmp.c ****   uint32_t temprg = 0;
 1745              		.loc 1 584 1 is_stmt 0 view .LVU494
 1746 0000 30B5     		push	{r4, r5, lr}
 1747              	.LCFI10:
 1748              		.cfi_def_cfa_offset 12
 1749              		.cfi_offset 4, -12
 1750              		.cfi_offset 5, -8
 1751              		.cfi_offset 14, -4
 584:Library/src/lcm32f06x_acmp.c ****   uint32_t temprg = 0;
 1752              		.loc 1 584 1 view .LVU495
 1753 0002 0C00     		movs	r4, r1
 1754              		.loc 1 588 6 view .LVU496
 1755 0004 0128     		cmp	r0, #1
 1756 0006 0FD0     		beq	.L99
 589:Library/src/lcm32f06x_acmp.c ****   {
 590:Library/src/lcm32f06x_acmp.c ****     ANACTRL->ANA_CTRL_b.CVREFEN = 1;
 591:Library/src/lcm32f06x_acmp.c ****   }
 592:Library/src/lcm32f06x_acmp.c ****   else
 593:Library/src/lcm32f06x_acmp.c ****   {
 594:Library/src/lcm32f06x_acmp.c ****     ANACTRL->ANA_CTRL_b.CVREFEN = 0;
 1757              		.loc 1 594 5 is_stmt 1 view .LVU497
 1758              		.loc 1 594 33 is_stmt 0 view .LVU498
 1759 0008 F821     		movs	r1, #248
 1760              	.LVL94:
 1761              		.loc 1 594 33 view .LVU499
 1762 000a 0B48     		ldr	r0, .L100
 1763              	.LVL95:
 1764              		.loc 1 594 33 view .LVU500
 1765 000c 0B4D     		ldr	r5, .L100+4
 1766 000e 4358     		ldr	r3, [r0, r1]
 1767 0010 2B40     		ands	r3, r5
 1768 0012 4350     		str	r3, [r0, r1]
 1769              	.L98:
 595:Library/src/lcm32f06x_acmp.c ****   }
 596:Library/src/lcm32f06x_acmp.c ****   temprg = ANACTRL->ANA_CTRL;
 1770              		.loc 1 596 3 is_stmt 1 view .LVU501
 1771              		.loc 1 596 10 is_stmt 0 view .LVU502
 1772 0014 F820     		movs	r0, #248
 597:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 598:Library/src/lcm32f06x_acmp.c ****   temprg |= (VRH_SEL | (RDS_SEL << ANACTRL_ANA_CTRL_RDS_Pos));
 599:Library/src/lcm32f06x_acmp.c ****   ANACTRL->ANA_CTRL = temprg;
 600:Library/src/lcm32f06x_acmp.c **** }
 1773              		.loc 1 600 1 view .LVU503
 1774              		@ sp needed
 596:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 1775              		.loc 1 596 10 view .LVU504
 1776 0016 084B     		ldr	r3, .L100
 598:Library/src/lcm32f06x_acmp.c ****   ANACTRL->ANA_CTRL = temprg;
 1777              		.loc 1 598 33 view .LVU505
 1778 0018 5206     		lsls	r2, r2, #25
 1779              	.LVL96:
 596:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 1780              		.loc 1 596 10 view .LVU506
 1781 001a 1958     		ldr	r1, [r3, r0]
 1782              	.LVL97:
 597:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 1783              		.loc 1 597 3 is_stmt 1 view .LVU507
ARM GAS  /tmp/ccQ8FEb0.s 			page 67


 598:Library/src/lcm32f06x_acmp.c ****   ANACTRL->ANA_CTRL = temprg;
 1784              		.loc 1 598 3 view .LVU508
 597:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 1785              		.loc 1 597 10 is_stmt 0 view .LVU509
 1786 001c C901     		lsls	r1, r1, #7
 1787              	.LVL98:
 597:Library/src/lcm32f06x_acmp.c ****   temprg &= ~(0xFE000000);
 1788              		.loc 1 597 10 view .LVU510
 1789 001e C909     		lsrs	r1, r1, #7
 1790 0020 2143     		orrs	r1, r4
 598:Library/src/lcm32f06x_acmp.c ****   ANACTRL->ANA_CTRL = temprg;
 1791              		.loc 1 598 10 view .LVU511
 1792 0022 0A43     		orrs	r2, r1
 1793              	.LVL99:
 599:Library/src/lcm32f06x_acmp.c **** }
 1794              		.loc 1 599 3 is_stmt 1 view .LVU512
 599:Library/src/lcm32f06x_acmp.c **** }
 1795              		.loc 1 599 21 is_stmt 0 view .LVU513
 1796 0024 1A50     		str	r2, [r3, r0]
 1797              	.LVL100:
 1798              		.loc 1 600 1 view .LVU514
 1799 0026 30BD     		pop	{r4, r5, pc}
 1800              	.LVL101:
 1801              	.L99:
 590:Library/src/lcm32f06x_acmp.c ****   }
 1802              		.loc 1 590 5 is_stmt 1 view .LVU515
 590:Library/src/lcm32f06x_acmp.c ****   }
 1803              		.loc 1 590 33 is_stmt 0 view .LVU516
 1804 0028 F821     		movs	r1, #248
 1805              	.LVL102:
 590:Library/src/lcm32f06x_acmp.c ****   }
 1806              		.loc 1 590 33 view .LVU517
 1807 002a 8023     		movs	r3, #128
 1808 002c 0248     		ldr	r0, .L100
 1809              	.LVL103:
 590:Library/src/lcm32f06x_acmp.c ****   }
 1810              		.loc 1 590 33 view .LVU518
 1811 002e 5B04     		lsls	r3, r3, #17
 1812 0030 4558     		ldr	r5, [r0, r1]
 1813 0032 2B43     		orrs	r3, r5
 1814 0034 4350     		str	r3, [r0, r1]
 1815 0036 EDE7     		b	.L98
 1816              	.L101:
 1817              		.align	2
 1818              	.L100:
 1819 0038 007C0140 		.word	1073839104
 1820 003c FFFFFFFE 		.word	-16777217
 1821              		.cfi_endproc
 1822              	.LFE67:
 1824              		.section	.text.ACMP0_BlankingCfg,"ax",%progbits
 1825              		.align	1
 1826              		.p2align 2,,3
 1827              		.global	ACMP0_BlankingCfg
 1828              		.syntax unified
 1829              		.code	16
 1830              		.thumb_func
 1832              	ACMP0_BlankingCfg:
ARM GAS  /tmp/ccQ8FEb0.s 			page 68


 1833              	.LVL104:
 1834              	.LFB68:
 601:Library/src/lcm32f06x_acmp.c **** 
 602:Library/src/lcm32f06x_acmp.c **** 
 603:Library/src/lcm32f06x_acmp.c **** /**
 604:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_BlankingCfg
 605:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 Hidden Source Selection.
 606:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 消隐源选择。
 607:Library/src/lcm32f06x_acmp.c ****   * @param  BlankingSource: 
 608:Library/src/lcm32f06x_acmp.c ****   *         EN: Select the hidden source, and the parameters can be or operated on.
 609:Library/src/lcm32f06x_acmp.c ****   *         CN: 选择消隐源，参数可以或操作。
 610:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_Software
 611:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM2_TRIG_OC4
 612:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM15_TRIG_OC2
 613:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM15_TRIG_OC1
 614:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC5
 615:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC3
 616:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC2
 617:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC1
 618:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 619:Library/src/lcm32f06x_acmp.c ****   *         EN: Enable/disable hidden source selection.
 620:Library/src/lcm32f06x_acmp.c ****   *         CN: 使能/失能消隐源选择。
 621:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 622:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 623:Library/src/lcm32f06x_acmp.c **** 
 624:Library/src/lcm32f06x_acmp.c ****   * @retval None
 625:Library/src/lcm32f06x_acmp.c ****   */
 626:Library/src/lcm32f06x_acmp.c **** void ACMP0_BlankingCfg(uint32_t BlankingSource, FunctionalState NewState)
 627:Library/src/lcm32f06x_acmp.c **** {
 1835              		.loc 1 627 1 is_stmt 1 view -0
 1836              		.cfi_startproc
 1837              		@ args = 0, pretend = 0, frame = 0
 1838              		@ frame_needed = 0, uses_anonymous_args = 0
 1839              		@ link register save eliminated.
 628:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 1840              		.loc 1 628 3 view .LVU520
 1841              		.loc 1 628 6 is_stmt 0 view .LVU521
 1842 0000 0029     		cmp	r1, #0
 1843 0002 0DD0     		beq	.L103
 629:Library/src/lcm32f06x_acmp.c ****   {
 630:Library/src/lcm32f06x_acmp.c ****     sysctrl_access();
 1844              		.loc 1 630 5 is_stmt 1 view .LVU522
 1845              	.LBB78:
 1846              	.LBI78:
 258:Core/cmsis_gcc.h **** {
 1847              		.loc 2 258 27 view .LVU523
 1848              	.LBB79:
 260:Core/cmsis_gcc.h **** }
 1849              		.loc 2 260 3 view .LVU524
 1850              		.syntax divided
 1851              	@ 260 "Core/cmsis_gcc.h" 1
 1852 0004 BFF36F8F 		isb 0xF
 1853              	@ 0 "" 2
 1854              		.thumb
 1855              		.syntax unified
 1856              	.LBE79:
 1857              	.LBE78:
ARM GAS  /tmp/ccQ8FEb0.s 			page 69


 1858              		.loc 1 630 5 discriminator 1 view .LVU525
 1859              	.LBB80:
 1860              	.LBI80:
1204:Core/cmsis_gcc.h **** {
 1861              		.loc 2 1204 31 view .LVU526
 1862              	.LBB81:
1206:Core/cmsis_gcc.h **** 
 1863              		.loc 2 1206 3 view .LVU527
1208:Core/cmsis_gcc.h ****   return(result);
 1864              		.loc 2 1208 3 view .LVU528
 1865              		.syntax divided
 1866              	@ 1208 "Core/cmsis_gcc.h" 1
 1867 0008 EFF31083 		MRS r3, primask
 1868              	@ 0 "" 2
 1869              	.LVL105:
 1870              		.loc 2 1209 3 view .LVU529
 1871              		.loc 2 1209 3 is_stmt 0 view .LVU530
 1872              		.thumb
 1873              		.syntax unified
 1874              	.LBE81:
 1875              	.LBE80:
 1876              		.loc 1 630 5 is_stmt 1 discriminator 2 view .LVU531
 1877              	.LBB82:
 1878              	.LBI82:
 960:Core/cmsis_gcc.h **** {
 1879              		.loc 2 960 27 view .LVU532
 1880              	.LBB83:
 962:Core/cmsis_gcc.h **** }
 1881              		.loc 2 962 3 view .LVU533
 1882              		.syntax divided
 1883              	@ 962 "Core/cmsis_gcc.h" 1
 1884 000c 72B6     		cpsid i
 1885              	@ 0 "" 2
 1886              		.thumb
 1887              		.syntax unified
 1888              	.LBE83:
 1889              	.LBE82:
 1890              		.loc 1 630 5 discriminator 3 view .LVU534
 1891 000e 0B4B     		ldr	r3, .L105
 1892 0010 0B4A     		ldr	r2, .L105+4
 1893 0012 1A60     		str	r2, [r3]
 1894              		.loc 1 630 21 discriminator 3 view .LVU535
 631:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= BlankingSource;
 1895              		.loc 1 631 5 view .LVU536
 1896              		.loc 1 631 12 is_stmt 0 view .LVU537
 1897 0014 0B4A     		ldr	r2, .L105+8
 1898 0016 D36D     		ldr	r3, [r2, #92]
 1899              		.loc 1 631 24 view .LVU538
 1900 0018 0343     		orrs	r3, r0
 1901 001a D365     		str	r3, [r2, #92]
 632:Library/src/lcm32f06x_acmp.c ****     __dekey();
 1902              		.loc 1 632 5 is_stmt 1 view .LVU539
 1903              	.LBB84:
 1904              	.LBI84:
 949:Core/cmsis_gcc.h **** {
 1905              		.loc 2 949 27 view .LVU540
 1906              	.LBB85:
ARM GAS  /tmp/ccQ8FEb0.s 			page 70


 951:Core/cmsis_gcc.h **** }
 1907              		.loc 2 951 3 view .LVU541
 1908              		.syntax divided
 1909              	@ 951 "Core/cmsis_gcc.h" 1
 1910 001c 62B6     		cpsie i
 1911              	@ 0 "" 2
 1912              		.thumb
 1913              		.syntax unified
 1914              	.LBE85:
 1915              	.LBE84:
 1916              		.loc 1 632 14 discriminator 1 view .LVU542
 1917              	.L102:
 633:Library/src/lcm32f06x_acmp.c ****   }
 634:Library/src/lcm32f06x_acmp.c ****   else
 635:Library/src/lcm32f06x_acmp.c ****   {
 636:Library/src/lcm32f06x_acmp.c ****       sysctrl_access();
 637:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 638:Library/src/lcm32f06x_acmp.c ****       __dekey();
 639:Library/src/lcm32f06x_acmp.c ****   }
 640:Library/src/lcm32f06x_acmp.c **** }
 1918              		.loc 1 640 1 is_stmt 0 view .LVU543
 1919              		@ sp needed
 1920 001e 7047     		bx	lr
 1921              	.L103:
 636:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 1922              		.loc 1 636 7 is_stmt 1 view .LVU544
 1923              	.LBB86:
 1924              	.LBI86:
 258:Core/cmsis_gcc.h **** {
 1925              		.loc 2 258 27 view .LVU545
 1926              	.LBB87:
 260:Core/cmsis_gcc.h **** }
 1927              		.loc 2 260 3 view .LVU546
 1928              		.syntax divided
 1929              	@ 260 "Core/cmsis_gcc.h" 1
 1930 0020 BFF36F8F 		isb 0xF
 1931              	@ 0 "" 2
 1932              		.thumb
 1933              		.syntax unified
 1934              	.LBE87:
 1935              	.LBE86:
 636:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 1936              		.loc 1 636 7 discriminator 1 view .LVU547
 1937              	.LBB88:
 1938              	.LBI88:
1204:Core/cmsis_gcc.h **** {
 1939              		.loc 2 1204 31 view .LVU548
 1940              	.LBB89:
1206:Core/cmsis_gcc.h **** 
 1941              		.loc 2 1206 3 view .LVU549
1208:Core/cmsis_gcc.h ****   return(result);
 1942              		.loc 2 1208 3 view .LVU550
 1943              		.syntax divided
 1944              	@ 1208 "Core/cmsis_gcc.h" 1
 1945 0024 EFF31083 		MRS r3, primask
 1946              	@ 0 "" 2
 1947              	.LVL106:
ARM GAS  /tmp/ccQ8FEb0.s 			page 71


 1948              		.loc 2 1209 3 view .LVU551
 1949              		.loc 2 1209 3 is_stmt 0 view .LVU552
 1950              		.thumb
 1951              		.syntax unified
 1952              	.LBE89:
 1953              	.LBE88:
 636:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 1954              		.loc 1 636 7 is_stmt 1 discriminator 2 view .LVU553
 1955              	.LBB90:
 1956              	.LBI90:
 960:Core/cmsis_gcc.h **** {
 1957              		.loc 2 960 27 view .LVU554
 1958              	.LBB91:
 962:Core/cmsis_gcc.h **** }
 1959              		.loc 2 962 3 view .LVU555
 1960              		.syntax divided
 1961              	@ 962 "Core/cmsis_gcc.h" 1
 1962 0028 72B6     		cpsid i
 1963              	@ 0 "" 2
 1964              		.thumb
 1965              		.syntax unified
 1966              	.LBE91:
 1967              	.LBE90:
 636:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 1968              		.loc 1 636 7 discriminator 3 view .LVU556
 1969 002a 044B     		ldr	r3, .L105
 1970 002c 044A     		ldr	r2, .L105+4
 1971 002e 1A60     		str	r2, [r3]
 636:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~BlankingSource);
 1972              		.loc 1 636 23 discriminator 3 view .LVU557
 637:Library/src/lcm32f06x_acmp.c ****       __dekey();
 1973              		.loc 1 637 7 view .LVU558
 637:Library/src/lcm32f06x_acmp.c ****       __dekey();
 1974              		.loc 1 637 14 is_stmt 0 view .LVU559
 1975 0030 044A     		ldr	r2, .L105+8
 1976 0032 D36D     		ldr	r3, [r2, #92]
 637:Library/src/lcm32f06x_acmp.c ****       __dekey();
 1977              		.loc 1 637 26 view .LVU560
 1978 0034 8343     		bics	r3, r0
 1979 0036 D365     		str	r3, [r2, #92]
 638:Library/src/lcm32f06x_acmp.c ****   }
 1980              		.loc 1 638 7 is_stmt 1 view .LVU561
 1981              	.LBB92:
 1982              	.LBI92:
 949:Core/cmsis_gcc.h **** {
 1983              		.loc 2 949 27 view .LVU562
 1984              	.LBB93:
 951:Core/cmsis_gcc.h **** }
 1985              		.loc 2 951 3 view .LVU563
 1986              		.syntax divided
 1987              	@ 951 "Core/cmsis_gcc.h" 1
 1988 0038 62B6     		cpsie i
 1989              	@ 0 "" 2
 1990              		.thumb
 1991              		.syntax unified
 1992              	.LBE93:
 1993              	.LBE92:
ARM GAS  /tmp/ccQ8FEb0.s 			page 72


 638:Library/src/lcm32f06x_acmp.c ****   }
 1994              		.loc 1 638 16 view .LVU564
 1995              		.loc 1 640 1 is_stmt 0 view .LVU565
 1996 003a F0E7     		b	.L102
 1997              	.L106:
 1998              		.align	2
 1999              	.L105:
 2000 003c 7C700048 		.word	1207988348
 2001 0040 9A65FA05 		.word	100296090
 2002 0044 00700048 		.word	1207988224
 2003              		.cfi_endproc
 2004              	.LFE68:
 2006              		.section	.text.ACMP1_BlankingCfg,"ax",%progbits
 2007              		.align	1
 2008              		.p2align 2,,3
 2009              		.global	ACMP1_BlankingCfg
 2010              		.syntax unified
 2011              		.code	16
 2012              		.thumb_func
 2014              	ACMP1_BlankingCfg:
 2015              	.LVL107:
 2016              	.LFB69:
 641:Library/src/lcm32f06x_acmp.c **** 
 642:Library/src/lcm32f06x_acmp.c **** /**
 643:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_BlankingCfg
 644:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 Hidden Source Selection.
 645:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 消隐源选择。
 646:Library/src/lcm32f06x_acmp.c ****   * @param  BlankingSource: 
 647:Library/src/lcm32f06x_acmp.c ****   *         EN: Select the hidden source, and the parameters can be or operated on.
 648:Library/src/lcm32f06x_acmp.c ****   *         CN: 选择消隐源，参数可以或操作。
 649:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_Software
 650:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM2_TRIG_OC4
 651:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM15_TRIG_OC2
 652:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM15_TRIG_OC1
 653:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC5
 654:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC3
 655:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC2
 656:Library/src/lcm32f06x_acmp.c ****   *             @arg Blanking_TIM1_TRIG_OC1
 657:Library/src/lcm32f06x_acmp.c ****   * @param  NewState: 
 658:Library/src/lcm32f06x_acmp.c ****   *         EN: Enable/disable hidden source selection.
 659:Library/src/lcm32f06x_acmp.c ****   *         CN: 使能/失能消隐源选择。
 660:Library/src/lcm32f06x_acmp.c ****   *             @arg ENABLE
 661:Library/src/lcm32f06x_acmp.c ****   *             @arg DISABLE
 662:Library/src/lcm32f06x_acmp.c **** 
 663:Library/src/lcm32f06x_acmp.c ****   * @retval None
 664:Library/src/lcm32f06x_acmp.c ****   */
 665:Library/src/lcm32f06x_acmp.c **** void ACMP1_BlankingCfg(uint32_t BlankingSource, FunctionalState NewState)
 666:Library/src/lcm32f06x_acmp.c **** {
 2017              		.loc 1 666 1 is_stmt 1 view -0
 2018              		.cfi_startproc
 2019              		@ args = 0, pretend = 0, frame = 0
 2020              		@ frame_needed = 0, uses_anonymous_args = 0
 2021              		@ link register save eliminated.
 667:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 2022              		.loc 1 667 3 view .LVU567
 668:Library/src/lcm32f06x_acmp.c ****   {
 669:Library/src/lcm32f06x_acmp.c ****     sysctrl_access();
ARM GAS  /tmp/ccQ8FEb0.s 			page 73


 670:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2023              		.loc 1 670 43 is_stmt 0 view .LVU568
 2024 0000 0002     		lsls	r0, r0, #8
 2025              	.LVL108:
 667:Library/src/lcm32f06x_acmp.c ****   if (NewState != DISABLE)
 2026              		.loc 1 667 6 view .LVU569
 2027 0002 0029     		cmp	r1, #0
 2028 0004 0DD0     		beq	.L108
 669:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2029              		.loc 1 669 5 is_stmt 1 view .LVU570
 2030              	.LBB94:
 2031              	.LBI94:
 258:Core/cmsis_gcc.h **** {
 2032              		.loc 2 258 27 view .LVU571
 2033              	.LBB95:
 260:Core/cmsis_gcc.h **** }
 2034              		.loc 2 260 3 view .LVU572
 2035              		.syntax divided
 2036              	@ 260 "Core/cmsis_gcc.h" 1
 2037 0006 BFF36F8F 		isb 0xF
 2038              	@ 0 "" 2
 2039              		.thumb
 2040              		.syntax unified
 2041              	.LBE95:
 2042              	.LBE94:
 669:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2043              		.loc 1 669 5 discriminator 1 view .LVU573
 2044              	.LBB96:
 2045              	.LBI96:
1204:Core/cmsis_gcc.h **** {
 2046              		.loc 2 1204 31 view .LVU574
 2047              	.LBB97:
1206:Core/cmsis_gcc.h **** 
 2048              		.loc 2 1206 3 view .LVU575
1208:Core/cmsis_gcc.h ****   return(result);
 2049              		.loc 2 1208 3 view .LVU576
 2050              		.syntax divided
 2051              	@ 1208 "Core/cmsis_gcc.h" 1
 2052 000a EFF31083 		MRS r3, primask
 2053              	@ 0 "" 2
 2054              	.LVL109:
 2055              		.loc 2 1209 3 view .LVU577
 2056              		.loc 2 1209 3 is_stmt 0 view .LVU578
 2057              		.thumb
 2058              		.syntax unified
 2059              	.LBE97:
 2060              	.LBE96:
 669:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2061              		.loc 1 669 5 is_stmt 1 discriminator 2 view .LVU579
 2062              	.LBB98:
 2063              	.LBI98:
 960:Core/cmsis_gcc.h **** {
 2064              		.loc 2 960 27 view .LVU580
 2065              	.LBB99:
 962:Core/cmsis_gcc.h **** }
 2066              		.loc 2 962 3 view .LVU581
 2067              		.syntax divided
ARM GAS  /tmp/ccQ8FEb0.s 			page 74


 2068              	@ 962 "Core/cmsis_gcc.h" 1
 2069 000e 72B6     		cpsid i
 2070              	@ 0 "" 2
 2071              		.thumb
 2072              		.syntax unified
 2073              	.LBE99:
 2074              	.LBE98:
 669:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2075              		.loc 1 669 5 discriminator 3 view .LVU582
 2076 0010 0B4B     		ldr	r3, .L110
 2077 0012 0C4A     		ldr	r2, .L110+4
 2078 0014 1A60     		str	r2, [r3]
 669:Library/src/lcm32f06x_acmp.c ****     SYSCTRL->EDU_CFG15 |= (BlankingSource << 8);
 2079              		.loc 1 669 21 discriminator 3 view .LVU583
 2080              		.loc 1 670 5 view .LVU584
 2081              		.loc 1 670 12 is_stmt 0 view .LVU585
 2082 0016 0C4B     		ldr	r3, .L110+8
 2083 0018 DA6D     		ldr	r2, [r3, #92]
 2084              		.loc 1 670 24 view .LVU586
 2085 001a 1043     		orrs	r0, r2
 2086 001c D865     		str	r0, [r3, #92]
 671:Library/src/lcm32f06x_acmp.c ****     __dekey();
 2087              		.loc 1 671 5 is_stmt 1 view .LVU587
 2088              	.LBB100:
 2089              	.LBI100:
 949:Core/cmsis_gcc.h **** {
 2090              		.loc 2 949 27 view .LVU588
 2091              	.LBB101:
 951:Core/cmsis_gcc.h **** }
 2092              		.loc 2 951 3 view .LVU589
 2093              		.syntax divided
 2094              	@ 951 "Core/cmsis_gcc.h" 1
 2095 001e 62B6     		cpsie i
 2096              	@ 0 "" 2
 2097              		.thumb
 2098              		.syntax unified
 2099              	.LBE101:
 2100              	.LBE100:
 2101              		.loc 1 671 14 discriminator 1 view .LVU590
 2102              	.L107:
 672:Library/src/lcm32f06x_acmp.c ****   }
 673:Library/src/lcm32f06x_acmp.c ****   else
 674:Library/src/lcm32f06x_acmp.c ****   {
 675:Library/src/lcm32f06x_acmp.c ****       sysctrl_access();
 676:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
 677:Library/src/lcm32f06x_acmp.c ****       __dekey();
 678:Library/src/lcm32f06x_acmp.c ****   }
 679:Library/src/lcm32f06x_acmp.c **** }
 2103              		.loc 1 679 1 is_stmt 0 view .LVU591
 2104              		@ sp needed
 2105 0020 7047     		bx	lr
 2106              	.L108:
 675:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
 2107              		.loc 1 675 7 is_stmt 1 view .LVU592
 2108              	.LBB102:
 2109              	.LBI102:
 258:Core/cmsis_gcc.h **** {
ARM GAS  /tmp/ccQ8FEb0.s 			page 75


 2110              		.loc 2 258 27 view .LVU593
 2111              	.LBB103:
 260:Core/cmsis_gcc.h **** }
 2112              		.loc 2 260 3 view .LVU594
 2113              		.syntax divided
 2114              	@ 260 "Core/cmsis_gcc.h" 1
 2115 0022 BFF36F8F 		isb 0xF
 2116              	@ 0 "" 2
 2117              		.thumb
 2118              		.syntax unified
 2119              	.LBE103:
 2120              	.LBE102:
 675:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
 2121              		.loc 1 675 7 discriminator 1 view .LVU595
 2122              	.LBB104:
 2123              	.LBI104:
1204:Core/cmsis_gcc.h **** {
 2124              		.loc 2 1204 31 view .LVU596
 2125              	.LBB105:
1206:Core/cmsis_gcc.h **** 
 2126              		.loc 2 1206 3 view .LVU597
1208:Core/cmsis_gcc.h ****   return(result);
 2127              		.loc 2 1208 3 view .LVU598
 2128              		.syntax divided
 2129              	@ 1208 "Core/cmsis_gcc.h" 1
 2130 0026 EFF31083 		MRS r3, primask
 2131              	@ 0 "" 2
 2132              	.LVL110:
 2133              		.loc 2 1209 3 view .LVU599
 2134              		.loc 2 1209 3 is_stmt 0 view .LVU600
 2135              		.thumb
 2136              		.syntax unified
 2137              	.LBE105:
 2138              	.LBE104:
 675:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
 2139              		.loc 1 675 7 is_stmt 1 discriminator 2 view .LVU601
 2140              	.LBB106:
 2141              	.LBI106:
 960:Core/cmsis_gcc.h **** {
 2142              		.loc 2 960 27 view .LVU602
 2143              	.LBB107:
 962:Core/cmsis_gcc.h **** }
 2144              		.loc 2 962 3 view .LVU603
 2145              		.syntax divided
 2146              	@ 962 "Core/cmsis_gcc.h" 1
 2147 002a 72B6     		cpsid i
 2148              	@ 0 "" 2
 2149              		.thumb
 2150              		.syntax unified
 2151              	.LBE107:
 2152              	.LBE106:
 675:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
 2153              		.loc 1 675 7 discriminator 3 view .LVU604
 2154 002c 044B     		ldr	r3, .L110
 2155 002e 054A     		ldr	r2, .L110+4
 2156 0030 1A60     		str	r2, [r3]
 675:Library/src/lcm32f06x_acmp.c ****       SYSCTRL->EDU_CFG15 &= (~(BlankingSource << 8));
ARM GAS  /tmp/ccQ8FEb0.s 			page 76


 2157              		.loc 1 675 23 discriminator 3 view .LVU605
 676:Library/src/lcm32f06x_acmp.c ****       __dekey();
 2158              		.loc 1 676 7 view .LVU606
 676:Library/src/lcm32f06x_acmp.c ****       __dekey();
 2159              		.loc 1 676 14 is_stmt 0 view .LVU607
 2160 0032 054A     		ldr	r2, .L110+8
 2161 0034 D36D     		ldr	r3, [r2, #92]
 676:Library/src/lcm32f06x_acmp.c ****       __dekey();
 2162              		.loc 1 676 26 view .LVU608
 2163 0036 8343     		bics	r3, r0
 2164 0038 D365     		str	r3, [r2, #92]
 677:Library/src/lcm32f06x_acmp.c ****   }
 2165              		.loc 1 677 7 is_stmt 1 view .LVU609
 2166              	.LBB108:
 2167              	.LBI108:
 949:Core/cmsis_gcc.h **** {
 2168              		.loc 2 949 27 view .LVU610
 2169              	.LBB109:
 951:Core/cmsis_gcc.h **** }
 2170              		.loc 2 951 3 view .LVU611
 2171              		.syntax divided
 2172              	@ 951 "Core/cmsis_gcc.h" 1
 2173 003a 62B6     		cpsie i
 2174              	@ 0 "" 2
 2175              		.thumb
 2176              		.syntax unified
 2177              	.LBE109:
 2178              	.LBE108:
 677:Library/src/lcm32f06x_acmp.c ****   }
 2179              		.loc 1 677 16 view .LVU612
 2180              		.loc 1 679 1 is_stmt 0 view .LVU613
 2181 003c F0E7     		b	.L107
 2182              	.L111:
 2183 003e C046     		.align	2
 2184              	.L110:
 2185 0040 7C700048 		.word	1207988348
 2186 0044 9A65FA05 		.word	100296090
 2187 0048 00700048 		.word	1207988224
 2188              		.cfi_endproc
 2189              	.LFE69:
 2191              		.section	.text.ACMP0_PollModeCfg,"ax",%progbits
 2192              		.align	1
 2193              		.p2align 2,,3
 2194              		.global	ACMP0_PollModeCfg
 2195              		.syntax unified
 2196              		.code	16
 2197              		.thumb_func
 2199              	ACMP0_PollModeCfg:
 2200              	.LVL111:
 2201              	.LFB70:
 680:Library/src/lcm32f06x_acmp.c **** /**
 681:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_PollModeCfg
 682:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 polling mode configuration.
 683:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 轮询模式配置。
 684:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_Mode: 
 685:Library/src/lcm32f06x_acmp.c ****   *         EN: Positive and negative selection of channel polling.
 686:Library/src/lcm32f06x_acmp.c ****   *         CN: 通道轮询的正负端选择。
ARM GAS  /tmp/ccQ8FEb0.s 			page 77


 687:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_MODE_POSITIVE
 688:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_MODE_NEGATIVE
 689:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_ChannelNum: 
 690:Library/src/lcm32f06x_acmp.c ****   *         EN: Polling comparison channel selection.
 691:Library/src/lcm32f06x_acmp.c ****   *         CN: 轮询比较通道数选择。
 692:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_1
 693:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_2
 694:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_3
 695:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_4
 696:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_OutputType: 
 697:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP Selection of external output results.
 698:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP 对外输出结果选择。
 699:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_Normal
 700:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ0
 701:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ1
 702:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ2
 703:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ3
 704:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ4
 705:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ5
 706:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ6
 707:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ7
 708:Library/src/lcm32f06x_acmp.c ****   * @retval None
 709:Library/src/lcm32f06x_acmp.c ****   */
 710:Library/src/lcm32f06x_acmp.c **** void ACMP0_PollModeCfg(uint32_t Poll_Mode, uint32_t Poll_ChannelNum, uint32_t Poll_OutputType)
 711:Library/src/lcm32f06x_acmp.c **** {
 2202              		.loc 1 711 1 is_stmt 1 view -0
 2203              		.cfi_startproc
 2204              		@ args = 0, pretend = 0, frame = 0
 2205              		@ frame_needed = 0, uses_anonymous_args = 0
 712:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL &= ~(ANACTRL_ACMPX_CHNLSEL_OUT_TYPE_Msk | \
 2206              		.loc 1 712 3 view .LVU615
 711:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL &= ~(ANACTRL_ACMPX_CHNLSEL_OUT_TYPE_Msk | \
 2207              		.loc 1 711 1 is_stmt 0 view .LVU616
 2208 0000 70B5     		push	{r4, r5, r6, lr}
 2209              	.LCFI11:
 2210              		.cfi_def_cfa_offset 16
 2211              		.cfi_offset 4, -16
 2212              		.cfi_offset 5, -12
 2213              		.cfi_offset 6, -8
 2214              		.cfi_offset 14, -4
 2215              		.loc 1 712 7 view .LVU617
 2216 0002 D824     		movs	r4, #216
 713:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 714:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_POLL_PS_Msk | \
 715:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNLSEL_OUT_Msk);
 716:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= Poll_Mode | Poll_ChannelNum | Poll_OutputType;
 717:Library/src/lcm32f06x_acmp.c **** }
 2217              		.loc 1 717 1 view .LVU618
 2218              		@ sp needed
 712:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2219              		.loc 1 712 7 view .LVU619
 2220 0004 054D     		ldr	r5, .L113
 712:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2221              		.loc 1 712 23 view .LVU620
 2222 0006 064E     		ldr	r6, .L113+4
 712:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2223              		.loc 1 712 7 view .LVU621
ARM GAS  /tmp/ccQ8FEb0.s 			page 78


 2224 0008 2B59     		ldr	r3, [r5, r4]
 712:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2225              		.loc 1 712 23 view .LVU622
 2226 000a 3340     		ands	r3, r6
 2227 000c 2B51     		str	r3, [r5, r4]
 716:Library/src/lcm32f06x_acmp.c **** }
 2228              		.loc 1 716 3 is_stmt 1 view .LVU623
 716:Library/src/lcm32f06x_acmp.c **** }
 2229              		.loc 1 716 7 is_stmt 0 view .LVU624
 2230 000e 2B59     		ldr	r3, [r5, r4]
 716:Library/src/lcm32f06x_acmp.c **** }
 2231              		.loc 1 716 23 view .LVU625
 2232 0010 1343     		orrs	r3, r2
 2233 0012 0B43     		orrs	r3, r1
 2234 0014 0343     		orrs	r3, r0
 2235 0016 2B51     		str	r3, [r5, r4]
 2236              		.loc 1 717 1 view .LVU626
 2237 0018 70BD     		pop	{r4, r5, r6, pc}
 2238              	.L114:
 2239 001a C046     		.align	2
 2240              	.L113:
 2241 001c 007C0140 		.word	1073839104
 2242 0020 FFFF0FEC 		.word	-334495745
 2243              		.cfi_endproc
 2244              	.LFE70:
 2246              		.section	.text.ACMP1_PollModeCfg,"ax",%progbits
 2247              		.align	1
 2248              		.p2align 2,,3
 2249              		.global	ACMP1_PollModeCfg
 2250              		.syntax unified
 2251              		.code	16
 2252              		.thumb_func
 2254              	ACMP1_PollModeCfg:
 2255              	.LVL112:
 2256              	.LFB71:
 718:Library/src/lcm32f06x_acmp.c **** 
 719:Library/src/lcm32f06x_acmp.c **** /**
 720:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_PollModeCfg
 721:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 polling mode configuration.
 722:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 轮询模式配置。
 723:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_Mode: 
 724:Library/src/lcm32f06x_acmp.c ****   *         EN: Positive and negative selection of channel polling.
 725:Library/src/lcm32f06x_acmp.c ****   *         CN: 通道轮询的正负端选择。
 726:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_MODE_POSITIVE
 727:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_MODE_NEGATIVE
 728:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_ChannelNum: 
 729:Library/src/lcm32f06x_acmp.c ****   *         EN: Polling comparison channel selection.
 730:Library/src/lcm32f06x_acmp.c ****   *         CN: 轮询比较通道数选择。
 731:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_1
 732:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_2
 733:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_3
 734:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_NUM_4
 735:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_OutputType: 
 736:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP Selection of external output results.
 737:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP 对外输出结果选择。
 738:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_Normal
 739:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ0
ARM GAS  /tmp/ccQ8FEb0.s 			page 79


 740:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ1
 741:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ2
 742:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ3
 743:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ4
 744:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ5
 745:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ6
 746:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_OUTTYPE_SEQ7
 747:Library/src/lcm32f06x_acmp.c ****   * @retval None
 748:Library/src/lcm32f06x_acmp.c ****   */
 749:Library/src/lcm32f06x_acmp.c **** void ACMP1_PollModeCfg(uint32_t Poll_Mode, uint32_t Poll_ChannelNum, uint32_t Poll_OutputType)
 750:Library/src/lcm32f06x_acmp.c **** {
 2257              		.loc 1 750 1 is_stmt 1 view -0
 2258              		.cfi_startproc
 2259              		@ args = 0, pretend = 0, frame = 0
 2260              		@ frame_needed = 0, uses_anonymous_args = 0
 751:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL &= ~(ANACTRL_ACMPX_CHNLSEL_OUT_TYPE_Msk | \
 2261              		.loc 1 751 3 view .LVU628
 750:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL &= ~(ANACTRL_ACMPX_CHNLSEL_OUT_TYPE_Msk | \
 2262              		.loc 1 750 1 is_stmt 0 view .LVU629
 2263 0000 70B5     		push	{r4, r5, r6, lr}
 2264              	.LCFI12:
 2265              		.cfi_def_cfa_offset 16
 2266              		.cfi_offset 4, -16
 2267              		.cfi_offset 5, -12
 2268              		.cfi_offset 6, -8
 2269              		.cfi_offset 14, -4
 2270              		.loc 1 751 7 view .LVU630
 2271 0002 DC24     		movs	r4, #220
 752:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 753:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_POLL_PS_Msk | \
 754:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNLSEL_OUT_Msk);
 755:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= Poll_Mode | Poll_ChannelNum | Poll_OutputType;
 756:Library/src/lcm32f06x_acmp.c **** }
 2272              		.loc 1 756 1 view .LVU631
 2273              		@ sp needed
 751:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2274              		.loc 1 751 7 view .LVU632
 2275 0004 054D     		ldr	r5, .L116
 751:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2276              		.loc 1 751 23 view .LVU633
 2277 0006 064E     		ldr	r6, .L116+4
 751:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2278              		.loc 1 751 7 view .LVU634
 2279 0008 2B59     		ldr	r3, [r5, r4]
 751:Library/src/lcm32f06x_acmp.c ****                            ANACTRL_ACMPX_CHNLSEL_CHNL_NUM_Msk | \
 2280              		.loc 1 751 23 view .LVU635
 2281 000a 3340     		ands	r3, r6
 2282 000c 2B51     		str	r3, [r5, r4]
 755:Library/src/lcm32f06x_acmp.c **** }
 2283              		.loc 1 755 3 is_stmt 1 view .LVU636
 755:Library/src/lcm32f06x_acmp.c **** }
 2284              		.loc 1 755 7 is_stmt 0 view .LVU637
 2285 000e 2B59     		ldr	r3, [r5, r4]
 755:Library/src/lcm32f06x_acmp.c **** }
 2286              		.loc 1 755 23 view .LVU638
 2287 0010 1343     		orrs	r3, r2
 2288 0012 0B43     		orrs	r3, r1
ARM GAS  /tmp/ccQ8FEb0.s 			page 80


 2289 0014 0343     		orrs	r3, r0
 2290 0016 2B51     		str	r3, [r5, r4]
 2291              		.loc 1 756 1 view .LVU639
 2292 0018 70BD     		pop	{r4, r5, r6, pc}
 2293              	.L117:
 2294 001a C046     		.align	2
 2295              	.L116:
 2296 001c 007C0140 		.word	1073839104
 2297 0020 FFFF0FEC 		.word	-334495745
 2298              		.cfi_endproc
 2299              	.LFE71:
 2301              		.section	.text.ACMP0_PollChannelSelxCfg,"ax",%progbits
 2302              		.align	1
 2303              		.p2align 2,,3
 2304              		.global	ACMP0_PollChannelSelxCfg
 2305              		.syntax unified
 2306              		.code	16
 2307              		.thumb_func
 2309              	ACMP0_PollChannelSelxCfg:
 2310              	.LVL113:
 2311              	.LFB72:
 757:Library/src/lcm32f06x_acmp.c **** 
 758:Library/src/lcm32f06x_acmp.c **** /**
 759:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP0_PollChannelSelxCfg
 760:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP0 Polling comparison channel position x channel selection selection.
 761:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP0 轮询比较通道位置 x 通道选择选择。
 762:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_Position: 
 763:Library/src/lcm32f06x_acmp.c ****   *         EN: Polling comparison channel position x selection.
 764:Library/src/lcm32f06x_acmp.c ****   *         CN: 轮询比较通道位置x选择。
 765:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_0
 766:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_1
 767:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_2
 768:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_3
 769:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_ChannelSel: 
 770:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP Polling comparison channel selection.
 771:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP 轮询比较通道选择。
 772:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_0
 773:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_1
 774:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_2
 775:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_3
 776:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_4
 777:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_5
 778:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_6
 779:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_7
 780:Library/src/lcm32f06x_acmp.c ****   * @retval None
 781:Library/src/lcm32f06x_acmp.c ****   */
 782:Library/src/lcm32f06x_acmp.c **** void ACMP0_PollChannelSelxCfg(uint32_t Poll_Position, uint32_t Poll_ChannelSel)
 783:Library/src/lcm32f06x_acmp.c **** {
 2312              		.loc 1 783 1 is_stmt 1 view -0
 2313              		.cfi_startproc
 2314              		@ args = 0, pretend = 0, frame = 0
 2315              		@ frame_needed = 0, uses_anonymous_args = 0
 784:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL &= ~(Poll_ChannelSel << Poll_Position);
 2316              		.loc 1 784 3 view .LVU641
 2317              		.loc 1 784 7 is_stmt 0 view .LVU642
 2318 0000 D823     		movs	r3, #216
 2319              		.loc 1 784 44 view .LVU643
ARM GAS  /tmp/ccQ8FEb0.s 			page 81


 2320 0002 8140     		lsls	r1, r1, r0
 2321              	.LVL114:
 2322              		.loc 1 784 7 view .LVU644
 2323 0004 044A     		ldr	r2, .L119
 783:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL &= ~(Poll_ChannelSel << Poll_Position);
 2324              		.loc 1 783 1 view .LVU645
 2325 0006 10B5     		push	{r4, lr}
 2326              	.LCFI13:
 2327              		.cfi_def_cfa_offset 8
 2328              		.cfi_offset 4, -8
 2329              		.cfi_offset 14, -4
 2330              		.loc 1 784 7 view .LVU646
 2331 0008 D458     		ldr	r4, [r2, r3]
 785:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 786:Library/src/lcm32f06x_acmp.c **** }
 2332              		.loc 1 786 1 view .LVU647
 2333              		@ sp needed
 784:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2334              		.loc 1 784 23 view .LVU648
 2335 000a 8C43     		bics	r4, r1
 2336 000c D450     		str	r4, [r2, r3]
 785:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2337              		.loc 1 785 3 is_stmt 1 view .LVU649
 785:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2338              		.loc 1 785 7 is_stmt 0 view .LVU650
 2339 000e D058     		ldr	r0, [r2, r3]
 2340              	.LVL115:
 785:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP0_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2341              		.loc 1 785 23 view .LVU651
 2342 0010 0143     		orrs	r1, r0
 2343 0012 D150     		str	r1, [r2, r3]
 2344              		.loc 1 786 1 view .LVU652
 2345 0014 10BD     		pop	{r4, pc}
 2346              	.L120:
 2347 0016 C046     		.align	2
 2348              	.L119:
 2349 0018 007C0140 		.word	1073839104
 2350              		.cfi_endproc
 2351              	.LFE72:
 2353              		.section	.text.ACMP1_PollChannelSelxCfg,"ax",%progbits
 2354              		.align	1
 2355              		.p2align 2,,3
 2356              		.global	ACMP1_PollChannelSelxCfg
 2357              		.syntax unified
 2358              		.code	16
 2359              		.thumb_func
 2361              	ACMP1_PollChannelSelxCfg:
 2362              	.LVL116:
 2363              	.LFB73:
 787:Library/src/lcm32f06x_acmp.c **** 
 788:Library/src/lcm32f06x_acmp.c **** /**
 789:Library/src/lcm32f06x_acmp.c ****   * @name   ACMP1_PollChannelSelxCfg
 790:Library/src/lcm32f06x_acmp.c ****   * @brief  EN: ACMP1 Polling comparison channel position x channel selection selection.
 791:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP1 轮询比较通道位置 x 通道选择选择。
 792:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_Position: 
 793:Library/src/lcm32f06x_acmp.c ****   *         EN: Polling comparison channel position x selection.
 794:Library/src/lcm32f06x_acmp.c ****   *         CN: 轮询比较通道位置x选择。
ARM GAS  /tmp/ccQ8FEb0.s 			page 82


 795:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_0
 796:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_1
 797:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_2
 798:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_POSITION_3
 799:Library/src/lcm32f06x_acmp.c ****   * @param  Poll_ChannelSel: 
 800:Library/src/lcm32f06x_acmp.c ****   *         EN: ACMP Polling comparison channel selection.
 801:Library/src/lcm32f06x_acmp.c ****   *         CN: ACMP 轮询比较通道选择。
 802:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_0
 803:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_1
 804:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_2
 805:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_3
 806:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_4
 807:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_5
 808:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_6
 809:Library/src/lcm32f06x_acmp.c ****   *             @arg POLL_CHANNEL_7
 810:Library/src/lcm32f06x_acmp.c ****   * @retval None
 811:Library/src/lcm32f06x_acmp.c ****   */
 812:Library/src/lcm32f06x_acmp.c **** void ACMP1_PollChannelSelxCfg(uint32_t Poll_Position, uint32_t Poll_ChannelSel)
 813:Library/src/lcm32f06x_acmp.c **** {
 2364              		.loc 1 813 1 is_stmt 1 view -0
 2365              		.cfi_startproc
 2366              		@ args = 0, pretend = 0, frame = 0
 2367              		@ frame_needed = 0, uses_anonymous_args = 0
 814:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL &= ~(Poll_ChannelSel << Poll_Position);
 2368              		.loc 1 814 3 view .LVU654
 2369              		.loc 1 814 7 is_stmt 0 view .LVU655
 2370 0000 DC23     		movs	r3, #220
 2371              		.loc 1 814 44 view .LVU656
 2372 0002 8140     		lsls	r1, r1, r0
 2373              	.LVL117:
 2374              		.loc 1 814 7 view .LVU657
 2375 0004 044A     		ldr	r2, .L122
 813:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL &= ~(Poll_ChannelSel << Poll_Position);
 2376              		.loc 1 813 1 view .LVU658
 2377 0006 10B5     		push	{r4, lr}
 2378              	.LCFI14:
 2379              		.cfi_def_cfa_offset 8
 2380              		.cfi_offset 4, -8
 2381              		.cfi_offset 14, -4
 2382              		.loc 1 814 7 view .LVU659
 2383 0008 D458     		ldr	r4, [r2, r3]
 815:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 816:Library/src/lcm32f06x_acmp.c **** }
 2384              		.loc 1 816 1 view .LVU660
 2385              		@ sp needed
 814:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2386              		.loc 1 814 23 view .LVU661
 2387 000a 8C43     		bics	r4, r1
 2388 000c D450     		str	r4, [r2, r3]
 815:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2389              		.loc 1 815 3 is_stmt 1 view .LVU662
 815:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2390              		.loc 1 815 7 is_stmt 0 view .LVU663
 2391 000e D058     		ldr	r0, [r2, r3]
 2392              	.LVL118:
 815:Library/src/lcm32f06x_acmp.c ****   ACMP->ACMP1_CHNLSEL |= (Poll_ChannelSel << Poll_Position);
 2393              		.loc 1 815 23 view .LVU664
ARM GAS  /tmp/ccQ8FEb0.s 			page 83


 2394 0010 0143     		orrs	r1, r0
 2395 0012 D150     		str	r1, [r2, r3]
 2396              		.loc 1 816 1 view .LVU665
 2397 0014 10BD     		pop	{r4, pc}
 2398              	.L123:
 2399 0016 C046     		.align	2
 2400              	.L122:
 2401 0018 007C0140 		.word	1073839104
 2402              		.cfi_endproc
 2403              	.LFE73:
 2405              		.text
 2406              	.Letext0:
 2407              		.file 3 "Library/inc/lcm32f06x.h"
 2408              		.file 4 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/machine/_default_types.h"
 2409              		.file 5 "/home/ha/toolchain/arm-gnu-toolchain-14.3/arm-none-eabi/include/sys/_stdint.h"
 2410              		.file 6 "Library/inc/lcm32f06x_acmp.h"
 2411              		.file 7 "Library/inc/lcm32f06x_rcc.h"
ARM GAS  /tmp/ccQ8FEb0.s 			page 84


DEFINED SYMBOLS
                            *ABS*:00000000 lcm32f06x_acmp.c
     /tmp/ccQ8FEb0.s:17     .text.ACMP_DeInit:00000000 $t
     /tmp/ccQ8FEb0.s:24     .text.ACMP_DeInit:00000000 ACMP_DeInit
     /tmp/ccQ8FEb0.s:56     .text.ACMP0_Init:00000000 $t
     /tmp/ccQ8FEb0.s:63     .text.ACMP0_Init:00000000 ACMP0_Init
     /tmp/ccQ8FEb0.s:326    .text.ACMP0_Init:000000c8 $d
     /tmp/ccQ8FEb0.s:337    .text.ACMP1_Init:00000000 $t
     /tmp/ccQ8FEb0.s:344    .text.ACMP1_Init:00000000 ACMP1_Init
     /tmp/ccQ8FEb0.s:613    .text.ACMP1_Init:000000cc $d
     /tmp/ccQ8FEb0.s:624    .text.ACMP_StructInit:00000000 $t
     /tmp/ccQ8FEb0.s:631    .text.ACMP_StructInit:00000000 ACMP_StructInit
     /tmp/ccQ8FEb0.s:696    .text.ACMP0_SoftWareTrigger:00000000 $t
     /tmp/ccQ8FEb0.s:703    .text.ACMP0_SoftWareTrigger:00000000 ACMP0_SoftWareTrigger
     /tmp/ccQ8FEb0.s:728    .text.ACMP0_SoftWareTrigger:00000010 $d
     /tmp/ccQ8FEb0.s:733    .text.ACMP1_SoftWareTrigger:00000000 $t
     /tmp/ccQ8FEb0.s:740    .text.ACMP1_SoftWareTrigger:00000000 ACMP1_SoftWareTrigger
     /tmp/ccQ8FEb0.s:765    .text.ACMP1_SoftWareTrigger:00000010 $d
     /tmp/ccQ8FEb0.s:770    .text.GET_ACMP0_SEQ_RESLUT:00000000 $t
     /tmp/ccQ8FEb0.s:777    .text.GET_ACMP0_SEQ_RESLUT:00000000 GET_ACMP0_SEQ_RESLUT
     /tmp/ccQ8FEb0.s:800    .text.GET_ACMP0_SEQ_RESLUT:0000000c $d
     /tmp/ccQ8FEb0.s:805    .text.GET_ACMP1_SEQ_RESLUT:00000000 $t
     /tmp/ccQ8FEb0.s:812    .text.GET_ACMP1_SEQ_RESLUT:00000000 GET_ACMP1_SEQ_RESLUT
     /tmp/ccQ8FEb0.s:835    .text.GET_ACMP1_SEQ_RESLUT:0000000c $d
     /tmp/ccQ8FEb0.s:840    .text.ACMP0_Cmd:00000000 $t
     /tmp/ccQ8FEb0.s:847    .text.ACMP0_Cmd:00000000 ACMP0_Cmd
     /tmp/ccQ8FEb0.s:883    .text.ACMP0_Cmd:00000018 $d
     /tmp/ccQ8FEb0.s:888    .text.ACMP1_Cmd:00000000 $t
     /tmp/ccQ8FEb0.s:895    .text.ACMP1_Cmd:00000000 ACMP1_Cmd
     /tmp/ccQ8FEb0.s:931    .text.ACMP1_Cmd:00000018 $d
     /tmp/ccQ8FEb0.s:936    .text.ACMP0_FREN_Cmd:00000000 $t
     /tmp/ccQ8FEb0.s:943    .text.ACMP0_FREN_Cmd:00000000 ACMP0_FREN_Cmd
     /tmp/ccQ8FEb0.s:979    .text.ACMP0_FREN_Cmd:00000018 $d
     /tmp/ccQ8FEb0.s:984    .text.ACMP1_FREN_Cmd:00000000 $t
     /tmp/ccQ8FEb0.s:991    .text.ACMP1_FREN_Cmd:00000000 ACMP1_FREN_Cmd
     /tmp/ccQ8FEb0.s:1027   .text.ACMP1_FREN_Cmd:00000018 $d
     /tmp/ccQ8FEb0.s:1032   .text.Acmp0_trim:00000000 $t
     /tmp/ccQ8FEb0.s:1039   .text.Acmp0_trim:00000000 Acmp0_trim
     /tmp/ccQ8FEb0.s:1069   .text.Acmp0_trim:00000010 $d
     /tmp/ccQ8FEb0.s:1075   .text.Acmp1_trim:00000000 $t
     /tmp/ccQ8FEb0.s:1082   .text.Acmp1_trim:00000000 Acmp1_trim
     /tmp/ccQ8FEb0.s:1112   .text.Acmp1_trim:00000010 $d
     /tmp/ccQ8FEb0.s:1118   .text.get_acmp0_trim:00000000 $t
     /tmp/ccQ8FEb0.s:1125   .text.get_acmp0_trim:00000000 get_acmp0_trim
     /tmp/ccQ8FEb0.s:1148   .text.get_acmp0_trim:0000000c $d
     /tmp/ccQ8FEb0.s:1153   .text.get_acmp1_trim:00000000 $t
     /tmp/ccQ8FEb0.s:1160   .text.get_acmp1_trim:00000000 get_acmp1_trim
     /tmp/ccQ8FEb0.s:1183   .text.get_acmp1_trim:0000000c $d
     /tmp/ccQ8FEb0.s:1188   .text.ACMP0_TrimInit:00000000 $t
     /tmp/ccQ8FEb0.s:1195   .text.ACMP0_TrimInit:00000000 ACMP0_TrimInit
     /tmp/ccQ8FEb0.s:1315   .text.ACMP0_TrimInit:00000048 $d
     /tmp/ccQ8FEb0.s:1321   .text.ACMP1_TrimInit:00000000 $t
     /tmp/ccQ8FEb0.s:1328   .text.ACMP1_TrimInit:00000000 ACMP1_TrimInit
     /tmp/ccQ8FEb0.s:1448   .text.ACMP1_TrimInit:00000048 $d
     /tmp/ccQ8FEb0.s:1454   .text.Hallmid_IP1_Config:00000000 $t
     /tmp/ccQ8FEb0.s:1461   .text.Hallmid_IP1_Config:00000000 Hallmid_IP1_Config
     /tmp/ccQ8FEb0.s:1524   .text.Hallmid_IP1_Config:00000030 $d
ARM GAS  /tmp/ccQ8FEb0.s 			page 85


     /tmp/ccQ8FEb0.s:1529   .text.Hallmid_IP2_Config:00000000 $t
     /tmp/ccQ8FEb0.s:1536   .text.Hallmid_IP2_Config:00000000 Hallmid_IP2_Config
     /tmp/ccQ8FEb0.s:1599   .text.Hallmid_IP2_Config:00000030 $d
     /tmp/ccQ8FEb0.s:1604   .text.Hallmid_IP3_Config:00000000 $t
     /tmp/ccQ8FEb0.s:1611   .text.Hallmid_IP3_Config:00000000 Hallmid_IP3_Config
     /tmp/ccQ8FEb0.s:1674   .text.Hallmid_IP3_Config:00000030 $d
     /tmp/ccQ8FEb0.s:1679   .text.Hallmid_Cmd:00000000 $t
     /tmp/ccQ8FEb0.s:1686   .text.Hallmid_Cmd:00000000 Hallmid_Cmd
     /tmp/ccQ8FEb0.s:1723   .text.Hallmid_Cmd:00000018 $d
     /tmp/ccQ8FEb0.s:1728   .text.ACMP_ANA_CVREFCfg:00000000 $t
     /tmp/ccQ8FEb0.s:1735   .text.ACMP_ANA_CVREFCfg:00000000 ACMP_ANA_CVREFCfg
     /tmp/ccQ8FEb0.s:1819   .text.ACMP_ANA_CVREFCfg:00000038 $d
     /tmp/ccQ8FEb0.s:1825   .text.ACMP0_BlankingCfg:00000000 $t
     /tmp/ccQ8FEb0.s:1832   .text.ACMP0_BlankingCfg:00000000 ACMP0_BlankingCfg
     /tmp/ccQ8FEb0.s:2000   .text.ACMP0_BlankingCfg:0000003c $d
     /tmp/ccQ8FEb0.s:2007   .text.ACMP1_BlankingCfg:00000000 $t
     /tmp/ccQ8FEb0.s:2014   .text.ACMP1_BlankingCfg:00000000 ACMP1_BlankingCfg
     /tmp/ccQ8FEb0.s:2185   .text.ACMP1_BlankingCfg:00000040 $d
     /tmp/ccQ8FEb0.s:2192   .text.ACMP0_PollModeCfg:00000000 $t
     /tmp/ccQ8FEb0.s:2199   .text.ACMP0_PollModeCfg:00000000 ACMP0_PollModeCfg
     /tmp/ccQ8FEb0.s:2241   .text.ACMP0_PollModeCfg:0000001c $d
     /tmp/ccQ8FEb0.s:2247   .text.ACMP1_PollModeCfg:00000000 $t
     /tmp/ccQ8FEb0.s:2254   .text.ACMP1_PollModeCfg:00000000 ACMP1_PollModeCfg
     /tmp/ccQ8FEb0.s:2296   .text.ACMP1_PollModeCfg:0000001c $d
     /tmp/ccQ8FEb0.s:2302   .text.ACMP0_PollChannelSelxCfg:00000000 $t
     /tmp/ccQ8FEb0.s:2309   .text.ACMP0_PollChannelSelxCfg:00000000 ACMP0_PollChannelSelxCfg
     /tmp/ccQ8FEb0.s:2349   .text.ACMP0_PollChannelSelxCfg:00000018 $d
     /tmp/ccQ8FEb0.s:2354   .text.ACMP1_PollChannelSelxCfg:00000000 $t
     /tmp/ccQ8FEb0.s:2361   .text.ACMP1_PollChannelSelxCfg:00000000 ACMP1_PollChannelSelxCfg
     /tmp/ccQ8FEb0.s:2401   .text.ACMP1_PollChannelSelxCfg:00000018 $d

UNDEFINED SYMBOLS
RCC_APB0PeriphResetCmd
